DE69432416D1 - Architektur-und beschaltungsschema für programmierbare logische schaltungen - Google Patents

Architektur-und beschaltungsschema für programmierbare logische schaltungen

Info

Publication number
DE69432416D1
DE69432416D1 DE69432416T DE69432416T DE69432416D1 DE 69432416 D1 DE69432416 D1 DE 69432416D1 DE 69432416 T DE69432416 T DE 69432416T DE 69432416 T DE69432416 T DE 69432416T DE 69432416 D1 DE69432416 D1 DE 69432416D1
Authority
DE
Germany
Prior art keywords
routing lines
cells
logical
architecture
logical circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69432416T
Other languages
English (en)
Inventor
S Ting
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BTR Inc
Original Assignee
BTR Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22283464&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69432416(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by BTR Inc filed Critical BTR Inc
Application granted granted Critical
Publication of DE69432416D1 publication Critical patent/DE69432416D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724Structural details of logic blocks
    • H03K19/17728Reconfigurable logic blocks, e.g. lookup tables
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736Structural details of routing resources
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778Structural details for adapting physical parameters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778Structural details for adapting physical parameters
    • H03K19/17796Structural details for adapting physical parameters for physical disposition of blocks
DE69432416T 1993-08-03 1994-06-24 Architektur-und beschaltungsschema für programmierbare logische schaltungen Expired - Lifetime DE69432416D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/101,197 US5457410A (en) 1993-08-03 1993-08-03 Architecture and interconnect scheme for programmable logic circuits
PCT/US1994/007187 WO1995004404A1 (en) 1993-08-03 1994-06-24 Architecture and interconnect scheme for programmable logic circuits

Publications (1)

Publication Number Publication Date
DE69432416D1 true DE69432416D1 (de) 2003-05-08

Family

ID=22283464

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69432416T Expired - Lifetime DE69432416D1 (de) 1993-08-03 1994-06-24 Architektur-und beschaltungsschema für programmierbare logische schaltungen
DE69431732T Expired - Lifetime DE69431732T2 (de) 1993-08-03 1994-06-24 Architektur und Verbindungsschema für programmierbare logische Schaltungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69431732T Expired - Lifetime DE69431732T2 (de) 1993-08-03 1994-06-24 Architektur und Verbindungsschema für programmierbare logische Schaltungen

Country Status (10)

Country Link
US (9) US5457410A (de)
EP (2) EP0712548B1 (de)
JP (2) JP4169164B2 (de)
KR (1) KR100413881B1 (de)
CN (1) CN1048127C (de)
AT (2) ATE236475T1 (de)
AU (1) AU7356294A (de)
DE (2) DE69432416D1 (de)
SG (1) SG55046A1 (de)
WO (1) WO1995004404A1 (de)

Families Citing this family (245)

* Cited by examiner, † Cited by third party
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