DE69434937D1 - Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie - Google Patents

Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie

Info

Publication number
DE69434937D1
DE69434937D1 DE69434937T DE69434937T DE69434937D1 DE 69434937 D1 DE69434937 D1 DE 69434937D1 DE 69434937 T DE69434937 T DE 69434937T DE 69434937 T DE69434937 T DE 69434937T DE 69434937 D1 DE69434937 D1 DE 69434937D1
Authority
DE
Germany
Prior art keywords
production
power components
mos technology
mos
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69434937T
Other languages
English (en)
Inventor
Giuseppe Ferla
Ferruccio Frisina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69434937D1 publication Critical patent/DE69434937D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69434937T 1994-06-23 1994-06-23 Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie Expired - Lifetime DE69434937D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830316A EP0689239B1 (de) 1994-06-23 1994-06-23 Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie

Publications (1)

Publication Number Publication Date
DE69434937D1 true DE69434937D1 (de) 2007-04-19

Family

ID=8218476

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69434937T Expired - Lifetime DE69434937D1 (de) 1994-06-23 1994-06-23 Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie

Country Status (4)

Country Link
US (2) US5933733A (de)
EP (1) EP0689239B1 (de)
JP (1) JP2618615B2 (de)
DE (1) DE69434937D1 (de)

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US6025231A (en) * 1997-02-18 2000-02-15 Texas Instruments Incorporated Self aligned DMOS transistor and method of fabrication
FR2767964B1 (fr) * 1997-09-04 2001-06-08 St Microelectronics Sa Procede de realisation de la zone de canal d'un transistor dmos
JP3429654B2 (ja) * 1997-12-24 2003-07-22 セイコーインスツルメンツ株式会社 半導体集積回路装置の製造方法
US6707103B1 (en) * 1998-03-05 2004-03-16 International Rectifier Corporation Low voltage rad hard MOSFET
DE19845003C1 (de) * 1998-09-30 2000-02-10 Siemens Ag Vertikaler Feldeffekttransistor mit innenliegendem ringförmigen Gate und Herstellverfahren
EP0999579B1 (de) 1998-11-04 2007-05-30 Lucent Technologies Inc. Induktivität oder Leiterbahn mit geringem Verlust in einer integrierten Schaltung
US6225182B1 (en) * 1999-08-30 2001-05-01 Agere Systems Guardian Corp. Simplified high Q inductor substrate
US6174778B1 (en) * 1998-12-15 2001-01-16 United Microelectronics Corp. Method of fabricating metal oxide semiconductor
US6624030B2 (en) 2000-12-19 2003-09-23 Advanced Power Devices, Inc. Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region
US20030030051A1 (en) 2001-08-09 2003-02-13 International Rectifier Corporation Superjunction device with improved avalanche capability and breakdown voltage
US7107040B2 (en) * 2002-02-11 2006-09-12 The Chamberlain Group, Inc. Method and apparatus for displaying blocked transmitter information
US6861303B2 (en) * 2003-05-09 2005-03-01 Texas Instruments Incorporated JFET structure for integrated circuit and fabrication method
JP4437655B2 (ja) * 2003-10-02 2010-03-24 三菱電機株式会社 半導体装置及び半導体装置の駆動回路
US7166890B2 (en) 2003-10-21 2007-01-23 Srikant Sridevan Superjunction device with improved ruggedness
KR100629605B1 (ko) * 2004-12-31 2006-09-27 동부일렉트로닉스 주식회사 엘디모스 채널 형성 방법
US7553734B2 (en) * 2005-10-17 2009-06-30 Princeton Lightwave, Inc. Method for forming an avalanche photodiode
JP4812480B2 (ja) * 2006-03-22 2011-11-09 富士通セミコンダクター株式会社 半導体装置の製造方法
KR100770538B1 (ko) 2006-08-09 2007-10-25 동부일렉트로닉스 주식회사 횡형 디모스 트랜지스터의 제조방법
US8274128B2 (en) * 2007-03-23 2012-09-25 Siliconix Technology C. V. Ir Semiconductor device with buffer layer
US10226818B2 (en) 2009-03-20 2019-03-12 Pratt & Whitney Canada Corp. Process for joining powder injection molded parts
US8525257B2 (en) * 2009-11-18 2013-09-03 Micrel, Inc. LDMOS transistor with asymmetric spacer as gate
US9722041B2 (en) 2012-09-19 2017-08-01 Vishay-Siliconix Breakdown voltage blocking device
US9970318B2 (en) 2014-06-25 2018-05-15 Pratt & Whitney Canada Corp. Shroud segment and method of manufacturing
DE102015118616B3 (de) * 2015-10-30 2017-04-13 Infineon Technologies Austria Ag Latchup-fester Transistor
JP6687476B2 (ja) * 2016-07-25 2020-04-22 株式会社日立製作所 半導体装置およびその製造方法
US11205718B1 (en) * 2018-11-26 2021-12-21 Texas Instruments Incorporated High performance super-beta NPN (SBNPN)
CN112117193B (zh) * 2020-09-21 2023-05-16 杭州芯迈半导体技术有限公司 碳化硅mosfet器件及其制造方法

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US3461360A (en) * 1965-06-30 1969-08-12 Ibm Semiconductor devices with cup-shaped regions
US4001860A (en) * 1973-11-12 1977-01-04 Signetics Corporation Double diffused metal oxide semiconductor structure with isolated source and drain and method
US3909320A (en) * 1973-12-26 1975-09-30 Signetics Corp Method for forming MOS structure using double diffusion
JPS5185381A (de) * 1975-01-24 1976-07-26 Hitachi Ltd
DE2703877C2 (de) * 1977-01-31 1982-06-03 Siemens Ag, 1000 Berlin Und 8000 Muenchen MIS-Transistor von kurzer Kanallänge und Verfahren zu seiner Herstellung
JPS53102668A (en) * 1977-02-18 1978-09-07 Toshiba Corp Manufacture for semiconductor device
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US4680853A (en) * 1980-08-18 1987-07-21 International Rectifier Corporation Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide
US4593302B1 (en) * 1980-08-18 1998-02-03 Int Rectifier Corp Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide
JPS59920A (ja) * 1982-06-23 1984-01-06 Fujitsu Ltd 半導体装置の製造方法
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
IT1213234B (it) * 1984-10-25 1989-12-14 Sgs Thomson Microelectronics Procedimento perfezionato per la fabbricazione di dispositivi a semiconduttore dmos.
JPS6251216A (ja) * 1985-08-30 1987-03-05 Toshiba Corp 半導体装置の製造方法
JPS62131579A (ja) * 1985-12-03 1987-06-13 Nec Corp 縦型電界効果トランジスタの製造方法
US4716126A (en) * 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
JPH0783122B2 (ja) * 1988-12-01 1995-09-06 富士電機株式会社 半導体装置の製造方法
JPH02239670A (ja) * 1989-03-14 1990-09-21 Fujitsu Ltd 半導体装置
JPH03105978A (ja) * 1989-09-20 1991-05-02 Hitachi Ltd 半導体装置
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor
JPH0831606B2 (ja) * 1989-11-17 1996-03-27 株式会社東芝 大電力用半導体装置
JPH03241747A (ja) * 1990-02-20 1991-10-28 Nissan Motor Co Ltd 半導体装置の製造方法
JPH0465132A (ja) * 1990-07-05 1992-03-02 Oki Electric Ind Co Ltd 二重拡散型ｍｏｓ　ｆｅｔの製造方法
EP0481153B1 (de) * 1990-10-16 1997-02-12 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom
JP2632101B2 (ja) * 1990-11-05 1997-07-23 三菱電機株式会社 半導体装置の製造方法
KR940004446B1 (ko) * 1990-11-05 1994-05-25 미쓰비시뎅끼 가부시끼가이샤 반도체장치의 제조방법
US5404040A (en) * 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
JPH05129602A (ja) * 1991-11-01 1993-05-25 Sony Corp Ｍｉｓ型半導体装置の製造方法
US5268586A (en) * 1992-02-25 1993-12-07 North American Philips Corporation Vertical power MOS device with increased ruggedness and method of fabrication
US5430314A (en) * 1992-04-23 1995-07-04 Siliconix Incorporated Power device with buffered gate shield region

Also Published As

Publication number Publication date
US5933733A (en) 1999-08-03
JP2618615B2 (ja) 1997-06-11
EP0689239B1 (de) 2007-03-07
JPH0817849A (ja) 1996-01-19
US6140679A (en) 2000-10-31
EP0689239A1 (de) 1995-12-27

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Legal Events

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8332 No legal effect for de