DE69506951T2 - Methode zur Bildung von Metallsilizidschichten auf Source- und Draingebiete - Google Patents

Methode zur Bildung von Metallsilizidschichten auf Source- und Draingebiete

Info

Publication number
DE69506951T2
DE69506951T2 DE69506951T DE69506951T DE69506951T2 DE 69506951 T2 DE69506951 T2 DE 69506951T2 DE 69506951 T DE69506951 T DE 69506951T DE 69506951 T DE69506951 T DE 69506951T DE 69506951 T2 DE69506951 T2 DE 69506951T2
Authority
DE
Germany
Prior art keywords
source
metal silicide
forming metal
silicide layers
drain areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69506951T
Other languages
English (en)
Other versions
DE69506951D1 (de
Inventor
Tohru Mogami
Toru Tatsumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69506951D1 publication Critical patent/DE69506951D1/de
Publication of DE69506951T2 publication Critical patent/DE69506951T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
DE69506951T 1994-06-21 1995-06-20 Methode zur Bildung von Metallsilizidschichten auf Source- und Draingebiete Expired - Fee Related DE69506951T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13882794 1994-06-21
JP7081185A JP2978736B2 (ja) 1994-06-21 1995-04-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69506951D1 DE69506951D1 (de) 1999-02-11
DE69506951T2 true DE69506951T2 (de) 1999-08-05

Family

ID=26422222

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69506951T Expired - Fee Related DE69506951T2 (de) 1994-06-21 1995-06-20 Methode zur Bildung von Metallsilizidschichten auf Source- und Draingebiete

Country Status (4)

Country Link
US (1) US5571735A (de)
EP (1) EP0689237B1 (de)
JP (1) JP2978736B2 (de)
DE (1) DE69506951T2 (de)

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US6720627B1 (en) * 1995-10-04 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device having junction depths for reducing short channel effect
JPH09260656A (ja) * 1996-03-25 1997-10-03 Toshiba Corp 半導体装置の製造方法
KR100250744B1 (ko) * 1996-06-21 2000-05-01 김영환 반도체 소자의 폴리사이드층 형성 방법
US5885896A (en) * 1996-07-08 1999-03-23 Micron Technology, Inc. Using implants to lower anneal temperatures
TW328153B (en) * 1996-08-09 1998-03-11 United Microelectronics Corp The manufacturing method for improving property of salicide
KR100234700B1 (ko) * 1996-11-27 1999-12-15 김영환 반도체 소자의 제조방법
US6214658B1 (en) * 1996-12-09 2001-04-10 Texas Instruments Incorporated Self-aligned contact structure and method
US5888888A (en) * 1997-01-29 1999-03-30 Ultratech Stepper, Inc. Method for forming a silicide region on a silicon body
JPH10223771A (ja) * 1997-02-12 1998-08-21 Yamaha Corp 半導体装置とその製造方法
KR100425147B1 (ko) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 반도체소자의제조방법
JP3389075B2 (ja) 1997-10-01 2003-03-24 株式会社東芝 半導体装置の製造方法
JP3104653B2 (ja) * 1997-10-15 2000-10-30 日本電気株式会社 半導体装置の製造方法
US6107154A (en) * 1998-05-12 2000-08-22 United Microelectronics Corp. Method of fabricating a semiconductor embedded dynamic random-access memory device
US6037204A (en) * 1998-08-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Silicon and arsenic double implanted pre-amorphization process for salicide technology
US6030863A (en) * 1998-09-11 2000-02-29 Taiwan Semiconductor Manufacturing Company Germanium and arsenic double implanted pre-amorphization process for salicide technology
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
US6255214B1 (en) * 1999-02-24 2001-07-03 Advanced Micro Devices, Inc. Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
US6117762A (en) * 1999-04-23 2000-09-12 Hrl Laboratories, Llc Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
KR100342394B1 (ko) * 2000-06-28 2002-07-02 황인길 반도체 소자의 제조 방법
US7217977B2 (en) 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6740942B2 (en) * 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6630394B2 (en) * 2001-12-28 2003-10-07 Texas Instruments Incorporated System for reducing silicon-consumption through selective deposition
US6897535B2 (en) 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
WO2004055868A2 (en) 2002-12-13 2004-07-01 Hrl Laboratories, Llc Integrated circuit modification using well implants
US6989302B2 (en) * 2003-05-05 2006-01-24 Texas Instruments Incorporated Method for fabricating a p-type shallow junction using diatomic arsenic
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
DE102005043913B4 (de) * 2004-09-22 2011-06-30 Infineon Technologies AG, 81669 Verfahren zur Herstellung einer dotierten Zone in einem Halbleiterkörper
US20070166936A1 (en) * 2006-01-19 2007-07-19 Po-Chao Tsao Pre-amorphization implantation process and salicide process
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
DE102006046363B4 (de) * 2006-09-29 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Verringern von Kristalldefekten in Transistoren mit wieder aufgewachsenen flachen Übergängen durch geeignetes Auswählen von Kristallorientierungen
JP5244364B2 (ja) 2007-10-16 2013-07-24 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
JP2015185583A (ja) * 2014-03-20 2015-10-22 旭化成エレクトロニクス株式会社 フューズ素子の製造方法及び半導体装置の製造方法、チタンシリサイド膜の製造方法

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JPS6014461A (ja) * 1983-07-04 1985-01-25 Hitachi Ltd 相補型絶縁ゲート電界効果トランジスタの製造方法
JPS60128656A (ja) * 1983-12-16 1985-07-09 Hitachi Ltd 半導体装置
JPS613461A (ja) * 1984-06-18 1986-01-09 Nec Corp 半導体装置の製造方法
US4648175A (en) * 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
JPH0291932A (ja) * 1988-09-28 1990-03-30 Fujitsu Ltd 半導体装置の製造方法
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
JPH04101433A (ja) * 1990-08-20 1992-04-02 Nec Corp 半導体装置の製造方法
US5156994A (en) 1990-12-21 1992-10-20 Texas Instruments Incorporated Local interconnect method and structure
US5236872A (en) * 1991-03-21 1993-08-17 U.S. Philips Corp. Method of manufacturing a semiconductor device having a semiconductor body with a buried silicide layer
JPH0661180A (ja) * 1992-08-03 1994-03-04 Yamaha Corp 電極形成法
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Also Published As

Publication number Publication date
JPH0870053A (ja) 1996-03-12
JP2978736B2 (ja) 1999-11-15
EP0689237B1 (de) 1998-12-30
EP0689237A1 (de) 1995-12-27
US5571735A (en) 1996-11-05
DE69506951D1 (de) 1999-02-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee