DE69524564D1 - Kohärenz- und synchronisationsmechanismus für ein-/ausgangkanalsteuereinheiten in einem datenverarbeitungssystem - Google Patents
Kohärenz- und synchronisationsmechanismus für ein-/ausgangkanalsteuereinheiten in einem datenverarbeitungssystemInfo
- Publication number
- DE69524564D1 DE69524564D1 DE69524564T DE69524564T DE69524564D1 DE 69524564 D1 DE69524564 D1 DE 69524564D1 DE 69524564 T DE69524564 T DE 69524564T DE 69524564 T DE69524564 T DE 69524564T DE 69524564 D1 DE69524564 D1 DE 69524564D1
- Authority
- DE
- Germany
- Prior art keywords
- operations
- coherence
- input
- data processing
- processing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/316,977 US5613153A (en) | 1994-10-03 | 1994-10-03 | Coherency and synchronization mechanisms for I/O channel controllers in a data processing system |
PCT/IB1995/000910 WO1996011430A2 (en) | 1994-10-03 | 1995-09-22 | Coherency and synchronization mechanism for i/o channel controllers in a data processing system |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69524564D1 true DE69524564D1 (de) | 2002-01-24 |
DE69524564T2 DE69524564T2 (de) | 2002-08-22 |
Family
ID=23231561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69524564T Expired - Fee Related DE69524564T2 (de) | 1994-10-03 | 1995-09-22 | Kohärenz- und synchronisationsmechanismus für ein-/ausgangkanalsteuereinheiten in einem datenverarbeitungssystem |
Country Status (8)
Country | Link |
---|---|
US (1) | US5613153A (de) |
EP (1) | EP0731944B1 (de) |
JP (1) | JP3280207B2 (de) |
KR (1) | KR0163231B1 (de) |
AT (1) | ATE210855T1 (de) |
DE (1) | DE69524564T2 (de) |
ES (1) | ES2164781T3 (de) |
WO (1) | WO1996011430A2 (de) |
Families Citing this family (84)
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US5790892A (en) * | 1995-09-29 | 1998-08-04 | International Business Machines Corporation | Information handling system for modifying coherency response set to allow intervention of a read command so that the intervention is not allowed by the system memory |
US5822553A (en) * | 1996-03-13 | 1998-10-13 | Diamond Multimedia Systems, Inc. | Multiple parallel digital data stream channel controller architecture |
US5797043A (en) * | 1996-03-13 | 1998-08-18 | Diamond Multimedia Systems, Inc. | System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs |
US5881303A (en) * | 1996-07-01 | 1999-03-09 | Sun Microsystems, Inc. | Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode |
TW386192B (en) * | 1997-04-14 | 2000-04-01 | Ibm | Method and system for speculatively sourcing cache memory data within a data-processing system |
US6078991A (en) * | 1997-04-14 | 2000-06-20 | International Business Machines Corporation | Method and system for speculatively requesting system data bus for sourcing cache memory data within a multiprocessor data-processing system |
US6061755A (en) * | 1997-04-14 | 2000-05-09 | International Business Machines Corporation | Method of layering cache and architectural specific functions to promote operation symmetry |
US5907712A (en) * | 1997-05-30 | 1999-05-25 | International Business Machines Corporation | Method for reducing processor interrupt processing time by transferring predetermined interrupt status to a system memory for eliminating PIO reads from the interrupt handler |
US6658537B2 (en) * | 1997-06-09 | 2003-12-02 | 3Com Corporation | DMA driven processor cache |
JPH11331890A (ja) * | 1998-05-08 | 1999-11-30 | Fujitsu Ltd | 情報処理システム |
US6163815A (en) * | 1998-05-27 | 2000-12-19 | International Business Machines Corporation | Dynamic disablement of a transaction ordering in response to an error |
US6108721A (en) * | 1998-06-29 | 2000-08-22 | Hewlett-Packard Company | Method and apparatus for ensuring data consistency between an i/o channel and a processor |
JP3858492B2 (ja) * | 1998-12-28 | 2006-12-13 | 株式会社日立製作所 | マルチプロセッサシステム |
US6338119B1 (en) * | 1999-03-31 | 2002-01-08 | International Business Machines Corporation | Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance |
US6792424B1 (en) | 1999-04-23 | 2004-09-14 | International Business Machines Corporation | System and method for managing authentication and coherency in a storage area network |
US6463553B1 (en) | 1999-10-01 | 2002-10-08 | Stmicroelectronics, Ltd. | Microcomputer debug architecture and method |
US7260745B1 (en) | 1999-10-01 | 2007-08-21 | Stmicroelectronics Ltd. | Detection of information on an interconnect |
US6629207B1 (en) | 1999-10-01 | 2003-09-30 | Hitachi, Ltd. | Method for loading instructions or data into a locked way of a cache memory |
US6615370B1 (en) | 1999-10-01 | 2003-09-02 | Hitachi, Ltd. | Circuit for storing trace information |
US6349371B1 (en) | 1999-10-01 | 2002-02-19 | Stmicroelectronics Ltd. | Circuit for storing information |
US6684348B1 (en) | 1999-10-01 | 2004-01-27 | Hitachi, Ltd. | Circuit for processing trace information |
US6693914B1 (en) | 1999-10-01 | 2004-02-17 | Stmicroelectronics, Inc. | Arbitration mechanism for packet transmission |
US6633971B2 (en) | 1999-10-01 | 2003-10-14 | Hitachi, Ltd. | Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline |
US6732307B1 (en) | 1999-10-01 | 2004-05-04 | Hitachi, Ltd. | Apparatus and method for storing trace information |
US6567932B2 (en) | 1999-10-01 | 2003-05-20 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US7793261B1 (en) | 1999-10-01 | 2010-09-07 | Stmicroelectronics Limited | Interface for transferring debug information |
US6530047B1 (en) | 1999-10-01 | 2003-03-04 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6542983B1 (en) | 1999-10-01 | 2003-04-01 | Hitachi, Ltd. | Microcomputer/floating point processor interface and method |
US6449712B1 (en) | 1999-10-01 | 2002-09-10 | Hitachi, Ltd. | Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions |
US6546480B1 (en) | 1999-10-01 | 2003-04-08 | Hitachi, Ltd. | Instructions for arithmetic operations on vectored data |
US6665816B1 (en) | 1999-10-01 | 2003-12-16 | Stmicroelectronics Limited | Data shift register |
JP2001142692A (ja) * | 1999-10-01 | 2001-05-25 | Hitachi Ltd | 2つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法 |
US6601189B1 (en) | 1999-10-01 | 2003-07-29 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6591369B1 (en) | 1999-10-01 | 2003-07-08 | Stmicroelectronics, Ltd. | System and method for communicating with an integrated circuit |
US6598177B1 (en) | 1999-10-01 | 2003-07-22 | Stmicroelectronics Ltd. | Monitoring error conditions in an integrated circuit |
US6412043B1 (en) | 1999-10-01 | 2002-06-25 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US7072817B1 (en) | 1999-10-01 | 2006-07-04 | Stmicroelectronics Ltd. | Method of designing an initiator in an integrated circuit |
US6826191B1 (en) | 1999-10-01 | 2004-11-30 | Stmicroelectronics Ltd. | Packets containing transaction attributes |
US7000078B1 (en) * | 1999-10-01 | 2006-02-14 | Stmicroelectronics Ltd. | System and method for maintaining cache coherency in a shared memory system |
US6779145B1 (en) | 1999-10-01 | 2004-08-17 | Stmicroelectronics Limited | System and method for communicating with an integrated circuit |
US6820195B1 (en) | 1999-10-01 | 2004-11-16 | Hitachi, Ltd. | Aligning load/store data with big/little endian determined rotation distance control |
US6408381B1 (en) | 1999-10-01 | 2002-06-18 | Hitachi, Ltd. | Mechanism for fast access to control space in a pipeline processor |
US6590907B1 (en) | 1999-10-01 | 2003-07-08 | Stmicroelectronics Ltd. | Integrated circuit with additional ports |
US6859891B2 (en) | 1999-10-01 | 2005-02-22 | Stmicroelectronics Limited | Apparatus and method for shadowing processor information |
US6772325B1 (en) * | 1999-10-01 | 2004-08-03 | Hitachi, Ltd. | Processor architecture and operation for exploiting improved branch control instruction |
US6298394B1 (en) | 1999-10-01 | 2001-10-02 | Stmicroelectronics, Ltd. | System and method for capturing information on an interconnect in an integrated circuit |
US6928073B2 (en) * | 1999-10-01 | 2005-08-09 | Stmicroelectronics Ltd. | Integrated circuit implementing packet transmission |
US6351803B2 (en) | 1999-10-01 | 2002-02-26 | Hitachi Ltd. | Mechanism for power efficient processing in a pipeline processor |
US6457118B1 (en) | 1999-10-01 | 2002-09-24 | Hitachi Ltd | Method and system for selecting and using source operands in computer system instructions |
US6487683B1 (en) | 1999-10-01 | 2002-11-26 | Stmicroelectronics Limited | Microcomputer debug architecture and method |
US6918065B1 (en) | 1999-10-01 | 2005-07-12 | Hitachi, Ltd. | Method for compressing and decompressing trace information |
US6553460B1 (en) | 1999-10-01 | 2003-04-22 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US6434665B1 (en) | 1999-10-01 | 2002-08-13 | Stmicroelectronics, Inc. | Cache memory store buffer |
US6460174B1 (en) | 1999-10-01 | 2002-10-01 | Stmicroelectronics, Ltd. | Methods and models for use in designing an integrated circuit |
US6412047B2 (en) | 1999-10-01 | 2002-06-25 | Stmicroelectronics, Inc. | Coherency protocol |
US7266728B1 (en) | 1999-10-01 | 2007-09-04 | Stmicroelectronics Ltd. | Circuit for monitoring information on an interconnect |
US6502210B1 (en) | 1999-10-01 | 2002-12-31 | Stmicroelectronics, Ltd. | Microcomputer debug architecture and method |
US6574651B1 (en) | 1999-10-01 | 2003-06-03 | Hitachi, Ltd. | Method and apparatus for arithmetic operation on vectored data |
US6598128B1 (en) | 1999-10-01 | 2003-07-22 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
US6557119B1 (en) | 1999-10-01 | 2003-04-29 | Stmicroelectronics Limited | Microcomputer debug architecture and method |
US6701405B1 (en) | 1999-10-01 | 2004-03-02 | Hitachi, Ltd. | DMA handshake protocol |
US6629115B1 (en) | 1999-10-01 | 2003-09-30 | Hitachi, Ltd. | Method and apparatus for manipulating vectored data |
US6643717B1 (en) | 1999-11-10 | 2003-11-04 | Digi International Inc. | Flow control |
US6629164B1 (en) | 1999-11-10 | 2003-09-30 | Digi International Inc. | Character counter and match registers in a serial interface |
US6886063B1 (en) | 1999-11-10 | 2005-04-26 | Digi International, Inc. | Systems, devices, structures, and methods to share resources among entities |
US6681320B1 (en) | 1999-12-29 | 2004-01-20 | Intel Corporation | Causality-based memory ordering in a multiprocessing environment |
US6785759B1 (en) | 2000-05-10 | 2004-08-31 | International Business Machines Corporation | System and method for sharing I/O address translation caching across multiple host bridges |
US6502169B1 (en) * | 2000-06-27 | 2002-12-31 | Adaptec, Inc. | System and method for detection of disk storage blocks containing unique values |
US6928593B1 (en) | 2000-09-18 | 2005-08-09 | Intel Corporation | Memory module and memory component built-in self test |
US6681292B2 (en) | 2001-08-27 | 2004-01-20 | Intel Corporation | Distributed read and write caching implementation for optimized input/output applications |
US20030041215A1 (en) * | 2001-08-27 | 2003-02-27 | George Robert T. | Method and apparatus for the utilization of distributed caches |
US6944721B2 (en) * | 2002-08-08 | 2005-09-13 | International Business Machines Corporation | Asynchronous non-blocking snoop invalidation |
US7318074B2 (en) * | 2003-11-17 | 2008-01-08 | International Business Machines Corporation | System and method for achieving deferred invalidation consistency |
US9753754B2 (en) * | 2004-12-22 | 2017-09-05 | Microsoft Technology Licensing, Llc | Enforcing deterministic execution of threads of guest operating systems running in a virtual machine hosted on a multiprocessor machine |
US20060143517A1 (en) * | 2004-12-22 | 2006-06-29 | Microsoft Corporation | Replicated virtual machine |
US20060236039A1 (en) * | 2005-04-19 | 2006-10-19 | International Business Machines Corporation | Method and apparatus for synchronizing shared data between components in a group |
US7350034B2 (en) * | 2005-06-20 | 2008-03-25 | International Business Machines Corporation | Architecture support of best-effort atomic transactions for multiprocessor systems |
US20070113031A1 (en) * | 2005-11-16 | 2007-05-17 | International Business Machines Corporation | Memory management system and method for storing and retrieving messages |
US20080301376A1 (en) * | 2007-05-31 | 2008-12-04 | Allison Brian D | Method, Apparatus, and System Supporting Improved DMA Writes |
US10152427B2 (en) | 2016-08-12 | 2018-12-11 | Google Llc | Hybrid memory management |
US10037173B2 (en) * | 2016-08-12 | 2018-07-31 | Google Llc | Hybrid memory management |
CN106886368B (zh) * | 2016-12-30 | 2019-08-16 | 北京同有飞骥科技股份有限公司 | 一种块设备写io整形和多控制器同步系统及同步方法 |
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US5045996A (en) * | 1986-11-12 | 1991-09-03 | Xerox Corporation | Multiprocessor cache memory housekeeping |
US5175826A (en) * | 1988-05-26 | 1992-12-29 | Ibm Corporation | Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 |
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US5097532A (en) * | 1989-03-03 | 1992-03-17 | Compaq Computer Corporation | Circuit for enabling a cache using a flush input to circumvent a late noncachable address input |
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US5434997A (en) * | 1992-10-02 | 1995-07-18 | Compaq Computer Corp. | Method and apparatus for testing and debugging a tightly coupled mirrored processing system |
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-
1994
- 1994-10-03 US US08/316,977 patent/US5613153A/en not_active Expired - Lifetime
-
1995
- 1995-09-22 EP EP95933585A patent/EP0731944B1/de not_active Expired - Lifetime
- 1995-09-22 ES ES95933585T patent/ES2164781T3/es not_active Expired - Lifetime
- 1995-09-22 DE DE69524564T patent/DE69524564T2/de not_active Expired - Fee Related
- 1995-09-22 WO PCT/IB1995/000910 patent/WO1996011430A2/en active IP Right Grant
- 1995-09-22 AT AT95933585T patent/ATE210855T1/de not_active IP Right Cessation
- 1995-09-29 JP JP25229495A patent/JP3280207B2/ja not_active Expired - Fee Related
- 1995-09-30 KR KR1019950033597A patent/KR0163231B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH08115260A (ja) | 1996-05-07 |
EP0731944B1 (de) | 2001-12-12 |
US5613153A (en) | 1997-03-18 |
ES2164781T3 (es) | 2002-03-01 |
ATE210855T1 (de) | 2001-12-15 |
WO1996011430A3 (en) | 1996-07-18 |
KR960015275A (ko) | 1996-05-22 |
EP0731944A1 (de) | 1996-09-18 |
DE69524564T2 (de) | 2002-08-22 |
WO1996011430A2 (en) | 1996-04-18 |
KR0163231B1 (ko) | 1999-01-15 |
JP3280207B2 (ja) | 2002-04-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |