DE69528085T2 - Intergrierte Halbleiterschaltung mit zwei Versorgungsspannungen - Google Patents
Intergrierte Halbleiterschaltung mit zwei VersorgungsspannungenInfo
- Publication number
- DE69528085T2 DE69528085T2 DE69528085T DE69528085T DE69528085T2 DE 69528085 T2 DE69528085 T2 DE 69528085T2 DE 69528085 T DE69528085 T DE 69528085T DE 69528085 T DE69528085 T DE 69528085T DE 69528085 T2 DE69528085 T2 DE 69528085T2
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor circuit
- supply voltages
- integrated semiconductor
- integrated
- voltages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP402494 | 1994-01-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69528085D1 DE69528085D1 (de) | 2002-10-10 |
| DE69528085T2 true DE69528085T2 (de) | 2003-01-02 |
Family
ID=11573400
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69527814T Expired - Lifetime DE69527814T2 (de) | 1994-01-19 | 1995-01-18 | Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
| DE69528085T Expired - Lifetime DE69528085T2 (de) | 1994-01-19 | 1995-01-18 | Intergrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
| DE69528084T Expired - Lifetime DE69528084T2 (de) | 1994-01-19 | 1995-01-18 | Verfahren zum Entwurf einer integrierten Halbleiter-Schaltung |
| DE69526811T Expired - Lifetime DE69526811T2 (de) | 1994-01-19 | 1995-01-18 | Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69527814T Expired - Lifetime DE69527814T2 (de) | 1994-01-19 | 1995-01-18 | Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69528084T Expired - Lifetime DE69528084T2 (de) | 1994-01-19 | 1995-01-18 | Verfahren zum Entwurf einer integrierten Halbleiter-Schaltung |
| DE69526811T Expired - Lifetime DE69526811T2 (de) | 1994-01-19 | 1995-01-18 | Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US5517132A (de) |
| EP (4) | EP0862127B1 (de) |
| KR (1) | KR0181550B1 (de) |
| CN (3) | CN1099704C (de) |
| DE (4) | DE69527814T2 (de) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612892A (en) * | 1993-12-16 | 1997-03-18 | Intel Corporation | Method and structure for improving power consumption on a component while maintaining high operating frequency |
| DE69527814T2 (de) | 1994-01-19 | 2002-12-12 | Matsushita Electric Ind Co Ltd | Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
| JP2776262B2 (ja) * | 1994-08-18 | 1998-07-16 | 日本電気株式会社 | 論理回路合成方法及び装置 |
| TW305958B (de) * | 1995-05-26 | 1997-05-21 | Matsushita Electric Ind Co Ltd | |
| US5963730A (en) * | 1995-09-26 | 1999-10-05 | Matsushita Electric Industrial Co., Ltd. | Method for automating top-down design processing for the design of LSI functions and LSI mask layouts |
| US5815004A (en) * | 1995-10-16 | 1998-09-29 | Xilinx, Inc. | Multi-buffered configurable logic block output lines in a field programmable gate array |
| US5923569A (en) | 1995-10-17 | 1999-07-13 | Matsushita Electric Industrial Co., Ltd. | Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof |
| US6750527B1 (en) * | 1996-05-30 | 2004-06-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method |
| US5798938A (en) * | 1996-07-02 | 1998-08-25 | Hewlett-Packard Co. | System and method for verification of a precharge critical path for a system of cascaded dynamic logic gates |
| JPH1063703A (ja) * | 1996-08-26 | 1998-03-06 | Toshiba Corp | 低消費電力回路設計方法 |
| US6151568A (en) * | 1996-09-13 | 2000-11-21 | Sente, Inc. | Power estimation software system |
| JPH10163843A (ja) * | 1996-12-04 | 1998-06-19 | Toshiba Corp | 組み合わせ論理回路及びその設計方法 |
| US6269468B1 (en) | 1999-03-02 | 2001-07-31 | International Business Machines Corporation | Split I/O circuit for performance optimization of digital circuits |
| WO2001056159A1 (fr) * | 2000-01-27 | 2001-08-02 | Hitachi, Ltd. | Dispositif a semiconducteur |
| US6539534B1 (en) * | 2000-08-25 | 2003-03-25 | Xilinx, Inc. | Apparatus and method for automatically generating circuit designs that meet user output requirements |
| US6792582B1 (en) * | 2000-11-15 | 2004-09-14 | International Business Machines Corporation | Concurrent logical and physical construction of voltage islands for mixed supply voltage designs |
| JP2002190572A (ja) * | 2000-12-20 | 2002-07-05 | Fujitsu Ltd | 半導体装置、レイアウトデータ設計装置、及び記録媒体 |
| US6728939B2 (en) * | 2001-01-08 | 2004-04-27 | Siemens Aktiengesellschaft | Method of circuit verification in digital design |
| JP4082653B2 (ja) * | 2001-11-15 | 2008-04-30 | 松下電器産業株式会社 | 高位合成方法および高位合成装置 |
| US7205684B2 (en) * | 2002-11-18 | 2007-04-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for designing the same |
| US7089510B2 (en) * | 2003-11-24 | 2006-08-08 | International Business Machines Corp. | Method and program product of level converter optimization |
| US7111266B2 (en) * | 2003-11-24 | 2006-09-19 | International Business Machines Corp. | Multiple voltage integrated circuit and design method therefor |
| US7146471B2 (en) * | 2003-12-31 | 2006-12-05 | International Business Machines Corp. | System and method for variable array architecture for memories |
| US9220180B2 (en) | 2010-12-09 | 2015-12-22 | Richard Anthony Dunn, JR. | System and methods for scalable parallel data processing and process control |
| CN102859680A (zh) | 2011-02-21 | 2013-01-02 | 松下电器产业株式会社 | 集成电路 |
| JP5772492B2 (ja) | 2011-10-21 | 2015-09-02 | 富士通株式会社 | 演算処理装置 |
| CN102611431B (zh) * | 2012-03-08 | 2014-12-24 | 无锡华大国奇科技有限公司 | 带组合逻辑通路的寄存器 |
| JP6056632B2 (ja) | 2013-04-22 | 2017-01-11 | 富士通株式会社 | データ保持回路、及び、半導体集積回路装置 |
| DE102019208983A1 (de) * | 2019-06-19 | 2020-12-24 | Robert Bosch Gmbh | Speichervorrichtung zur Speicherung mindestens einer Information in einem bestimmten logischen Zustand |
| KR20210045075A (ko) | 2019-10-16 | 2021-04-26 | 삼성전자주식회사 | 반도체 장치 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3950636A (en) | 1974-01-16 | 1976-04-13 | Signetics Corporation | High speed multiplier logic circuit |
| US4080539A (en) * | 1976-11-10 | 1978-03-21 | Rca Corporation | Level shift circuit |
| JPS57162838A (en) * | 1981-03-31 | 1982-10-06 | Fujitsu Ltd | Emitter coupling type logical circuit |
| JPS59116790A (ja) * | 1982-12-24 | 1984-07-05 | シチズン時計株式会社 | マトリクス型表示装置の駆動回路 |
| US5245224A (en) * | 1983-01-31 | 1993-09-14 | Hitachi, Ltd. | Level conversion circuitry for a semiconductor integrated circuit |
| JPH0795395B2 (ja) | 1984-02-13 | 1995-10-11 | 株式会社日立製作所 | 半導体集積回路 |
| JPS62500764A (ja) * | 1984-11-02 | 1987-03-26 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | 異なるロジックファミリのレベルにおいて入力を受取りかつ出力を与える集積回路装置 |
| JPS62189739A (ja) * | 1986-02-17 | 1987-08-19 | Hitachi Ltd | 半導体集積回路装置 |
| US5187385A (en) * | 1986-08-29 | 1993-02-16 | Kabushiki Kaisha Toshiba | Latch circuit including filter for metastable prevention |
| US5115408A (en) | 1988-01-29 | 1992-05-19 | Texas Instruments Incorporated | High speed multiplier |
| US5175693A (en) * | 1989-06-01 | 1992-12-29 | Kabushiki Kaisha Toshiba | Method of designing semiconductor integrated circuit device |
| US4978633A (en) * | 1989-08-22 | 1990-12-18 | Harris Corporation | Hierarchical variable die size gate array architecture |
| US5541849A (en) | 1990-04-06 | 1996-07-30 | Lsi Logic Corporation | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters |
| US5218551A (en) * | 1990-04-30 | 1993-06-08 | International Business Machines Corporation | Timing driven placement |
| JPH0496369A (ja) * | 1990-08-13 | 1992-03-27 | Kawasaki Steel Corp | ゲートアレー型ｌｓｉ |
| JP3079515B2 (ja) * | 1991-01-29 | 2000-08-21 | 株式会社東芝 | ゲ−トアレイ装置及び入力回路及び出力回路及び降圧回路 |
| JPH04288865A (ja) | 1991-03-06 | 1992-10-13 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JP2674353B2 (ja) * | 1991-04-04 | 1997-11-12 | 日本電気株式会社 | 概略配線処理方式 |
| US5132577A (en) | 1991-04-11 | 1992-07-21 | National Semiconductor Corporation | High speed passgate, latch and flip-flop circuits |
| JP3172211B2 (ja) * | 1991-09-05 | 2001-06-04 | 富士通株式会社 | 回路合成システム |
| JPH0567963A (ja) * | 1991-09-06 | 1993-03-19 | Hitachi Ltd | 論理集積回路 |
| JPH05299624A (ja) * | 1992-04-23 | 1993-11-12 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JP2739013B2 (ja) * | 1992-09-01 | 1998-04-08 | 三菱電機株式会社 | 論理合成装置 |
| US5311083A (en) | 1993-01-25 | 1994-05-10 | Standard Microsystems Corporation | Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads |
| US5300835A (en) | 1993-02-10 | 1994-04-05 | Cirrus Logic, Inc. | CMOS low power mixed voltage bidirectional I/O buffer |
| JP3335700B2 (ja) * | 1993-03-30 | 2002-10-21 | 富士通株式会社 | レベルコンバータ及び半導体集積回路 |
| US5432467A (en) * | 1993-05-07 | 1995-07-11 | Altera Corporation | Programmable logic device with low power voltage level translator |
| US5408138A (en) * | 1993-10-04 | 1995-04-18 | Motorola, Inc. | Flip flop circuit and method therefor |
| DE69527814T2 (de) | 1994-01-19 | 2002-12-12 | Matsushita Electric Ind Co Ltd | Integrierte Halbleiterschaltung mit zwei Versorgungsspannungen |
| US5557533A (en) | 1994-04-19 | 1996-09-17 | Lsi Logic Corporation | Cell placement alteration apparatus for integrated circuit chip physical design automation system |
| TW265489B (en) * | 1994-07-20 | 1995-12-11 | Micron Technology Inc | Low-to-high voltage cmos driver circuit for driving capacitive loads |
| US5594368A (en) | 1995-04-19 | 1997-01-14 | Kabushiki Kaisha Toshiba | Low power combinational logic circuit |
-
1995
- 1995-01-18 DE DE69527814T patent/DE69527814T2/de not_active Expired - Lifetime
- 1995-01-18 EP EP98107361A patent/EP0862127B1/de not_active Expired - Lifetime
- 1995-01-18 US US08/375,413 patent/US5517132A/en not_active Ceased
- 1995-01-18 DE DE69528085T patent/DE69528085T2/de not_active Expired - Lifetime
- 1995-01-18 CN CN95101330A patent/CN1099704C/zh not_active Expired - Fee Related
- 1995-01-18 DE DE69528084T patent/DE69528084T2/de not_active Expired - Lifetime
- 1995-01-18 DE DE69526811T patent/DE69526811T2/de not_active Expired - Lifetime
- 1995-01-18 EP EP95100625A patent/EP0664517B1/de not_active Expired - Lifetime
- 1995-01-18 EP EP98107369A patent/EP0863472B1/de not_active Expired - Lifetime
- 1995-01-18 EP EP98107368A patent/EP0863471B1/de not_active Expired - Lifetime
- 1995-01-18 CN CNB981163505A patent/CN1170242C/zh not_active Expired - Fee Related
- 1995-01-19 KR KR1019950000821A patent/KR0181550B1/ko not_active IP Right Cessation
-
1998
- 1998-05-13 US US09/076,703 patent/USRE37475E1/en not_active Expired - Lifetime
- 1998-07-22 CN CNB981163513A patent/CN1172256C/zh not_active Expired - Fee Related
-
2000
- 2000-09-08 US US09/656,040 patent/USRE38152E1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| USRE38152E1 (en) | 2003-06-24 |
| DE69527814T2 (de) | 2002-12-12 |
| CN1221984A (zh) | 1999-07-07 |
| EP0863472B1 (de) | 2002-08-14 |
| EP0862127A2 (de) | 1998-09-02 |
| KR0181550B1 (ko) | 1999-04-15 |
| DE69526811T2 (de) | 2002-09-12 |
| EP0664517B1 (de) | 2002-05-29 |
| EP0863471B1 (de) | 2002-09-04 |
| EP0664517A2 (de) | 1995-07-26 |
| EP0863471A3 (de) | 1999-02-17 |
| KR950024305A (ko) | 1995-08-21 |
| EP0664517A3 (de) | 1996-07-24 |
| EP0863471A2 (de) | 1998-09-09 |
| CN1221923A (zh) | 1999-07-07 |
| EP0863472A3 (de) | 1999-02-10 |
| DE69527814D1 (de) | 2002-09-19 |
| CN1170242C (zh) | 2004-10-06 |
| EP0862127A3 (de) | 1999-02-17 |
| EP0862127B1 (de) | 2002-09-04 |
| DE69528084T2 (de) | 2003-01-02 |
| EP0863472A2 (de) | 1998-09-09 |
| DE69526811D1 (de) | 2002-07-04 |
| USRE37475E1 (en) | 2001-12-18 |
| DE69528085D1 (de) | 2002-10-10 |
| CN1113037A (zh) | 1995-12-06 |
| CN1172256C (zh) | 2004-10-20 |
| CN1099704C (zh) | 2003-01-22 |
| DE69528084D1 (de) | 2002-10-10 |
| US5517132A (en) | 1996-05-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORP., KADOMA, OSAKA, JP |