DE69602932T2 - Multitor ram zur anwendung in einem viterbidecoder - Google Patents
Multitor ram zur anwendung in einem viterbidecoderInfo
- Publication number
- DE69602932T2 DE69602932T2 DE69602932T DE69602932T DE69602932T2 DE 69602932 T2 DE69602932 T2 DE 69602932T2 DE 69602932 T DE69602932 T DE 69602932T DE 69602932 T DE69602932 T DE 69602932T DE 69602932 T2 DE69602932 T2 DE 69602932T2
- Authority
- DE
- Germany
- Prior art keywords
- memory block
- block structure
- words
- bits
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/418,661 US5822341A (en) | 1995-04-06 | 1995-04-06 | Multiport RAM for use within a viterbi decoder |
PCT/US1996/004730 WO1996031953A1 (en) | 1995-04-06 | 1996-04-04 | Multiport ram for use within a viterbi decoder |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69602932D1 DE69602932D1 (de) | 1999-07-22 |
DE69602932T2 true DE69602932T2 (de) | 1999-10-28 |
Family
ID=23659047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69602932T Expired - Fee Related DE69602932T2 (de) | 1995-04-06 | 1996-04-04 | Multitor ram zur anwendung in einem viterbidecoder |
Country Status (5)
Country | Link |
---|---|
US (1) | US5822341A (de) |
EP (1) | EP0819341B1 (de) |
AT (1) | ATE181474T1 (de) |
DE (1) | DE69602932T2 (de) |
WO (1) | WO1996031953A1 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100484127B1 (ko) * | 1997-08-07 | 2005-06-16 | 삼성전자주식회사 | 비터비디코더 |
GB9720811D0 (en) * | 1997-09-30 | 1997-12-03 | Sgs Thomson Microelectronics | Dual port buffer |
JP3747604B2 (ja) * | 1997-12-19 | 2006-02-22 | ソニー株式会社 | ビタビ復号装置 |
EP0945989A1 (de) | 1998-03-12 | 1999-09-29 | Hitachi Micro Systems Europe Limited | Viterbi-Dekodierung |
US6477680B2 (en) * | 1998-06-26 | 2002-11-05 | Agere Systems Inc. | Area-efficient convolutional decoder |
US7114056B2 (en) | 1998-12-03 | 2006-09-26 | Sun Microsystems, Inc. | Local and global register partitioning in a VLIW processor |
US6343348B1 (en) * | 1998-12-03 | 2002-01-29 | Sun Microsystems, Inc. | Apparatus and method for optimizing die utilization and speed performance by register file splitting |
US7117342B2 (en) * | 1998-12-03 | 2006-10-03 | Sun Microsystems, Inc. | Implicitly derived register specifiers in a processor |
US6580767B1 (en) * | 1999-10-22 | 2003-06-17 | Motorola, Inc. | Cache and caching method for conventional decoders |
KR100584538B1 (ko) | 1999-11-04 | 2006-05-30 | 삼성전자주식회사 | 마이크로미러 가동장치를 채용한 반사형 프로젝터 |
US6601215B1 (en) * | 2000-02-01 | 2003-07-29 | Agere Systems Inc. | Traceback buffer management for VLSI Viterbi decoders |
US6963962B2 (en) * | 2002-04-11 | 2005-11-08 | Analog Devices, Inc. | Memory system for supporting multiple parallel accesses at very high frequencies |
US8185810B1 (en) * | 2007-04-13 | 2012-05-22 | Link—A—Media Devices Corporation | Low power viterbi trace back architecture |
US8111767B2 (en) * | 2007-05-31 | 2012-02-07 | Renesas Electronics Corporation | Adaptive sliding block Viterbi decoder |
CN102404011B (zh) | 2010-09-15 | 2015-05-20 | 中兴通讯股份有限公司 | 维特比解码实现方法及装置 |
US10346093B1 (en) * | 2018-03-16 | 2019-07-09 | Xilinx, Inc. | Memory arrangement for tensor data |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4394774A (en) * | 1978-12-15 | 1983-07-19 | Compression Labs, Inc. | Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback |
US4302775A (en) * | 1978-12-15 | 1981-11-24 | Compression Labs, Inc. | Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback |
US4539684A (en) * | 1983-01-07 | 1985-09-03 | Motorola, Inc. | Automatic frame synchronization recovery utilizing a sequential decoder |
US4761796A (en) * | 1985-01-24 | 1988-08-02 | Itt Defense Communications | High frequency spread spectrum communication system terminal |
US4748626A (en) * | 1987-01-28 | 1988-05-31 | Racal Data Communications Inc. | Viterbi decoder with reduced number of data move operations |
JPS63275227A (ja) * | 1987-05-07 | 1988-11-11 | Fujitsu Ltd | ビタビ復号器用パスメモリ回路 |
US5249159A (en) * | 1987-05-27 | 1993-09-28 | Hitachi, Ltd. | Semiconductor memory |
US5014235A (en) * | 1987-12-15 | 1991-05-07 | Steven G. Morton | Convolution memory |
US4937781A (en) * | 1988-05-13 | 1990-06-26 | Dallas Semiconductor Corporation | Dual port ram with arbitration status register |
US4958318A (en) * | 1988-07-08 | 1990-09-18 | Eliyahou Harari | Sidewall capacitor DRAM cell |
US5263143A (en) * | 1988-07-11 | 1993-11-16 | Star Semiconductor Corporation | Real time probe device for internals of signal processor |
DE69024109T2 (de) * | 1989-06-19 | 1996-07-11 | Nec Corp | Halbleiterspeicheranordnung mit einer verbesserten Schreibsteuerschaltung |
US5105387A (en) * | 1989-10-13 | 1992-04-14 | Texas Instruments Incorporated | Three transistor dual port dynamic random access memory gain cell |
US5342990A (en) * | 1990-01-05 | 1994-08-30 | E-Mu Systems, Inc. | Digital sampling instrument employing cache-memory |
US5031132A (en) * | 1990-02-27 | 1991-07-09 | Analogic Corporation | Circuit for convolving a set of digital data |
US5193094A (en) * | 1990-03-07 | 1993-03-09 | Qualcomm Incorporated | Method and apparatus for generating super-orthogonal convolutional codes and the decoding thereof |
US5142540A (en) * | 1990-03-13 | 1992-08-25 | Glasser Lance A | Multipart memory apparatus with error detection |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US5101446A (en) * | 1990-05-31 | 1992-03-31 | Aware, Inc. | Method and apparatus for coding an image |
EP0466997A1 (de) * | 1990-07-18 | 1992-01-22 | International Business Machines Corporation | Verbesserte digitale Signal-Verarbeitungsarchitektur |
US5204841A (en) * | 1990-07-27 | 1993-04-20 | International Business Machines Corporation | Virtual multi-port RAM |
KR950003666B1 (ko) * | 1990-12-31 | 1995-04-17 | 삼성전자 주식회사 | 지엠에스케이신호복조방법 및 그 장치 |
US5271061A (en) * | 1991-09-17 | 1993-12-14 | Next Computer, Inc. | Method and apparatus for public key exchange in a cryptographic system |
JPH0591142A (ja) * | 1991-09-30 | 1993-04-09 | Nec Corp | パケツトスイツチ |
US5365551A (en) * | 1992-12-15 | 1994-11-15 | Micron Technology, Inc. | Data communication transceiver using identification protocol |
US5375250A (en) * | 1992-07-13 | 1994-12-20 | Van Den Heuvel; Raymond C. | Method of intelligent computing and neural-like processing of time and space functions |
US5390215A (en) * | 1992-10-13 | 1995-02-14 | Hughes Aircraft Company | Multi-processor demodulator for digital cellular base station employing partitioned demodulation procedure with pipelined execution |
US5519808A (en) * | 1993-03-10 | 1996-05-21 | Lanier Worldwide, Inc. | Transcription interface for a word processing station |
US5432804A (en) * | 1993-11-16 | 1995-07-11 | At&T Corp. | Digital processor and viterbi decoder having shared memory |
-
1995
- 1995-04-06 US US08/418,661 patent/US5822341A/en not_active Expired - Lifetime
-
1996
- 1996-04-04 DE DE69602932T patent/DE69602932T2/de not_active Expired - Fee Related
- 1996-04-04 EP EP96911603A patent/EP0819341B1/de not_active Expired - Lifetime
- 1996-04-04 AT AT96911603T patent/ATE181474T1/de active
- 1996-04-04 WO PCT/US1996/004730 patent/WO1996031953A1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP0819341A1 (de) | 1998-01-21 |
ATE181474T1 (de) | 1999-07-15 |
WO1996031953A1 (en) | 1996-10-10 |
EP0819341B1 (de) | 1999-06-16 |
US5822341A (en) | 1998-10-13 |
DE69602932D1 (de) | 1999-07-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: COMTECH TELECOMMUNICATIONS CORP. (N.D.GES.D. STAAT |
|
8339 | Ceased/non-payment of the annual fee |