DE69615278T2 - SDRAM-Datenzuweisungsanordnung und -verfahren - Google Patents

SDRAM-Datenzuweisungsanordnung und -verfahren

Info

Publication number
DE69615278T2
DE69615278T2 DE69615278T DE69615278T DE69615278T2 DE 69615278 T2 DE69615278 T2 DE 69615278T2 DE 69615278 T DE69615278 T DE 69615278T DE 69615278 T DE69615278 T DE 69615278T DE 69615278 T2 DE69615278 T2 DE 69615278T2
Authority
DE
Germany
Prior art keywords
data allocation
sdram data
allocation arrangement
arrangement
sdram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69615278T
Other languages
English (en)
Other versions
DE69615278D1 (de
Inventor
John Dykstal
Byron A Alcorn
Darel N Emmot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69615278D1 publication Critical patent/DE69615278D1/de
Publication of DE69615278T2 publication Critical patent/DE69615278T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/04Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851Cache with interleaved addressing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/121Frame memory handling using a cache memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/123Frame memory handling using interleaving
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/128Frame memory using a Synchronous Dynamic RAM [SDRAM]
DE69615278T 1995-06-06 1996-05-07 SDRAM-Datenzuweisungsanordnung und -verfahren Expired - Fee Related DE69615278T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US46686595A 1995-06-06 1995-06-06

Publications (2)

Publication Number Publication Date
DE69615278D1 DE69615278D1 (de) 2001-10-25
DE69615278T2 true DE69615278T2 (de) 2002-06-27

Family

ID=23853399

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615278T Expired - Fee Related DE69615278T2 (de) 1995-06-06 1996-05-07 SDRAM-Datenzuweisungsanordnung und -verfahren

Country Status (4)

Country Link
US (1) US6000019A (de)
EP (1) EP0747825B1 (de)
JP (1) JP3645654B2 (de)
DE (1) DE69615278T2 (de)

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Also Published As

Publication number Publication date
JP3645654B2 (ja) 2005-05-11
EP0747825A2 (de) 1996-12-11
EP0747825B1 (de) 2001-09-19
DE69615278D1 (de) 2001-10-25
US6000019A (en) 1999-12-07
JPH08328952A (ja) 1996-12-13
EP0747825A3 (de) 1998-03-18

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee