DE69619417D1 - Rechnersystem mit hierarchischen Speichern - Google Patents

Rechnersystem mit hierarchischen Speichern

Info

Publication number
DE69619417D1
DE69619417D1 DE69619417T DE69619417T DE69619417D1 DE 69619417 D1 DE69619417 D1 DE 69619417D1 DE 69619417 T DE69619417 T DE 69619417T DE 69619417 T DE69619417 T DE 69619417T DE 69619417 D1 DE69619417 D1 DE 69619417D1
Authority
DE
Germany
Prior art keywords
computer system
hierarchical memories
hierarchical
memories
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69619417T
Other languages
English (en)
Other versions
DE69619417T2 (de
Inventor
Christian Piguet
Jean-Marc Masgonty
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre Suisse dElectronique et Microtechnique SA CSEM
Original Assignee
Centre Suisse dElectronique et Microtechnique SA CSEM
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre Suisse dElectronique et Microtechnique SA CSEM filed Critical Centre Suisse dElectronique et Microtechnique SA CSEM
Application granted granted Critical
Publication of DE69619417D1 publication Critical patent/DE69619417D1/de
Publication of DE69619417T2 publication Critical patent/DE69619417T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE69619417T 1995-03-23 1996-03-20 Rechnersystem mit hierarchischen Speichern Expired - Fee Related DE69619417T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9503432A FR2732134B1 (fr) 1995-03-23 1995-03-23 Systeme informatique avec memoires hierarchisees

Publications (2)

Publication Number Publication Date
DE69619417D1 true DE69619417D1 (de) 2002-04-04
DE69619417T2 DE69619417T2 (de) 2002-10-31

Family

ID=9477356

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619417T Expired - Fee Related DE69619417T2 (de) 1995-03-23 1996-03-20 Rechnersystem mit hierarchischen Speichern

Country Status (4)

Country Link
US (1) US5845311A (de)
EP (1) EP0733977B1 (de)
DE (1) DE69619417T2 (de)
FR (1) FR2732134B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI107196B (fi) * 1997-07-09 2001-06-15 Vlsi Solution Oy Menetelmä ja laite kuvaelementtien käsittelemiseksi
JP2001134486A (ja) 1999-11-04 2001-05-18 Fujitsu Ltd マイクロプロセッサおよび記憶装置
US7330954B2 (en) * 2002-04-18 2008-02-12 Intel Corporation Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices
US20060294334A1 (en) * 2005-06-23 2006-12-28 International Business Machines Corporation Statement regarding federally sponsored-research or development

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435775A (en) * 1981-01-19 1984-03-06 Texas Instruments Incorporated Data processing system having interlinked slow and fast memory means
EP0082903B1 (de) * 1981-12-29 1987-05-13 International Business Machines Corporation Steuergerät mit Anschlussmöglichkeit an zwei Speicher unterschiedlicher Geschwindigkeit
JPS595355A (ja) * 1982-06-30 1984-01-12 Fujitsu Ltd 仮想スタツクのアクセス制御方式
JPS63201828A (ja) * 1987-02-18 1988-08-19 Hitachi Ltd 情報処理装置
US4958304A (en) * 1987-03-02 1990-09-18 Apple Computer, Inc. Computer with interface for fast and slow memory circuits
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
JP2818415B2 (ja) * 1988-05-18 1998-10-30 日本電気株式会社 バッファ記憶装置
JPH02273843A (ja) * 1989-04-14 1990-11-08 Nec Corp スワッピング装置
US5155828A (en) * 1989-07-05 1992-10-13 Hewlett-Packard Company Computing system with a cache memory and an additional look-aside cache memory
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5073851A (en) * 1990-02-21 1991-12-17 Apple Computer, Inc. Apparatus and method for improved caching in a computer system
US5241663A (en) * 1990-05-31 1993-08-31 Sony Corporation Hierarchically pairing memory blocks based upon relative storage capacities and simultaneously accessing each memory block within the paired memory blocks
US5249282A (en) * 1990-11-21 1993-09-28 Benchmarq Microelectronics, Inc. Integrated cache memory system with primary and secondary cache memories
JPH06110781A (ja) * 1992-09-30 1994-04-22 Nec Corp キャッシュメモリ装置
JPH06250928A (ja) * 1993-02-24 1994-09-09 Matsushita Electric Ind Co Ltd 情報処理装置
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US5539893A (en) * 1993-11-16 1996-07-23 Unisys Corporation Multi-level memory and methods for allocating data most likely to be used to the fastest memory level
US5606688A (en) * 1994-08-31 1997-02-25 International Business Machines Corporation Method and apparatus for dynamic cache memory allocation via single-reference residency times

Also Published As

Publication number Publication date
EP0733977B1 (de) 2002-02-27
DE69619417T2 (de) 2002-10-31
FR2732134B1 (fr) 1997-06-06
EP0733977A1 (de) 1996-09-25
FR2732134A1 (fr) 1996-09-27
US5845311A (en) 1998-12-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee