DE69626485D1 - Schnittstellenbildung zwischen Direktspeicherzugriffsvorrichtung und einem nicht-ISA-Bus - Google Patents

Schnittstellenbildung zwischen Direktspeicherzugriffsvorrichtung und einem nicht-ISA-Bus

Info

Publication number
DE69626485D1
DE69626485D1 DE69626485T DE69626485T DE69626485D1 DE 69626485 D1 DE69626485 D1 DE 69626485D1 DE 69626485 T DE69626485 T DE 69626485T DE 69626485 T DE69626485 T DE 69626485T DE 69626485 D1 DE69626485 D1 DE 69626485D1
Authority
DE
Germany
Prior art keywords
access device
memory access
direct memory
isa bus
interface formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69626485T
Other languages
English (en)
Other versions
DE69626485T2 (de
Inventor
Christopher C Wanner
Jeffrey C Stevens
Robert A Lester
Dwight D Riley
David J Maguire
James R Edwards
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24279478&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69626485(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69626485D1 publication Critical patent/DE69626485D1/de
Publication of DE69626485T2 publication Critical patent/DE69626485T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
DE69626485T 1995-12-11 1996-12-10 Schnittstellenbildung zwischen Direktspeicherzugriffsvorrichtung und einem nicht-ISA-Bus Expired - Lifetime DE69626485T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/570,394 US5774680A (en) 1995-12-11 1995-12-11 Interfacing direct memory access devices to a non-ISA bus

Publications (2)

Publication Number Publication Date
DE69626485D1 true DE69626485D1 (de) 2003-04-10
DE69626485T2 DE69626485T2 (de) 2003-09-11

Family

ID=24279478

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69626485T Expired - Lifetime DE69626485T2 (de) 1995-12-11 1996-12-10 Schnittstellenbildung zwischen Direktspeicherzugriffsvorrichtung und einem nicht-ISA-Bus

Country Status (4)

Country Link
US (5) US5774680A (de)
EP (1) EP0784277B1 (de)
DE (1) DE69626485T2 (de)
TW (1) TW379294B (de)

Families Citing this family (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3403284B2 (ja) * 1995-12-14 2003-05-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理システム及びその制御方法
US5954802A (en) * 1996-01-31 1999-09-21 Texas Instruments Incorporated System for interfacing ISA compatible computer devices with non-ISA buses using secondary DMA controllers and glue logic circuit
US6233704B1 (en) * 1996-03-13 2001-05-15 Silicon Graphics, Inc. System and method for fault-tolerant transmission of data within a dual ring network
JPH1040211A (ja) * 1996-04-30 1998-02-13 Texas Instr Inc <Ti> パケット化されたデータ通信インタフェース機器内での直接メモリアクセス優先順位を割り当てるための方法ならびにｄｍａチャンネル回路
US5918028A (en) * 1997-07-08 1999-06-29 Motorola, Inc. Apparatus and method for smart host bus adapter for personal computer cards
US5991841A (en) * 1997-09-24 1999-11-23 Intel Corporation Memory transactions on a low pin count bus
US6157970A (en) * 1997-09-24 2000-12-05 Intel Corporation Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
US6119189A (en) * 1997-09-24 2000-09-12 Intel Corporation Bus master transactions on a low pin count bus
JPH11120120A (ja) * 1997-10-13 1999-04-30 Fujitsu Ltd カードバス用インターフェース回路及びそれを有するカードバス用ｐｃカード
US5938744A (en) * 1997-11-04 1999-08-17 Aiwa/Raid Technlogy, Method for managing multiple DMA queues by a single controller
US6230219B1 (en) * 1997-11-10 2001-05-08 International Business Machines Corporation High performance multichannel DMA controller for a PCI host bridge with a built-in cache
US5983024A (en) * 1997-11-26 1999-11-09 Honeywell, Inc. Method and apparatus for robust data broadcast on a peripheral component interconnect bus
KR19990043773A (ko) * 1997-11-29 1999-06-15 정선종 직접 메모리 액세스 제어기
US6397279B1 (en) * 1998-01-07 2002-05-28 Vlsi Technology, Inc. Smart retry system that reduces wasted bus transactions associated with master retries
US6122676A (en) * 1998-01-07 2000-09-19 National Semiconductor Corporation Apparatus and method for transmitting and receiving data into and out of a universal serial bus device
US6157975A (en) * 1998-01-07 2000-12-05 National Semiconductor Corporation Apparatus and method for providing an interface to a compound Universal Serial Bus controller
US6205501B1 (en) 1998-01-07 2001-03-20 National Semiconductor Corp. Apparatus and method for handling universal serial bus control transfers
US6070208A (en) * 1998-01-07 2000-05-30 National Semiconductor Corporation Apparatus and method for implementing a versatile USB endpoint pipe
US6353866B1 (en) 1998-01-07 2002-03-05 National Semiconductor Corporation Apparatus and method for initializing a universal serial bus device
US6412027B1 (en) * 1998-02-11 2002-06-25 Globespanvirata, Inc. Direct memory access controller having on-board arbitration circuitry
US6122679A (en) * 1998-03-13 2000-09-19 Compaq Computer Corporation Master DMA controller with re-map engine for only spawning programming cycles to slave DMA controllers which do not match current programming cycle
US6473780B1 (en) * 1998-04-01 2002-10-29 Intel Corporation Scheduling of direct memory access
US6138183A (en) * 1998-05-06 2000-10-24 Ess Technolgoy Inc. Transparent direct memory access
US5966384A (en) * 1998-05-08 1999-10-12 Motorola, Inc. Method and apparatus for data transmission within a broad-band communication system
KR100285956B1 (ko) 1998-06-30 2001-04-16 윤종용 고속직렬버스에연결된동기식및비동기식장치의제어시스템과제어방법
JP2938049B1 (ja) * 1998-07-02 1999-08-23 新潟日本電気株式会社 コンピュータ本体への拡張入出力装置の活線挿抜制御装置
US7158532B2 (en) * 1998-07-06 2007-01-02 Intel Corporation Half duplex link with isochronous and asynchronous arbitration
US6163818A (en) * 1998-08-27 2000-12-19 Xerox Corporation Streaming memory controller for a PCI bus
US6425021B1 (en) * 1998-11-16 2002-07-23 Lsi Logic Corporation System for transferring data packets of different context utilizing single interface and concurrently processing data packets of different contexts
US6260082B1 (en) * 1998-12-23 2001-07-10 Bops, Inc. Methods and apparatus for providing data transfer control
US6233628B1 (en) * 1999-01-08 2001-05-15 Oak Technology, Inc. System and method for transferring data using separate pipes for command and data
DE60005157T2 (de) * 1999-03-04 2004-07-08 Deka Products Ltd. Partnership Verfahren und anordnung für blockdatenübertragung
US6889254B1 (en) * 1999-03-30 2005-05-03 International Business Machines Corporation Scalable merge technique for information retrieval across a distributed network
US6701405B1 (en) * 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6434674B1 (en) 2000-04-04 2002-08-13 Advanced Digital Information Corporation Multiport memory architecture with direct data flow
US7085875B1 (en) * 2000-04-06 2006-08-01 Avaya Communication Israel Ltd. Modular switch with dynamic bus
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6735715B1 (en) 2000-04-13 2004-05-11 Stratus Technologies Bermuda Ltd. System and method for operating a SCSI bus with redundant SCSI adaptors
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6708283B1 (en) 2000-04-13 2004-03-16 Stratus Technologies, Bermuda Ltd. System and method for operating a system with redundant peripheral bus controllers
US6633996B1 (en) 2000-04-13 2003-10-14 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus architecture
US6691257B1 (en) 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
US6898646B1 (en) * 2000-05-03 2005-05-24 Hewlett-Packard Development Company, L.P. Highly concurrent DMA controller with programmable DMA channels
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US6977927B1 (en) 2000-09-18 2005-12-20 Hewlett-Packard Development Company, L.P. Method and system of allocating storage resources in a storage area network
US6804819B1 (en) 2000-09-18 2004-10-12 Hewlett-Packard Development Company, L.P. Method, system, and computer program product for a data propagation platform and applications of same
US7386610B1 (en) 2000-09-18 2008-06-10 Hewlett-Packard Development Company, L.P. Internet protocol data mirroring
US6665760B1 (en) 2000-09-29 2003-12-16 Rockwell Automation Technologies, Inc. Group shifting and level shifting rotational arbiter system
US6883132B1 (en) 2000-09-29 2005-04-19 Rockwell Automation Technologies, Inc. Programmable error checking value circuit and method
US6606690B2 (en) 2001-02-20 2003-08-12 Hewlett-Packard Development Company, L.P. System and method for accessing a storage area network as network attached storage
US6766479B2 (en) 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations
US6950893B2 (en) * 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture
US7065672B2 (en) * 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
JP2002297112A (ja) * 2001-03-30 2002-10-11 Minolta Co Ltd 液晶表示素子の駆動装置
US6996750B2 (en) * 2001-05-31 2006-02-07 Stratus Technologies Bermuda Ltd. Methods and apparatus for computer bus error termination
US6823414B2 (en) * 2002-03-01 2004-11-23 Intel Corporation Interrupt disabling apparatus, system, and method
US20040059862A1 (en) * 2002-09-24 2004-03-25 I-Bus Corporation Method and apparatus for providing redundant bus control
US7152123B2 (en) * 2002-12-23 2006-12-19 Micron Technology, Inc. Distributed configuration storage
US20050038946A1 (en) * 2003-08-12 2005-02-17 Tadpole Computer, Inc. System and method using a high speed interface in a system having co-processors
TWI223754B (en) * 2003-10-22 2004-11-11 Avermedia Tech Inc Computer system with direct media access mode
JP2005165508A (ja) * 2003-12-01 2005-06-23 Renesas Technology Corp ダイレクトメモリアクセスコントローラ
JP2005221731A (ja) * 2004-02-05 2005-08-18 Konica Minolta Photo Imaging Inc 撮像装置
US7822032B1 (en) * 2004-03-30 2010-10-26 Extreme Networks, Inc. Data structures for supporting packet data modification operations
US7304996B1 (en) 2004-03-30 2007-12-04 Extreme Networks, Inc. System and method for assembling a data packet
WO2007003986A1 (en) 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Device and method for controlling an execution of a dma task
DE602005023542D1 (de) * 2005-06-30 2010-10-21 Freescale Semiconductor Inc Einrichtung und verfahren zum ausführen einer dma-task
DE602005017948D1 (de) 2005-06-30 2010-01-07 Freescale Semiconductor Inc Einrichtung und verfahren zum arbitrieren zwischen direktspeicherzugriffs-task-anforderungen
DE602005015632D1 (de) * 2005-06-30 2009-09-03 Freescale Semiconductor Inc Einrichtung und verfahren zur steuerung mehrerer dma-tasks
GB2433611A (en) * 2005-12-21 2007-06-27 Advanced Risc Mach Ltd DMA controller with virtual channels
WO2007083197A1 (en) 2006-01-18 2007-07-26 Freescale Semiconductor Inc. Device having data sharing capabilities and a method for sharing data
US7490177B2 (en) * 2006-01-23 2009-02-10 Infineon Technologies Ag System method for performing a direct memory access for automatically copying initialization boot code in a new memory architecture
JP4446968B2 (ja) * 2006-02-22 2010-04-07 シャープ株式会社 データ処理装置
US7689732B2 (en) * 2006-02-24 2010-03-30 Via Technologies, Inc. Method for improving flexibility of arbitration of direct memory access (DMA) engines requesting access to shared DMA channels
US7716389B1 (en) * 2006-03-17 2010-05-11 Bitmicro Networks, Inc. Direct memory access controller with encryption and decryption for non-blocking high bandwidth I/O transactions
US8165301B1 (en) 2006-04-04 2012-04-24 Bitmicro Networks, Inc. Input-output device and storage controller handshake protocol using key exchange for data security
TWI315475B (en) * 2006-09-01 2009-10-01 Via Tech Inc Control method and control system for multiple host bus adapters
JP2008146541A (ja) * 2006-12-13 2008-06-26 Fujitsu Ltd Ｄｍａ転送システム、ｄｍａコントローラ及びｄｍａ転送方法
US7924296B2 (en) * 2007-02-20 2011-04-12 Mtekvision Co., Ltd. System and method for DMA controlled image processing
US8959307B1 (en) 2007-11-16 2015-02-17 Bitmicro Networks, Inc. Reduced latency memory read transactions in storage devices
US7941574B2 (en) * 2008-08-11 2011-05-10 International Business Machines Corporation CKD partial record handling
US8139583B1 (en) 2008-09-30 2012-03-20 Extreme Networks, Inc. Command selection in a packet forwarding device
US20100138575A1 (en) 2008-12-01 2010-06-03 Micron Technology, Inc. Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
US9135190B1 (en) 2009-09-04 2015-09-15 Bitmicro Networks, Inc. Multi-profile memory controller for computing devices
US8665601B1 (en) 2009-09-04 2014-03-04 Bitmicro Networks, Inc. Solid state drive with improved enclosure assembly
US8447908B2 (en) 2009-09-07 2013-05-21 Bitmicro Networks, Inc. Multilevel memory bus system for solid-state mass storage
US8560804B2 (en) 2009-09-14 2013-10-15 Bitmicro Networks, Inc. Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device
US8250253B2 (en) * 2010-06-23 2012-08-21 Intel Corporation Method, apparatus and system for reduced channel starvation in a DMA engine
US9372755B1 (en) 2011-10-05 2016-06-21 Bitmicro Networks, Inc. Adaptive power cycle sequences for data recovery
TW201344445A (zh) * 2012-04-27 2013-11-01 Sunix Co Ltd 可分配低階輸入輸出埠其介面位址的ｐｃｉ介面裝置
US9043669B1 (en) 2012-05-18 2015-05-26 Bitmicro Networks, Inc. Distributed ECC engine for storage media
US8966132B2 (en) 2012-11-16 2015-02-24 International Business Machines Corporation Determining a mapping mode for a DMA data transfer
US9423457B2 (en) 2013-03-14 2016-08-23 Bitmicro Networks, Inc. Self-test solution for delay locked loops
US9501436B1 (en) 2013-03-15 2016-11-22 Bitmicro Networks, Inc. Multi-level message passing descriptor
US9842024B1 (en) 2013-03-15 2017-12-12 Bitmicro Networks, Inc. Flash electronic disk with RAID controller
US9400617B2 (en) 2013-03-15 2016-07-26 Bitmicro Networks, Inc. Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained
US9971524B1 (en) 2013-03-15 2018-05-15 Bitmicro Networks, Inc. Scatter-gather approach for parallel data transfer in a mass storage system
US9734067B1 (en) 2013-03-15 2017-08-15 Bitmicro Networks, Inc. Write buffering
US10120694B2 (en) 2013-03-15 2018-11-06 Bitmicro Networks, Inc. Embedded system boot from a storage device
US10489318B1 (en) 2013-03-15 2019-11-26 Bitmicro Networks, Inc. Scatter-gather approach for parallel data transfer in a mass storage system
US9934045B1 (en) 2013-03-15 2018-04-03 Bitmicro Networks, Inc. Embedded system boot from a storage device
US9916213B1 (en) 2013-03-15 2018-03-13 Bitmicro Networks, Inc. Bus arbitration with routing and failover mechanism
US9875205B1 (en) 2013-03-15 2018-01-23 Bitmicro Networks, Inc. Network of memory systems
US9672178B1 (en) 2013-03-15 2017-06-06 Bitmicro Networks, Inc. Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system
US9720603B1 (en) 2013-03-15 2017-08-01 Bitmicro Networks, Inc. IOC to IOC distributed caching architecture
US9798688B1 (en) 2013-03-15 2017-10-24 Bitmicro Networks, Inc. Bus arbitration with routing and failover mechanism
US9430386B2 (en) 2013-03-15 2016-08-30 Bitmicro Networks, Inc. Multi-leveled cache management in a hybrid storage system
US8984179B1 (en) 2013-11-15 2015-03-17 International Business Machines Corporation Determining a direct memory access data transfer mode
US9952991B1 (en) 2014-04-17 2018-04-24 Bitmicro Networks, Inc. Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation
US10078604B1 (en) 2014-04-17 2018-09-18 Bitmicro Networks, Inc. Interrupt coalescing
US10025736B1 (en) 2014-04-17 2018-07-17 Bitmicro Networks, Inc. Exchange message protocol message transmission between two devices
US10055150B1 (en) 2014-04-17 2018-08-21 Bitmicro Networks, Inc. Writing volatile scattered memory metadata to flash device
US9811461B1 (en) 2014-04-17 2017-11-07 Bitmicro Networks, Inc. Data storage system
US10042792B1 (en) 2014-04-17 2018-08-07 Bitmicro Networks, Inc. Method for transferring and receiving frames across PCI express bus for SSD device
US10162775B2 (en) * 2015-12-22 2018-12-25 Futurewei Technologies, Inc. System and method for efficient cross-controller request handling in active/active storage systems
US10496388B2 (en) * 2016-03-24 2019-12-03 Intel Corporation Technologies for securing a firmware update
US10552050B1 (en) 2017-04-07 2020-02-04 Bitmicro Llc Multi-dimensional computer storage system
US10599601B1 (en) 2019-01-16 2020-03-24 Qorvo Us, Inc. Single-wire bus (SuBUS) slave circuit and related apparatus
US11119958B2 (en) * 2019-04-18 2021-09-14 Qorvo Us, Inc. Hybrid bus apparatus
US11226924B2 (en) 2019-04-24 2022-01-18 Qorvo Us, Inc. Single-wire bus apparatus supporting slave-initiated operation in a master circuit
US10983942B1 (en) 2019-12-11 2021-04-20 Qorvo Us, Inc. Multi-master hybrid bus apparatus
US11409677B2 (en) 2020-11-11 2022-08-09 Qorvo Us, Inc. Bus slave circuit and related single-wire bus apparatus
US11489695B2 (en) 2020-11-24 2022-11-01 Qorvo Us, Inc. Full-duplex communications over a single-wire bus
CN114661651A (zh) * 2020-12-23 2022-06-24 富泰华工业（深圳）有限公司 数据存取方法以及系统
US11706048B1 (en) 2021-12-16 2023-07-18 Qorvo Us, Inc. Multi-protocol bus circuit

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942050B2 (ja) * 1981-03-31 1984-10-12 株式会社豊田中央研究所 ステンレス鋼材固溶化熱処理時の冷却方法
JPS5819968A (ja) * 1981-07-28 1983-02-05 Omron Tateisi Electronics Co アドレス指定方式
US4751634A (en) * 1985-06-14 1988-06-14 International Business Machines Corporation Multiple port communications adapter apparatus
US5317715A (en) * 1987-12-15 1994-05-31 Advanced Micro Devices, Inc. Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics
MY117259A (en) * 1991-05-02 2004-06-30 Thomson Consumer Electronics Autoprogrammed channel mapping for a videocassette recorder.
US5335329A (en) * 1991-07-18 1994-08-02 Texas Microsystems, Inc. Apparatus for providing DMA functionality to devices located in a bus expansion chassis
US5455934A (en) * 1993-03-23 1995-10-03 Eclipse Technologies, Inc. Fault tolerant hard disk array controller
US5561821A (en) * 1993-10-29 1996-10-01 Advanced Micro Devices System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus
US5685012A (en) * 1993-11-09 1997-11-04 Micron Electronics, Inc. System for employing high speed data transfer between host and peripheral via host interface circuitry utilizing an IOread signal driven by the peripheral or the host
US5687338A (en) * 1994-03-01 1997-11-11 Intel Corporation Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
US5598579A (en) * 1994-04-25 1997-01-28 Compaq Computer Corporation System fpr transferring data between two buses using control registers writable by host processor connected to system bus and local processor coupled to local bus
US5608889A (en) * 1994-08-17 1997-03-04 Ceridian Corporation DNA controller with wrap-around buffer mode
US5619647A (en) * 1994-09-30 1997-04-08 Tandem Computers, Incorporated System for multiplexing prioritized virtual channels onto physical channels where higher priority virtual will pre-empt a lower priority virtual or a lower priority will wait
US5621902A (en) * 1994-11-30 1997-04-15 International Business Machines Corporation Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller
US5598526A (en) * 1995-02-23 1997-01-28 Alliance Semiconductor Corporation Method and system for displaying images using a dynamically reconfigurable display memory architecture
US5673400A (en) * 1995-06-06 1997-09-30 National Semiconductor Corporation Method and apparatus for identifying and controlling a target peripheral device in a multiple bus system
US5590377A (en) * 1995-06-07 1996-12-31 Ast Research, Inc. Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses
US5752076A (en) * 1995-08-31 1998-05-12 Intel Corporation Dynamic programming of bus master channels by intelligent peripheral devices using communication packets

Also Published As

Publication number Publication date
DE69626485T2 (de) 2003-09-11
US5765024A (en) 1998-06-09
US5875351A (en) 1999-02-23
US5774680A (en) 1998-06-30
US6088517A (en) 2000-07-11
EP0784277A1 (de) 1997-07-16
TW379294B (en) 2000-01-11
EP0784277B1 (de) 2003-03-05
US5838993A (en) 1998-11-17

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