DE69632978D1 - Multi-Operand-Addierer, der Parallelzähler benutzt - Google Patents

Multi-Operand-Addierer, der Parallelzähler benutzt

Info

Publication number
DE69632978D1
DE69632978D1 DE69632978T DE69632978T DE69632978D1 DE 69632978 D1 DE69632978 D1 DE 69632978D1 DE 69632978 T DE69632978 T DE 69632978T DE 69632978 T DE69632978 T DE 69632978T DE 69632978 D1 DE69632978 D1 DE 69632978D1
Authority
DE
Germany
Prior art keywords
uses parallel
operand adder
parallel counters
counters
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69632978T
Other languages
English (en)
Other versions
DE69632978T2 (de
Inventor
Takeshi Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69632978D1 publication Critical patent/DE69632978D1/de
Publication of DE69632978T2 publication Critical patent/DE69632978T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3836—One's complement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4816—Pass transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4822—Majority gates
DE69632978T 1995-04-11 1996-04-11 Multi-Operand-Addierer, der Parallelzähler benutzt Expired - Fee Related DE69632978T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP8525595 1995-04-11
JP8525595 1995-04-11
JP8954196 1996-04-11
JP08954196A JP3658079B2 (ja) 1995-04-11 1996-04-11 演算処理装置及びデータ処理装置

Publications (2)

Publication Number Publication Date
DE69632978D1 true DE69632978D1 (de) 2004-09-02
DE69632978T2 DE69632978T2 (de) 2005-07-21

Family

ID=32827169

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69632978T Expired - Fee Related DE69632978T2 (de) 1995-04-11 1996-04-11 Multi-Operand-Addierer, der Parallelzähler benutzt

Country Status (6)

Country Link
US (1) US5978827A (de)
EP (1) EP0741354B1 (de)
JP (1) JP3658079B2 (de)
KR (1) KR100359965B1 (de)
CN (1) CN1129066C (de)
DE (1) DE69632978T2 (de)

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US7136888B2 (en) 2000-08-04 2006-11-14 Arithmatica Limited Parallel counter and a logic circuit for performing multiplication
US6883011B2 (en) 2000-08-04 2005-04-19 Arithmatica Limited Parallel counter and a multiplication logic circuit
GB2365636B (en) 2000-08-04 2005-01-05 Automatic Parallel Designs Ltd A parallel counter and a multiplication logic circuit
US6701339B2 (en) * 2000-12-08 2004-03-02 Intel Corporation Pipelined compressor circuit
US6729168B2 (en) * 2000-12-08 2004-05-04 Stmicroelectronics, Inc. Circuit for determining the number of logical one values on a data bus
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US6779013B2 (en) * 2001-06-04 2004-08-17 Intel Corporation Floating point overflow and sign detection
US7080111B2 (en) * 2001-06-04 2006-07-18 Intel Corporation Floating point multiply accumulator
EP1308836A1 (de) * 2001-10-31 2003-05-07 Motorola, Inc. Addierer-Baum mit einer reduzierten Carry-Ripple Addierstufe
US20030154227A1 (en) * 2002-02-08 2003-08-14 Intel Corporation Multi-threaded multiply accumulator
US7734675B1 (en) * 2002-12-05 2010-06-08 Cisco Technology, Inc. System and method for generating a binary result in a data processing environment
US7293056B2 (en) * 2002-12-18 2007-11-06 Intel Corporation Variable width, at least six-way addition/accumulation instructions
US7260595B2 (en) * 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
WO2004064254A2 (en) 2003-01-14 2004-07-29 Arithmatica Limited A logic circuit
US7042246B2 (en) 2003-02-11 2006-05-09 Arithmatica Limited Logic circuits for performing threshold functions
US7308471B2 (en) 2003-03-28 2007-12-11 Arithmatica Limited Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
WO2004104820A2 (en) 2003-05-23 2004-12-02 Arithmatica Limited A sum bit generation circuit
JP2005182238A (ja) * 2003-12-17 2005-07-07 Renesas Technology Corp 演算装置
US20050228845A1 (en) * 2004-04-12 2005-10-13 Mathstar, Inc. Shift and recode multiplier
US20060020655A1 (en) * 2004-06-29 2006-01-26 The Research Foundation Of State University Of New York Library of low-cost low-power and high-performance multipliers
JP4810090B2 (ja) * 2004-12-20 2011-11-09 キヤノン株式会社 データ処理装置
US8271572B2 (en) * 2008-10-14 2012-09-18 The Research Foundation Of State University Of New York Generating partial sums
JP2011107972A (ja) * 2009-11-17 2011-06-02 Fujitsu Ltd 総和計算方法及び数値演算装置
JP5048748B2 (ja) * 2009-12-18 2012-10-17 三菱電機株式会社 試験テーブル生成装置及び試験テーブル生成方法
CN102999310A (zh) * 2012-12-14 2013-03-27 蒋海勇 一种新型芯片晶体管阵列方法
US9355066B1 (en) * 2012-12-17 2016-05-31 Marvell International Ltd. Accelerated calculation of array statistics
RU2547625C2 (ru) * 2013-06-28 2015-04-10 федеральное государственное автономное образовательное учреждение высшего профессионального образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) Многовходовой сумматор
US9836218B2 (en) 2014-10-03 2017-12-05 Micron Technology, Inc. Computing reduction and prefix sum operations in memory
US10171105B2 (en) 2016-08-25 2019-01-01 International Business Machines Corporation Carry-less population count
US11374574B2 (en) 2019-12-27 2022-06-28 Kepler Computing Inc. Linear input and non-linear output threshold logic gate
US11283453B2 (en) * 2019-12-27 2022-03-22 Kepler Computing Inc. Low power ferroelectric based majority logic gate carry propagate and serial adder
US10944404B1 (en) * 2019-12-27 2021-03-09 Kepler Computing, Inc. Low power ferroelectric based majority logic gate adder
US11018672B1 (en) 2019-12-27 2021-05-25 Kepler Computing Inc. Linear input and non-linear output majority logic gate
US11381244B1 (en) 2020-12-21 2022-07-05 Kepler Computing Inc. Low power ferroelectric based majority logic gate multiplier
US11165430B1 (en) 2020-12-21 2021-11-02 Kepler Computing Inc. Majority logic gate based sequential circuit
US11764790B1 (en) * 2021-05-21 2023-09-19 Kepler Computing Inc. Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme
US11290112B1 (en) * 2021-05-21 2022-03-29 Kepler Computing, Inc. Majority logic gate based XOR logic gate with non-linear input capacitors
US11303280B1 (en) 2021-08-19 2022-04-12 Kepler Computing Inc. Ferroelectric or paraelectric based sequential circuit
US11664370B1 (en) 2021-12-14 2023-05-30 Kepler Corpating inc. Multi-function paraelectric threshold gate with input based adaptive threshold
US11705905B1 (en) 2021-12-14 2023-07-18 Kepler Computing, Inc. Multi-function ferroelectric threshold gate with input based adaptive threshold
US11716086B1 (en) 2021-12-23 2023-08-01 Kepler Computing Inc. Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate
US11855627B1 (en) 2022-01-13 2023-12-26 Kepler Computing Inc. Asynchronous consensus circuit using multi-function threshold gate with input based adaptive threshold
US20230238047A1 (en) * 2022-01-21 2023-07-27 National Tsing Hua University Memory unit with time domain edge delay accumulation for computing-in-memory applications and computing method thereof
US11757452B1 (en) * 2022-04-20 2023-09-12 Kepler Computing Inc. OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates
US11765908B1 (en) 2023-02-10 2023-09-19 Kepler Computing Inc. Memory device fabrication through wafer bonding

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JPH08504525A (ja) * 1992-11-20 1996-05-14 ユニシス・コーポレイション 改良された高速乗算器

Also Published As

Publication number Publication date
JP3658079B2 (ja) 2005-06-08
DE69632978T2 (de) 2005-07-21
CN1139777A (zh) 1997-01-08
JPH08339292A (ja) 1996-12-24
KR100359965B1 (ko) 2003-03-15
KR960038594A (ko) 1996-11-21
EP0741354A3 (de) 1997-05-02
US5978827A (en) 1999-11-02
CN1129066C (zh) 2003-11-26
EP0741354B1 (de) 2004-07-28
EP0741354A2 (de) 1996-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee