DE69700318T2 - Phasensynchronisationssystem - Google Patents
PhasensynchronisationssystemInfo
- Publication number
- DE69700318T2 DE69700318T2 DE69700318T DE69700318T DE69700318T2 DE 69700318 T2 DE69700318 T2 DE 69700318T2 DE 69700318 T DE69700318 T DE 69700318T DE 69700318 T DE69700318 T DE 69700318T DE 69700318 T2 DE69700318 T2 DE 69700318T2
- Authority
- DE
- Germany
- Prior art keywords
- phase synchronization
- synchronization system
- phase
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L3/00—Starting of generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8073696A JP2924773B2 (ja) | 1996-03-28 | 1996-03-28 | 位相同期システム |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69700318D1 DE69700318D1 (de) | 1999-08-19 |
DE69700318T2 true DE69700318T2 (de) | 2000-02-03 |
Family
ID=13525647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69700318T Expired - Fee Related DE69700318T2 (de) | 1996-03-28 | 1997-03-24 | Phasensynchronisationssystem |
Country Status (4)
Country | Link |
---|---|
US (1) | US5828253A (de) |
EP (1) | EP0798861B1 (de) |
JP (1) | JP2924773B2 (de) |
DE (1) | DE69700318T2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5949261A (en) * | 1996-12-17 | 1999-09-07 | Cypress Semiconductor Corp. | Method and circuit for reducing power and/or current consumption |
JP4571959B2 (ja) * | 1998-01-21 | 2010-10-27 | 富士通セミコンダクター株式会社 | 入力回路および該入力回路を有する半導体集積回路 |
MY122426A (en) * | 1998-10-29 | 2006-04-29 | Matsushita Electric Ind Co Ltd | Memory controller for controlling an integrated memory undergoing logical state transitions |
US6194927B1 (en) * | 1999-05-19 | 2001-02-27 | Advanced Micro Devices, Inc. | Apparatus and method for a coincident rising edge detection circuit |
US6369660B1 (en) * | 1999-10-27 | 2002-04-09 | Cypress Semiconductor Corp. | Circuit and method for preventing runaway in a phase lock loop |
US6362988B1 (en) * | 2000-06-29 | 2002-03-26 | Ford Global Tech., Inc. | System and method for synchronizing the phase angle for an AC power source in parallel operation with a grid |
KR100473265B1 (ko) * | 2000-09-09 | 2005-03-07 | 엘지전자 주식회사 | 통신시스템의 위상잡음 감지장치 |
US6937680B2 (en) * | 2001-04-24 | 2005-08-30 | Sun Microsystems, Inc. | Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection |
US6768362B1 (en) | 2001-08-13 | 2004-07-27 | Cypress Semiconductor Corp. | Fail-safe zero delay buffer with automatic internal reference |
FR2832564B1 (fr) * | 2001-11-19 | 2004-01-30 | Stepmind | Procede et dispositif de comparaison de phase et de frequence |
US6919650B2 (en) * | 2002-05-31 | 2005-07-19 | Ballard Power Systems Corporation | Hybrid synchronization phase angle generation method |
KR100560434B1 (ko) | 2003-12-17 | 2006-03-13 | 한국전자통신연구원 | 범용 망 동기 시스템 클럭 공급 장치 |
US9286198B2 (en) | 2005-04-21 | 2016-03-15 | Violin Memory | Method and system for storage of data in non-volatile media |
US9384818B2 (en) * | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
EP2378432A1 (de) | 2005-04-21 | 2011-10-19 | Violin Memory, Inc. | Verbindungssystem |
US8452929B2 (en) | 2005-04-21 | 2013-05-28 | Violin Memory Inc. | Method and system for storage of data in non-volatile media |
US9582449B2 (en) | 2005-04-21 | 2017-02-28 | Violin Memory, Inc. | Interconnection system |
US8112655B2 (en) | 2005-04-21 | 2012-02-07 | Violin Memory, Inc. | Mesosynchronous data bus apparatus and method of data transmission |
US8028186B2 (en) | 2006-10-23 | 2011-09-27 | Violin Memory, Inc. | Skew management in an interconnection system |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5170135A (en) * | 1990-07-24 | 1992-12-08 | Nec Corporation | Phase and frequency-locked loop circuit having expanded pull-in range and reduced lock-in time |
JPH0548450A (ja) * | 1991-08-08 | 1993-02-26 | Fujitsu Ltd | Pllシンセサイザ回路 |
US5363419A (en) * | 1992-04-24 | 1994-11-08 | Advanced Micro Devices, Inc. | Dual phase-locked-loop having forced mid range fine control zero at handover |
US5347232A (en) * | 1992-05-15 | 1994-09-13 | Matsushita Electric Industrial Co. Ltd. | Phase locked loop clock generator |
US5294894A (en) * | 1992-10-02 | 1994-03-15 | Compaq Computer Corporation | Method of and apparatus for startup of a digital computer system clock |
JPH06187063A (ja) * | 1992-12-18 | 1994-07-08 | Kawasaki Steel Corp | 半導体装置 |
-
1996
- 1996-03-28 JP JP8073696A patent/JP2924773B2/ja not_active Expired - Lifetime
-
1997
- 1997-03-24 EP EP97104985A patent/EP0798861B1/de not_active Expired - Lifetime
- 1997-03-24 DE DE69700318T patent/DE69700318T2/de not_active Expired - Fee Related
- 1997-03-25 US US08/823,682 patent/US5828253A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5828253A (en) | 1998-10-27 |
EP0798861B1 (de) | 1999-07-14 |
JPH09266442A (ja) | 1997-10-07 |
DE69700318D1 (de) | 1999-08-19 |
JP2924773B2 (ja) | 1999-07-26 |
EP0798861A1 (de) | 1997-10-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |