DE69712382D1 - Speichersystem und Datenkommunikationssystem - Google Patents

Speichersystem und Datenkommunikationssystem

Info

Publication number
DE69712382D1
DE69712382D1 DE69712382T DE69712382T DE69712382D1 DE 69712382 D1 DE69712382 D1 DE 69712382D1 DE 69712382 T DE69712382 T DE 69712382T DE 69712382 T DE69712382 T DE 69712382T DE 69712382 D1 DE69712382 D1 DE 69712382D1
Authority
DE
Germany
Prior art keywords
data communication
communication system
storage system
storage
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69712382T
Other languages
English (en)
Other versions
DE69712382T2 (de
Inventor
Avi Ginsberg
Yaniv Shapira
Yaron Ben-Arie
Benjamin Rosen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69712382D1 publication Critical patent/DE69712382D1/de
Publication of DE69712382T2 publication Critical patent/DE69712382T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
DE69712382T 1996-02-09 1997-02-05 Speichersystem und Datenkommunikationssystem Expired - Fee Related DE69712382T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/598,934 US5721871A (en) 1996-02-09 1996-02-09 Memory system ensuring coherency for memory buffers in a data communication system

Publications (2)

Publication Number Publication Date
DE69712382D1 true DE69712382D1 (de) 2002-06-13
DE69712382T2 DE69712382T2 (de) 2002-11-07

Family

ID=24397535

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69712382T Expired - Fee Related DE69712382T2 (de) 1996-02-09 1997-02-05 Speichersystem und Datenkommunikationssystem

Country Status (3)

Country Link
US (1) US5721871A (de)
EP (1) EP0789303B1 (de)
DE (1) DE69712382T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872980A (en) * 1996-01-25 1999-02-16 International Business Machines Corporation Semaphore access control buffer and method for accelerated semaphore operations
US5909574A (en) * 1997-12-23 1999-06-01 Northern Telecom Limited Computing system with exception handler and method of handling exceptions in a computing system
AU2001249545A1 (en) * 2000-03-31 2001-10-15 Dataplay, Inc. Asynchronous input/output interface protocol
US7161954B2 (en) * 2002-05-28 2007-01-09 International Business Machines Corporation Technique for controlling selection of a write adapter from multiple adapters connected to a high speed switch
US7177322B2 (en) * 2002-05-28 2007-02-13 International Business Machines Corporation Technique for controlling selection of a peek adapter or a read adapter from multiple adapters connected to a high speed switch
US7409558B2 (en) * 2004-09-02 2008-08-05 International Business Machines Corporation Low-latency data decryption interface
US7496753B2 (en) * 2004-09-02 2009-02-24 International Business Machines Corporation Data encryption interface for reducing encrypt latency impact on standard traffic
US8750040B2 (en) * 2011-01-21 2014-06-10 Micron Technology, Inc. Memory devices having source lines directly coupled to body regions and methods
US8750053B2 (en) * 2011-06-09 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM multiplexing apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380798A (en) * 1980-09-15 1983-04-19 Motorola, Inc. Semaphore register including ownership bits
US4897786A (en) * 1987-09-04 1990-01-30 Digital Equipment Corporation Bus window interlock
JPH0740241B2 (ja) * 1989-01-17 1995-05-01 富士通株式会社 リクエストキャンセル方式
US5293491A (en) * 1990-12-28 1994-03-08 International Business Machines Corp. Data processing system and memory controller for lock semaphore operations
CA2057446C (en) * 1991-04-04 1998-02-17 Brian Neil Baker Shared memory access and data structure access control

Also Published As

Publication number Publication date
EP0789303B1 (de) 2002-05-08
DE69712382T2 (de) 2002-11-07
EP0789303A1 (de) 1997-08-13
US5721871A (en) 1998-02-24

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee