DE69719968D1 - Stabilisierkreise für mehrere digitale bits - Google Patents

Stabilisierkreise für mehrere digitale bits

Info

Publication number
DE69719968D1
DE69719968D1 DE69719968T DE69719968T DE69719968D1 DE 69719968 D1 DE69719968 D1 DE 69719968D1 DE 69719968 T DE69719968 T DE 69719968T DE 69719968 T DE69719968 T DE 69719968T DE 69719968 D1 DE69719968 D1 DE 69719968D1
Authority
DE
Germany
Prior art keywords
memory
charge
memory cells
memory system
predetermined levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69719968T
Other languages
English (en)
Other versions
DE69719968T2 (de
Inventor
J Korsh
M Khan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agate Semiconductor Inc
Original Assignee
Agate Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agate Semiconductor Inc filed Critical Agate Semiconductor Inc
Publication of DE69719968D1 publication Critical patent/DE69719968D1/de
Application granted granted Critical
Publication of DE69719968T2 publication Critical patent/DE69719968T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
DE69719968T 1996-04-30 1997-04-28 Stabilisierkreise für mehrere digitale bits Expired - Fee Related DE69719968T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US640367 1996-04-30
US08/640,367 US5815439A (en) 1996-04-30 1996-04-30 Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell
PCT/US1997/007152 WO1997041640A1 (en) 1996-04-30 1997-04-28 Stabilization circuits for multiple digital bits

Publications (2)

Publication Number Publication Date
DE69719968D1 true DE69719968D1 (de) 2003-04-24
DE69719968T2 DE69719968T2 (de) 2004-01-08

Family

ID=24567961

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69719968T Expired - Fee Related DE69719968T2 (de) 1996-04-30 1997-04-28 Stabilisierkreise für mehrere digitale bits

Country Status (9)

Country Link
US (2) US5815439A (de)
EP (1) EP0896763B1 (de)
JP (1) JP3706146B2 (de)
KR (1) KR100522561B1 (de)
CN (1) CN1126256C (de)
AT (1) ATE235094T1 (de)
DE (1) DE69719968T2 (de)
TW (1) TW345660B (de)
WO (1) WO1997041640A1 (de)

Families Citing this family (115)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6857099B1 (en) * 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
JP3159105B2 (ja) * 1997-02-21 2001-04-23 日本電気株式会社 不揮発性半導体記憶装置及びその書込方法
US6781883B1 (en) * 1997-03-20 2004-08-24 Altera Corporation Apparatus and method for margin testing single polysilicon EEPROM cells
JPH1139886A (ja) * 1997-07-14 1999-02-12 Rohm Co Ltd 半導体メモリ
KR100292625B1 (ko) * 1998-06-29 2001-07-12 박종섭 고속인터페이스장치
US6282145B1 (en) * 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
US6198662B1 (en) 1999-06-24 2001-03-06 Amic Technology, Inc. Circuit and method for pre-erasing/erasing flash memory array
US6166962A (en) * 1999-06-24 2000-12-26 Amic Technology, Inc. Circuit and method for conditioning flash memory array
US6211698B1 (en) * 1999-06-29 2001-04-03 Hyundai Electronics Industries Co., Ltd. High speed interface apparatus
KR20010005001A (ko) 1999-06-30 2001-01-15 김영환 플래쉬 메모리 셀의 제조 방법
KR20010004990A (ko) 1999-06-30 2001-01-15 김영환 플래쉬 이이피롬 셀 및 그 제조 방법
WO2001027931A1 (en) * 1999-10-08 2001-04-19 Aplus Flash Technology, Inc. Multiple level flash memory
US6259627B1 (en) * 2000-01-27 2001-07-10 Multi Level Memory Technology Read and write operations using constant row line voltage and variable column line load
US6219276B1 (en) * 2000-02-25 2001-04-17 Advanced Micro Devices, Inc. Multilevel cell programming
US6829571B1 (en) * 2000-06-15 2004-12-07 Hewlett-Packard Development Company, L.P. Method of determining DC margin of a latch
DE60102203D1 (de) * 2000-12-15 2004-04-08 St Microelectronics Srl Programmierverfahren für eine Mehrpegelspeicherzelle
US6493261B1 (en) 2001-01-31 2002-12-10 Advanced Micro Devices, Inc. Single bit array edges
US6344994B1 (en) 2001-01-31 2002-02-05 Advanced Micro Devices Data retention characteristics as a result of high temperature bake
US6456533B1 (en) 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Higher program VT and faster programming rates based on improved erase methods
US6307784B1 (en) 2001-02-28 2001-10-23 Advanced Micro Devices Negative gate erase
US6442074B1 (en) 2001-02-28 2002-08-27 Advanced Micro Devices, Inc. Tailored erase method using higher program VT and higher negative gate erase
KR100391154B1 (ko) * 2001-05-14 2003-07-12 삼성전자주식회사 불휘발성 반도체 메모리 장치의 프로그램 방법 및 장치
US6512701B1 (en) 2001-06-21 2003-01-28 Advanced Micro Devices, Inc. Erase method for dual bit virtual ground flash
US6614695B2 (en) * 2001-08-24 2003-09-02 Micron Technology, Inc. Non-volatile memory with block erase
JP4206683B2 (ja) * 2002-03-27 2009-01-14 セイコーエプソン株式会社 強誘電体メモリ
US7051127B2 (en) * 2002-05-10 2006-05-23 Hewlett-Packard Development Company, L.P. Method and apparatus for selectively providing data pre-emphasis based upon data content history
WO2004001606A1 (en) * 2002-06-20 2003-12-31 Tokyo Electron Device Limited Memory device, memory managing method and program
DE60230129D1 (de) * 2002-07-10 2009-01-15 St Microelectronics Srl Zeilenauswahlschaltung für Speicherzellenarray
US6856534B2 (en) * 2002-09-30 2005-02-15 Texas Instruments Incorporated Ferroelectric memory with wide operating voltage and multi-bit storage per cell
US6754103B2 (en) * 2002-11-04 2004-06-22 Silicon Storage Technology, Inc. Method and apparatus for programming and testing a non-volatile memory cell for storing multibit states
JP3935139B2 (ja) * 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
US7009889B2 (en) * 2004-05-28 2006-03-07 Sandisk Corporation Comprehensive erase verification for non-volatile memory
JP4713873B2 (ja) * 2004-11-12 2011-06-29 株式会社東芝 半導体記憶装置
KR100648254B1 (ko) * 2004-12-01 2006-11-24 삼성전자주식회사 소거시간을 줄일 수 있는 불휘발성 메모리 장치 및 그것의소거방법
US20070086244A1 (en) * 2005-10-17 2007-04-19 Msystems Ltd. Data restoration in case of page-programming failure
US7844879B2 (en) 2006-01-20 2010-11-30 Marvell World Trade Ltd. Method and system for error correction in flash memory
WO2007132456A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device with adaptive capacity
WO2007132452A2 (en) * 2006-05-12 2007-11-22 Anobit Technologies Reducing programming error in memory devices
CN103258572B (zh) 2006-05-12 2016-12-07 苹果公司 存储设备中的失真估计和消除
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US7877564B2 (en) * 2006-08-05 2011-01-25 Benhov Gmbh, Llc Memory configuration and method for calibrating read/write data based on performance characteristics of the memory configuration
US8060806B2 (en) 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
CN101601094B (zh) 2006-10-30 2013-03-27 苹果公司 使用多个门限读取存储单元的方法
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
WO2008068747A2 (en) 2006-12-03 2008-06-12 Anobit Technologies Ltd. Automatic defect management in memory devices
US7593263B2 (en) 2006-12-17 2009-09-22 Anobit Technologies Ltd. Memory device with reduced reading latency
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7539052B2 (en) 2006-12-28 2009-05-26 Micron Technology, Inc. Non-volatile multilevel memory cell programming
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
WO2008111058A2 (en) 2007-03-12 2008-09-18 Anobit Technologies Ltd. Adaptive estimation of memory cell read thresholds
US7729165B2 (en) * 2007-03-29 2010-06-01 Flashsilicon, Incorporation Self-adaptive and self-calibrated multiple-level non-volatile memories
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
WO2008139441A2 (en) 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8060798B2 (en) 2007-07-19 2011-11-15 Micron Technology, Inc. Refresh of non-volatile memory cells based on fatigue conditions
US7489543B1 (en) * 2007-07-25 2009-02-10 Micron Technology, Inc. Programming multilevel cell memory arrays
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
WO2009063450A2 (en) 2007-11-13 2009-05-22 Anobit Technologies Optimized selection of memory units in multi-unit memory devices
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
KR101378365B1 (ko) * 2008-03-12 2014-03-28 삼성전자주식회사 하이브리드 메모리 데이터 검출 장치 및 방법
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US7924613B1 (en) * 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8677203B1 (en) 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
KR101882853B1 (ko) * 2011-12-21 2018-08-27 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
US8797804B2 (en) 2012-07-30 2014-08-05 Micron Technology, Inc. Vertical memory with body connection
US9378830B2 (en) 2013-07-16 2016-06-28 Seagate Technology Llc Partial reprogramming of solid-state non-volatile memory cells
KR102248276B1 (ko) * 2014-05-26 2021-05-07 삼성전자주식회사 스토리지 장치의 동작 방법
US9548107B1 (en) * 2015-07-09 2017-01-17 Kabushiki Kaisha Toshiba Semiconductor memory device
US9753657B2 (en) * 2015-09-18 2017-09-05 Sandisk Technologies Llc Dynamic reconditioning of charge trapped based memory
US9928126B1 (en) 2017-06-01 2018-03-27 Apple Inc. Recovery from cross-temperature read failures by programming neighbor word lines
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771404A (en) * 1984-09-05 1988-09-13 Nippon Telegraph And Telephone Corporation Memory device employing multilevel storage circuits
US5043940A (en) * 1988-06-08 1991-08-27 Eliyahou Harari Flash EEPROM memory systems having multistate storage cells
US5293560A (en) * 1988-06-08 1994-03-08 Eliyahou Harari Multi-state flash EEPROM system using incremental programing and erasing methods
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US4890259A (en) * 1988-07-13 1989-12-26 Information Storage Devices High density integrated circuit analog signal recording and playback system
US4989179A (en) * 1988-07-13 1991-01-29 Information Storage Devices, Inc. High density integrated circuit analog signal recording and playback system
US5172338B1 (en) * 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US5218569A (en) * 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
US5657332A (en) * 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
US5258759A (en) * 1992-10-16 1993-11-02 California Institute Of Technology Method and apparatus for monotonic algorithmic digital-to-analog and analog-to-digital conversion
US5479170A (en) * 1992-10-16 1995-12-26 California Institute Of Technology Method and apparatus for long-term multi-valued storage in dynamic analog memory
US5365486A (en) * 1992-12-16 1994-11-15 Texas Instruments Incorporated Method and circuitry for refreshing a flash electrically erasable, programmable read only memory
US5422842A (en) * 1993-07-08 1995-06-06 Sundisk Corporation Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
US5511020A (en) * 1993-11-23 1996-04-23 Monolithic System Technology, Inc. Pseudo-nonvolatile memory incorporating data refresh operation
GB9401227D0 (en) * 1994-01-22 1994-03-16 Deas Alexander R Non-volatile digital memory device with multi-level storage cells
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells
GB9415539D0 (en) * 1994-08-02 1994-09-21 Deas Alexander R Bit resolution optimising mechanism

Also Published As

Publication number Publication date
TW345660B (en) 1998-11-21
ATE235094T1 (de) 2003-04-15
JP2001508218A (ja) 2001-06-19
KR100522561B1 (ko) 2006-01-27
US5815439A (en) 1998-09-29
CN1268261A (zh) 2000-09-27
KR20000065145A (ko) 2000-11-06
EP0896763A4 (de) 2000-08-16
EP0896763A1 (de) 1999-02-17
US5901089A (en) 1999-05-04
EP0896763B1 (de) 2003-03-19
CN1126256C (zh) 2003-10-29
WO1997041640A1 (en) 1997-11-06
JP3706146B2 (ja) 2005-10-12
DE69719968T2 (de) 2004-01-08

Similar Documents

Publication Publication Date Title
DE69719968D1 (de) Stabilisierkreise für mehrere digitale bits
US7492642B2 (en) Flash memory device capable of reduced programming time
TW326093B (en) Non-volatile semiconductor memory device
TW373337B (en) Non-volatile semiconductor memory
TW343307B (en) Nonvolatile memory system and nonvolatile semiconductor memory
GB9519670D0 (en) Algorithm for an improved flash memory storage system
EP0822557A3 (de) Nichtflüchtige Halbleiterspeicheranordnung mit variabler Source-Spannung
TW350048B (en) Non-volatile semiconductor memory and the writing method
TW355839B (en) Non-volatile memory cell and method for programming the same
FI942045A0 (fi) Systeemi sähkökemiallisten teholähteiden tutkimiseksi ja hallitsemiseksi
EP1239490A3 (de) Integrierte Schaltung zur Speicherung und Rückgewinnung von mehreren digitalen Bits pro nichtflüchtiger Speicherzelle
TW366495B (en) Multiple writes per a single erase for a nonvolatile memory
TW365002B (en) High speed programming method for non-volatile semiconductor memory apparatus
MY140850A (en) Program recording apparatus and program recording medium
KR960006084A (ko) 불휘발성 반도체 기억장치와 그 소거방법
DE69333631D1 (de) Halbleiterspeicheranordnung
TW333704B (en) The semiconductor memory device
DE3475360D1 (en) Circuit arrangement comprising a memory and an access control unit
TW374925B (en) Non-volatile storage device
JPS5792488A (en) Nonvolatile memory
KR970017665A (ko) 가변 기록 및 소거 시간 주기를 갖는 비휘발성 반도체 메모리 장치
TW334566B (en) Non-volatile semiconductor memory device
EP0108681A3 (de) Bit-löschbarer EEPROM
US5153854A (en) EEPROM memory system having selectable programming voltage for low power readability
DE69632999D1 (de) Löschspannungs-Steuerschaltkreis für eine löschbare, nichtflüchtige Speicherzelle

Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee