DE69729243D1 - Multiprozessorsystem mit Vorrichtung zur Optimierung von Spin-Lock-Operationen - Google Patents
Multiprozessorsystem mit Vorrichtung zur Optimierung von Spin-Lock-OperationenInfo
- Publication number
- DE69729243D1 DE69729243D1 DE69729243T DE69729243T DE69729243D1 DE 69729243 D1 DE69729243 D1 DE 69729243D1 DE 69729243 T DE69729243 T DE 69729243T DE 69729243 T DE69729243 T DE 69729243T DE 69729243 D1 DE69729243 D1 DE 69729243D1
- Authority
- DE
- Germany
- Prior art keywords
- multiprocessor system
- lock operations
- optimizing
- spin
- optimizing spin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/466—Transaction processing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture
- G06F2212/254—Distributed memory
- G06F2212/2542—Non-uniform memory access [NUMA] architecture
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US674272 | 1996-07-01 | ||
US08/674,272 US5860159A (en) | 1996-07-01 | 1996-07-01 | Multiprocessing system including an apparatus for optimizing spin--lock operations |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69729243D1 true DE69729243D1 (de) | 2004-07-01 |
DE69729243T2 DE69729243T2 (de) | 2005-05-25 |
Family
ID=24705983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69729243T Expired - Lifetime DE69729243T2 (de) | 1996-07-01 | 1997-06-27 | Multiprozessorsystem mit Vorrichtung zur Optimierung von Spin-Lock-Operationen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5860159A (de) |
EP (1) | EP0817042B1 (de) |
JP (1) | JPH10187470A (de) |
DE (1) | DE69729243T2 (de) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6662216B1 (en) * | 1997-04-14 | 2003-12-09 | International Business Machines Corporation | Fixed bus tags for SMP buses |
CA2241909A1 (en) * | 1997-07-10 | 1999-01-10 | Howard Thomas Olnowich | Cache coherent network, network adapter and message protocol for scalable shared memory processing systems |
US6047316A (en) * | 1997-12-12 | 2000-04-04 | Intel Corporation | Multiprocessor computing apparatus having spin lock fairness |
US6023747A (en) * | 1997-12-17 | 2000-02-08 | International Business Machines Corporation | Method and system for handling conflicts between cache operation requests in a data processing system |
US6480927B1 (en) * | 1997-12-31 | 2002-11-12 | Unisys Corporation | High-performance modular memory system with crossbar connections |
US6415364B1 (en) * | 1997-12-31 | 2002-07-02 | Unisys Corporation | High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems |
US6347363B1 (en) * | 1998-02-17 | 2002-02-12 | International Business Machines Corporation | Merged vertical cache controller mechanism with combined cache controller and snoop queries for in-line caches |
US6182196B1 (en) * | 1998-02-20 | 2001-01-30 | Ati International Srl | Method and apparatus for arbitrating access requests to a memory |
FR2780178B1 (fr) * | 1998-06-18 | 2001-08-10 | Inst Nat Rech Inf Automat | Procede de transformation et d'acheminement de donnees entre des serveurs d'agents presents sur des machines et un serveur d'agent central present sur une autre machine |
US6148300A (en) * | 1998-06-19 | 2000-11-14 | Sun Microsystems, Inc. | Hybrid queue and backoff computer resource lock featuring different spin speeds corresponding to multiple-states |
US6115804A (en) * | 1999-02-10 | 2000-09-05 | International Business Machines Corporation | Non-uniform memory access (NUMA) data processing system that permits multiple caches to concurrently hold data in a recent state from which data can be sourced by shared intervention |
US6272602B1 (en) * | 1999-03-08 | 2001-08-07 | Sun Microsystems, Inc. | Multiprocessing system employing pending tags to maintain cache coherence |
US6484272B1 (en) * | 1999-09-30 | 2002-11-19 | Bull Hn Information Systems, Inc. | Gate close balking for fair gating in a nonuniform memory architecture data processing system |
US6473819B1 (en) | 1999-12-17 | 2002-10-29 | International Business Machines Corporation | Scalable interruptible queue locks for shared-memory multiprocessor |
US6813767B1 (en) * | 2000-06-30 | 2004-11-02 | Intel Corporation | Prioritizing transaction requests with a delayed transaction reservation buffer |
US7640315B1 (en) | 2000-08-04 | 2009-12-29 | Advanced Micro Devices, Inc. | Implementing locks in a distributed processing system |
US6826619B1 (en) | 2000-08-21 | 2004-11-30 | Intel Corporation | Method and apparatus for preventing starvation in a multi-node architecture |
US6487643B1 (en) | 2000-09-29 | 2002-11-26 | Intel Corporation | Method and apparatus for preventing starvation in a multi-node architecture |
US6772298B2 (en) | 2000-12-20 | 2004-08-03 | Intel Corporation | Method and apparatus for invalidating a cache line without data return in a multi-node architecture |
US7234029B2 (en) * | 2000-12-28 | 2007-06-19 | Intel Corporation | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture |
US6791412B2 (en) * | 2000-12-28 | 2004-09-14 | Intel Corporation | Differential amplifier output stage |
US20020087775A1 (en) * | 2000-12-29 | 2002-07-04 | Looi Lily P. | Apparatus and method for interrupt delivery |
US20020087766A1 (en) * | 2000-12-29 | 2002-07-04 | Akhilesh Kumar | Method and apparatus to implement a locked-bus transaction |
US6721918B2 (en) | 2000-12-29 | 2004-04-13 | Intel Corporation | Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect |
JP3628265B2 (ja) * | 2001-02-21 | 2005-03-09 | 株式会社半導体理工学研究センター | マルチプロセッサシステム装置 |
US6971098B2 (en) | 2001-06-27 | 2005-11-29 | Intel Corporation | Method and apparatus for managing transaction requests in a multi-node architecture |
US7895239B2 (en) * | 2002-01-04 | 2011-02-22 | Intel Corporation | Queue arrays in network devices |
US7480909B2 (en) * | 2002-02-25 | 2009-01-20 | International Business Machines Corporation | Method and apparatus for cooperative distributed task management in a storage subsystem with multiple controllers using cache locking |
US6862668B2 (en) | 2002-02-25 | 2005-03-01 | International Business Machines Corporation | Method and apparatus for using cache coherency locking to facilitate on-line volume expansion in a multi-controller storage system |
JP3791433B2 (ja) * | 2002-02-27 | 2006-06-28 | 日本電気株式会社 | システム、制御処理装置、およびシステム制御方法 |
EP1376370B1 (de) * | 2002-06-28 | 2017-06-14 | Oracle America, Inc. | Mechanismus zum verhindern von Datenausfall bei Aufrechterhaltung der Datenkoherenz in den cache-speichern eines Komputersystems |
US7155588B1 (en) * | 2002-08-12 | 2006-12-26 | Cisco Technology, Inc. | Memory fence with background lock release |
US8185602B2 (en) | 2002-11-05 | 2012-05-22 | Newisys, Inc. | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters |
US7324995B2 (en) * | 2003-11-17 | 2008-01-29 | Rackable Systems Inc. | Method for retrieving and modifying data elements on a shared medium |
US20050108300A1 (en) * | 2003-11-17 | 2005-05-19 | Terrascale Technologies Inc. | Method for the management of local client cache buffers in a clustered computer environment |
US7380073B2 (en) * | 2003-11-26 | 2008-05-27 | Sas Institute Inc. | Computer-implemented system and method for lock handling |
US20060101469A1 (en) * | 2004-11-10 | 2006-05-11 | International Business Machines (Ibm) Corporation | Method, controller, program product and services for managing resource element queues |
US20070150658A1 (en) * | 2005-12-28 | 2007-06-28 | Jaideep Moses | Pinning locks in shared cache |
US8099538B2 (en) | 2006-03-29 | 2012-01-17 | Intel Corporation | Increasing functionality of a reader-writer lock |
US7861093B2 (en) * | 2006-08-30 | 2010-12-28 | International Business Machines Corporation | Managing data access via a loop only if changed locking facility |
GB0617454D0 (en) * | 2006-09-06 | 2006-10-18 | Guaranteed Markets Ltd | Apparatus & method for prioritising sellers in electronic markets |
US9292436B2 (en) * | 2007-06-25 | 2016-03-22 | Sonics, Inc. | Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary |
US9213586B2 (en) * | 2009-03-18 | 2015-12-15 | Sas Institute Inc. | Computer-implemented systems for resource level locking without resource level locks |
US8572617B2 (en) | 2009-07-21 | 2013-10-29 | Sas Institute Inc. | Processor-implemented systems and methods for event handling |
JP2011150422A (ja) * | 2010-01-19 | 2011-08-04 | Renesas Electronics Corp | データ処理装置 |
US10921874B2 (en) | 2017-03-06 | 2021-02-16 | Facebook Technologies, Llc | Hardware-based operating point controller for circuit regions in an integrated circuit |
US11231769B2 (en) | 2017-03-06 | 2022-01-25 | Facebook Technologies, Llc | Sequencer-based protocol adapter |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE68924306T2 (de) * | 1988-06-27 | 1996-05-09 | Digital Equipment Corp | Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern. |
US5175837A (en) * | 1989-02-03 | 1992-12-29 | Digital Equipment Corporation | Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits |
US5195089A (en) * | 1990-12-31 | 1993-03-16 | Sun Microsystems, Inc. | Apparatus and method for a synchronous, high speed, packet-switched bus |
US5649157A (en) * | 1995-03-30 | 1997-07-15 | Hewlett-Packard Co. | Memory controller with priority queues |
US5657472A (en) * | 1995-03-31 | 1997-08-12 | Sun Microsystems, Inc. | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor |
-
1996
- 1996-07-01 US US08/674,272 patent/US5860159A/en not_active Expired - Lifetime
-
1997
- 1997-06-27 EP EP97304611A patent/EP0817042B1/de not_active Expired - Lifetime
- 1997-06-27 DE DE69729243T patent/DE69729243T2/de not_active Expired - Lifetime
- 1997-06-30 JP JP9208235A patent/JPH10187470A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH10187470A (ja) | 1998-07-21 |
US5860159A (en) | 1999-01-12 |
EP0817042B1 (de) | 2004-05-26 |
DE69729243T2 (de) | 2005-05-25 |
EP0817042A3 (de) | 2001-11-21 |
EP0817042A2 (de) | 1998-01-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |