DE69736646D1 - Verfahren zum Zertrennen von Wafern in Einzelchips - Google Patents

Verfahren zum Zertrennen von Wafern in Einzelchips

Info

Publication number
DE69736646D1
DE69736646D1 DE69736646T DE69736646T DE69736646D1 DE 69736646 D1 DE69736646 D1 DE 69736646D1 DE 69736646 T DE69736646 T DE 69736646T DE 69736646 T DE69736646 T DE 69736646T DE 69736646 D1 DE69736646 D1 DE 69736646D1
Authority
DE
Germany
Prior art keywords
single chips
dicing wafers
dicing
wafers
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69736646T
Other languages
English (en)
Other versions
DE69736646T2 (de
Inventor
Hisashi Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69736646D1 publication Critical patent/DE69736646D1/de
Publication of DE69736646T2 publication Critical patent/DE69736646T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
DE69736646T 1996-07-10 1997-07-09 Verfahren zum Zertrennen von Wafern in Einzelchips Expired - Fee Related DE69736646T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8179723A JPH1027971A (ja) 1996-07-10 1996-07-10 有機薄膜多層配線基板の切断方法
JP17972396 1996-07-10

Publications (2)

Publication Number Publication Date
DE69736646D1 true DE69736646D1 (de) 2006-10-26
DE69736646T2 DE69736646T2 (de) 2007-01-04

Family

ID=16070753

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69736646T Expired - Fee Related DE69736646T2 (de) 1996-07-10 1997-07-09 Verfahren zum Zertrennen von Wafern in Einzelchips

Country Status (5)

Country Link
US (1) US6117347A (de)
EP (1) EP0818818B1 (de)
JP (1) JPH1027971A (de)
CA (1) CA2209884C (de)
DE (1) DE69736646T2 (de)

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Also Published As

Publication number Publication date
EP0818818B1 (de) 2006-09-13
US6117347A (en) 2000-09-12
JPH1027971A (ja) 1998-01-27
DE69736646T2 (de) 2007-01-04
EP0818818A1 (de) 1998-01-14
CA2209884A1 (en) 1998-01-10
CA2209884C (en) 2001-07-03

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8339 Ceased/non-payment of the annual fee