DE69801744T2 - Verfahren und system zur fehlerisolierung für pci-busfehler - Google Patents

Verfahren und system zur fehlerisolierung für pci-busfehler

Info

Publication number
DE69801744T2
DE69801744T2 DE69801744T DE69801744T DE69801744T2 DE 69801744 T2 DE69801744 T2 DE 69801744T2 DE 69801744 T DE69801744 T DE 69801744T DE 69801744 T DE69801744 T DE 69801744T DE 69801744 T2 DE69801744 T2 DE 69801744T2
Authority
DE
Germany
Prior art keywords
pci bus
bus faults
fault insulation
fault
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69801744T
Other languages
English (en)
Other versions
DE69801744D1 (de
Inventor
Andrew Mclaughlin
Alongkorn Kitamorn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69801744D1 publication Critical patent/DE69801744D1/de
Application granted granted Critical
Publication of DE69801744T2 publication Critical patent/DE69801744T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
DE69801744T 1997-03-31 1998-03-23 Verfahren und system zur fehlerisolierung für pci-busfehler Expired - Lifetime DE69801744T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/829,088 US6557121B1 (en) 1997-03-31 1997-03-31 Method and system for fault isolation for PCI bus errors
PCT/EP1998/001674 WO1998044417A1 (en) 1997-03-31 1998-03-23 A method and system for fault isolation for pci bus errors

Publications (2)

Publication Number Publication Date
DE69801744D1 DE69801744D1 (de) 2001-10-25
DE69801744T2 true DE69801744T2 (de) 2002-07-04

Family

ID=25253497

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69801744T Expired - Lifetime DE69801744T2 (de) 1997-03-31 1998-03-23 Verfahren und system zur fehlerisolierung für pci-busfehler

Country Status (9)

Country Link
US (1) US6557121B1 (de)
EP (1) EP0972245B1 (de)
JP (1) JP4015740B2 (de)
CN (1) CN1146797C (de)
CZ (1) CZ346099A3 (de)
DE (1) DE69801744T2 (de)
PL (1) PL335938A1 (de)
SG (1) SG76539A1 (de)
WO (1) WO1998044417A1 (de)

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JP2016186719A (ja) * 2015-03-27 2016-10-27 富士通株式会社 入出力制御装置、情報処理装置及び入出力制御装置の制御方法
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Also Published As

Publication number Publication date
JPH113294A (ja) 1999-01-06
JP4015740B2 (ja) 2007-11-28
SG76539A1 (en) 2000-11-21
CZ346099A3 (cs) 1999-12-15
WO1998044417A1 (en) 1998-10-08
EP0972245B1 (de) 2001-09-19
US6557121B1 (en) 2003-04-29
CN1197954A (zh) 1998-11-04
PL335938A1 (en) 2000-05-22
CN1146797C (zh) 2004-04-21
DE69801744D1 (de) 2001-10-25
EP0972245A1 (de) 2000-01-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7