DE69802562T2 - Prozessor mit vordekodierung von relativen verzweigungsbefehlen - Google Patents

Prozessor mit vordekodierung von relativen verzweigungsbefehlen

Info

Publication number
DE69802562T2
DE69802562T2 DE69802562T DE69802562T DE69802562T2 DE 69802562 T2 DE69802562 T2 DE 69802562T2 DE 69802562 T DE69802562 T DE 69802562T DE 69802562 T DE69802562 T DE 69802562T DE 69802562 T2 DE69802562 T2 DE 69802562T2
Authority
DE
Germany
Prior art keywords
processor
code relative
relative branching
branching commands
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69802562T
Other languages
English (en)
Other versions
DE69802562D1 (de
Inventor
B Witt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69802562D1 publication Critical patent/DE69802562D1/de
Publication of DE69802562T2 publication Critical patent/DE69802562T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
DE69802562T 1997-11-17 1998-09-11 Prozessor mit vordekodierung von relativen verzweigungsbefehlen Expired - Lifetime DE69802562T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6587897P 1997-11-17 1997-11-17
US09/065,681 US6167506A (en) 1997-11-17 1998-04-23 Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
PCT/US1998/019045 WO1999026135A1 (en) 1997-11-17 1998-09-11 Processor configured to predecode relative control transfer instructions

Publications (2)

Publication Number Publication Date
DE69802562D1 DE69802562D1 (de) 2001-12-20
DE69802562T2 true DE69802562T2 (de) 2002-07-25

Family

ID=26745860

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69802562T Expired - Lifetime DE69802562T2 (de) 1997-11-17 1998-09-11 Prozessor mit vordekodierung von relativen verzweigungsbefehlen

Country Status (4)

Country Link
US (2) US6167506A (de)
EP (1) EP1031075B1 (de)
DE (1) DE69802562T2 (de)
WO (1) WO1999026135A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3798563B2 (ja) * 1999-01-06 2006-07-19 株式会社東芝 命令キャッシュメモリ
US6330662B1 (en) * 1999-02-23 2001-12-11 Sun Microsystems, Inc. Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures
JP2001067335A (ja) * 1999-06-23 2001-03-16 Denso Corp マイクロコンピュータ
US7032100B1 (en) * 1999-12-17 2006-04-18 Koninklijke Philips Electronics N.V. Simple algorithmic cryptography engine
JP2001243070A (ja) * 2000-02-29 2001-09-07 Toshiba Corp プロセッサ及び分岐予測方法並びにコンパイル方法
US6795876B1 (en) * 2001-03-27 2004-09-21 Intel Corporation Adaptive read pre-fetch
GB2381602B (en) * 2001-10-12 2004-04-14 Siroyan Ltd Early resolving instructions
US7092869B2 (en) * 2001-11-14 2006-08-15 Ronald Hilton Memory address prediction under emulation
US6948053B2 (en) * 2002-02-25 2005-09-20 International Business Machines Corporation Efficiently calculating a branch target address
US6816962B2 (en) * 2002-02-25 2004-11-09 International Business Machines Corporation Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
US7321954B2 (en) * 2004-08-11 2008-01-22 International Business Machines Corporation Method for software controllable dynamically lockable cache line replacement system
US20060155961A1 (en) * 2005-01-06 2006-07-13 International Business Machines Corporation Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor
US7487334B2 (en) * 2005-02-03 2009-02-03 International Business Machines Corporation Branch encoding before instruction cache write
JP2007041837A (ja) * 2005-08-03 2007-02-15 Nec Electronics Corp 命令プリフェッチ装置及び命令プリフェッチ方法
US7404042B2 (en) * 2005-05-18 2008-07-22 Qualcomm Incorporated Handling cache miss in an instruction crossing a cache line boundary
JP5012084B2 (ja) * 2007-02-22 2012-08-29 富士通セミコンダクター株式会社 情報処理装置
US8566797B2 (en) * 2008-02-27 2013-10-22 Red Hat, Inc. Heuristic backtracer
US7941653B2 (en) * 2008-12-04 2011-05-10 Analog Devices, Inc. Jump instruction having a reference to a pointer for accessing a branch address table
US20130138888A1 (en) * 2011-11-30 2013-05-30 Jama I. Barreh Storing a target address of a control transfer instruction in an instruction field
WO2013101121A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Managed instruction cache prefetching
US9990199B2 (en) * 2015-09-18 2018-06-05 Axis Ab Conditional flow with hardware acceleration

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4502111A (en) * 1981-05-29 1985-02-26 Harris Corporation Token generator
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5155820A (en) * 1989-02-21 1992-10-13 Gibson Glenn A Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
EP0415366B1 (de) * 1989-08-28 1997-06-11 Nec Corporation Mikroprozessor mit Pipeline-Predecodereinheit und -Hauptdecodereinheit
JPH0650465B2 (ja) * 1989-10-16 1994-06-29 株式会社東芝 分岐制御回路
CA2038264C (en) * 1990-06-26 1995-06-27 Richard James Eickemeyer In-memory preprocessor for a scalable compound instruction set machine processor
WO1992006426A1 (en) * 1990-10-09 1992-04-16 Nexgen Microsystems Method and apparatus for parallel decoding of instructions with branch prediction look-up
JPH04156613A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 命令バッファ装置
US5313605A (en) * 1990-12-20 1994-05-17 Intel Corporation High bandwith output hierarchical memory store including a cache, fetch buffer and ROM
DE69231011T2 (de) * 1991-02-08 2000-09-28 Fujitsu Ltd Cachespeicher zur Verarbeitung von Befehlsdaten und Datenprozessor mit demselben
GB2263987B (en) * 1992-02-06 1996-03-06 Intel Corp End bit markers for instruction decode
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5337415A (en) * 1992-12-04 1994-08-09 Hewlett-Packard Company Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency
EP0649224B1 (de) * 1993-09-23 1999-03-03 Lg Electronics Inc. Variabler Längen-Kodieren und variabler Längen-Dekodierer
DE69434669T2 (de) * 1993-10-29 2006-10-12 Advanced Micro Devices, Inc., Sunnyvale Spekulative Befehlswarteschlange für Befehle mit variabler Byteslänge
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
EP0950946B1 (de) * 1993-11-05 2001-08-16 Intergraph Corporation Superskalare Rechnerarchitektur mit Softwarescheduling
US5634025A (en) * 1993-12-09 1997-05-27 International Business Machines Corporation Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units
US5566298A (en) * 1994-03-01 1996-10-15 Intel Corporation Method for state recovery during assist and restart in a decoder having an alias mechanism
US5586277A (en) * 1994-03-01 1996-12-17 Intel Corporation Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
US5600806A (en) * 1994-03-01 1997-02-04 Intel Corporation Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US5559975A (en) * 1994-06-01 1996-09-24 Advanced Micro Devices, Inc. Program counter update mechanism
US5499204A (en) * 1994-07-05 1996-03-12 Motorola, Inc. Memory cache with interlaced data and method of operation
US5608886A (en) 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5758116A (en) * 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
JPH08106387A (ja) * 1994-10-06 1996-04-23 Oki Electric Ind Co Ltd 命令プリフェッチ回路及びキャッシュ装置
US5692168A (en) * 1994-10-18 1997-11-25 Cyrix Corporation Prefetch buffer using flow control bit to identify changes of flow within the code stream
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
EP0730220A3 (de) * 1995-03-03 1997-01-08 Hal Computer Systems Inc Verfahren und Vorrichtung zur schnellen Ausführung von Verzweigungsbefehlen
US5819059A (en) * 1995-04-12 1998-10-06 Advanced Micro Devices, Inc. Predecode unit adapted for variable byte-length instruction set processors and method of operating the same
US5822558A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5758114A (en) * 1995-04-12 1998-05-26 Advanced Micro Devices, Inc. High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor
US6049863A (en) 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US5872943A (en) * 1996-07-26 1999-02-16 Advanced Micro Devices, Inc. Apparatus for aligning instructions using predecoded shift amounts
US5968163A (en) * 1997-03-10 1999-10-19 Advanced Micro Devices, Inc. Microcode scan unit for scanning microcode instructions using predecode data
US5987235A (en) * 1997-04-04 1999-11-16 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
US5935238A (en) * 1997-06-19 1999-08-10 Sun Microsystems, Inc. Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles
US6134649A (en) 1997-11-17 2000-10-17 Advanced Micro Devices, Inc. Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction
US6061786A (en) 1998-04-23 2000-05-09 Advanced Micro Devices, Inc. Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction

Also Published As

Publication number Publication date
EP1031075B1 (de) 2001-11-14
EP1031075A1 (de) 2000-08-30
WO1999026135A1 (en) 1999-05-27
US6457117B1 (en) 2002-09-24
US6167506A (en) 2000-12-26
DE69802562D1 (de) 2001-12-20

Similar Documents

Publication Publication Date Title
DE69802562D1 (de) Prozessor mit vordekodierung von relativen verzweigungsbefehlen
ATE348151T1 (de) Protein mit phospholipaseaktivität
DE69827870D1 (de) Drebohrmeissel mit beweglichen Formation-eingreifenden Elementen
DE69812568D1 (de) Verbinder mit Abdeckung
IS5375A (is) KAY-nýstárlegt ónæmisprótín
DE69733511D1 (de) Radaranlage mit vereinfachter Bauart
PT996701E (pt) Polialquilenoiminas alcoxiladas compativeis com lixivia
DE69818878D1 (de) Copolyester mit verbesserter Klarheit
DE69634671D1 (de) Mit Nima interagierende Proteine
DE59710022D1 (de) Prozessor mit Pipelining-Aufbau
DE69718820D1 (de) Micropumpe mit eingebautem zwischenstück
NL1009421A1 (nl) Applicator.
ATE191318T1 (de) Büstenhalter mit versteifungsbügeln
DE69827350D1 (de) Ausgangsstufe mit anstiegs-steuermitteln
DE69738247D1 (de) Informationsprozessor mit Ablauffolgeplanungsfunktion
DE69811027T2 (de) Zirkulator mit konzentrierten Elementen
DE69836069D1 (de) Zweirichtungsthyristor
DE59803884D1 (de) Taumelscheibenkompressor
DE69835878D1 (de) IGFIIE/ IGFBP2 Komplex
DE69814326D1 (de) Kodierung von mausbefehlen
DE59808303D1 (de) Uv-optisches system mit reduzierter alterung
DE59811771D1 (de) Faltenbalg mit imprägnierung
DE69812288D1 (de) Förderer
ES1036909Y (es) Pupitre infantil.
DE29720648U1 (de) Spielsandkasten mit variabler Abdeckung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY