DE69804672T2 - Verfahren zur selektiven ablagerung ferroelektrischer schichten auf wismut basis - Google Patents

Verfahren zur selektiven ablagerung ferroelektrischer schichten auf wismut basis

Info

Publication number
DE69804672T2
DE69804672T2 DE69804672T DE69804672T DE69804672T2 DE 69804672 T2 DE69804672 T2 DE 69804672T2 DE 69804672 T DE69804672 T DE 69804672T DE 69804672 T DE69804672 T DE 69804672T DE 69804672 T2 DE69804672 T2 DE 69804672T2
Authority
DE
Germany
Prior art keywords
wismut
base
selective deposition
ferroelectric layers
ferroelectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69804672T
Other languages
English (en)
Other versions
DE69804672D1 (de
Inventor
Frank Hintermaier
Bryan Hendrix
R Roeder
Buskirk Peter Van
H Baum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Advanced Technology Materials Inc
Original Assignee
Siemens AG
Advanced Technology Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Advanced Technology Materials Inc filed Critical Siemens AG
Application granted granted Critical
Publication of DE69804672D1 publication Critical patent/DE69804672D1/de
Publication of DE69804672T2 publication Critical patent/DE69804672T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
DE69804672T 1997-12-23 1998-12-16 Verfahren zur selektiven ablagerung ferroelektrischer schichten auf wismut basis Expired - Fee Related DE69804672T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/996,575 US6120846A (en) 1997-12-23 1997-12-23 Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
PCT/US1998/026656 WO1999032685A1 (en) 1997-12-23 1998-12-16 Method for selectively depositing bismuth based ferroelectric films

Publications (2)

Publication Number Publication Date
DE69804672D1 DE69804672D1 (de) 2002-05-08
DE69804672T2 true DE69804672T2 (de) 2002-10-10

Family

ID=25543073

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69804672T Expired - Fee Related DE69804672T2 (de) 1997-12-23 1998-12-16 Verfahren zur selektiven ablagerung ferroelektrischer schichten auf wismut basis

Country Status (7)

Country Link
US (1) US6120846A (de)
EP (1) EP1042529B1 (de)
JP (1) JP2001527282A (de)
KR (1) KR20010033553A (de)
CN (1) CN1184348C (de)
DE (1) DE69804672T2 (de)
WO (1) WO1999032685A1 (de)

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US6500489B1 (en) * 1996-11-27 2002-12-31 Advanced Technology Materials, Inc. Low temperature CVD processes for preparing ferroelectric films using Bi alcoxides
US6693318B1 (en) * 1997-12-18 2004-02-17 Infineon Technologies North America Reduced diffusion of a mobile specie from a metal oxide ceramic
JPH11186523A (ja) * 1997-12-19 1999-07-09 Sharp Corp 絶縁体材料、絶縁膜被覆基板、その製造方法及びその用途
WO2000034550A2 (en) * 1998-12-09 2000-06-15 Infineon Technologies Ag Cvd processes using bi aryl
JP3596416B2 (ja) * 2000-03-29 2004-12-02 セイコーエプソン株式会社 セラミックスの製造方法およびその製造装置
JP3664033B2 (ja) * 2000-03-29 2005-06-22 セイコーエプソン株式会社 セラミックスの製造方法およびその製造装置
KR100382149B1 (ko) * 2000-11-30 2003-05-09 한국전자통신연구원 스트론튬 탄탈륨 산화물 박막 형성 방법
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7118726B2 (en) 2002-12-13 2006-10-10 Clark Manufacturing, Llc Method for making oxide compounds
KR100513724B1 (ko) * 2002-12-24 2005-09-08 삼성전자주식회사 강유전성 박막 및 그 제조방법
JP2004256510A (ja) * 2003-02-26 2004-09-16 Toyoshima Seisakusho:Kk Ｃｖｄ用ビスマス原料溶液及びこれを用いたビスマス含有薄膜の製造方法
US8478645B2 (en) * 2003-04-07 2013-07-02 Sevenecho, Llc Method, system and software for digital media narrative personalization
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
JP4632018B2 (ja) * 2003-10-15 2011-02-16 セイコーエプソン株式会社 強誘電体膜、強誘電体膜の製造方法、および強誘電体キャパシタ、ならびに強誘電体メモリ
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
JP4257537B2 (ja) * 2005-06-02 2009-04-22 セイコーエプソン株式会社 強誘電体層の製造方法、電子機器の製造方法、強誘電体メモリ装置の製造方法、圧電素子の製造方法、およびインクジェット式記録ヘッドの製造方法
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
CN1967749B (zh) * 2005-11-18 2010-05-12 同济大学 一种非铅铁电薄膜的低温制备方法
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
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Also Published As

Publication number Publication date
US6120846A (en) 2000-09-19
EP1042529A1 (de) 2000-10-11
KR20010033553A (ko) 2001-04-25
WO1999032685A1 (en) 1999-07-01
JP2001527282A (ja) 2001-12-25
CN1184348C (zh) 2005-01-12
CN1285007A (zh) 2001-02-21
EP1042529B1 (de) 2002-04-03
DE69804672D1 (de) 2002-05-08

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8339 Ceased/non-payment of the annual fee