DE69806497D1 - Bidirektionales kommunikationsport für digitalen signalprozessor - Google Patents

Bidirektionales kommunikationsport für digitalen signalprozessor

Info

Publication number
DE69806497D1
DE69806497D1 DE69806497T DE69806497T DE69806497D1 DE 69806497 D1 DE69806497 D1 DE 69806497D1 DE 69806497 T DE69806497 T DE 69806497T DE 69806497 T DE69806497 T DE 69806497T DE 69806497 D1 DE69806497 D1 DE 69806497D1
Authority
DE
Germany
Prior art keywords
digital signal
signal processor
communication port
bidirectional communication
bidirectional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69806497T
Other languages
English (en)
Other versions
DE69806497T2 (de
Inventor
Douglas Garde
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of DE69806497D1 publication Critical patent/DE69806497D1/de
Application granted granted Critical
Publication of DE69806497T2 publication Critical patent/DE69806497T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
DE69806497T 1997-11-03 1998-10-30 Bidirektionales kommunikationsport für digitalen signalprozessor Expired - Lifetime DE69806497T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US96274197A 1997-11-03 1997-11-03
PCT/US1998/023100 WO1999023787A2 (en) 1997-11-03 1998-10-30 Bidirectional communication port for digital signal processor

Publications (2)

Publication Number Publication Date
DE69806497D1 true DE69806497D1 (de) 2002-08-14
DE69806497T2 DE69806497T2 (de) 2003-03-27

Family

ID=25506287

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69806497T Expired - Lifetime DE69806497T2 (de) 1997-11-03 1998-10-30 Bidirektionales kommunikationsport für digitalen signalprozessor

Country Status (5)

Country Link
US (1) US6002882A (de)
EP (1) EP1027786B1 (de)
JP (1) JP4267818B2 (de)
DE (1) DE69806497T2 (de)
WO (1) WO1999023787A2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3117001B2 (ja) * 1997-06-04 2000-12-11 日本電気株式会社 デジタル信号処理装置
US6836838B1 (en) * 1998-06-29 2004-12-28 Cisco Technology, Inc. Architecture for a processor complex of an arrayed pipelined processing engine
US6853385B1 (en) 1999-11-09 2005-02-08 Broadcom Corporation Video, audio and graphics decode, composite and display system
US6768774B1 (en) 1998-11-09 2004-07-27 Broadcom Corporation Video and graphics system with video scaling
US7446774B1 (en) 1998-11-09 2008-11-04 Broadcom Corporation Video and graphics system with an integrated system bridge controller
US6636222B1 (en) 1999-11-09 2003-10-21 Broadcom Corporation Video and graphics system with an MPEG video decoder for concurrent multi-row decoding
US6927783B1 (en) 1998-11-09 2005-08-09 Broadcom Corporation Graphics display system with anti-aliased text and graphics feature
US6434654B1 (en) * 1999-03-26 2002-08-13 Koninklijke Philips Electronics N.V. System bus with a variable width selectivity configurable at initialization
KR100304582B1 (ko) * 1999-07-07 2001-11-01 구자홍 시리얼 데이터 통신 방법 및 장치
US6529748B1 (en) * 1999-09-30 2003-03-04 Motorola, Inc. Bilateral power management system
US9668011B2 (en) 2001-02-05 2017-05-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Single chip set-top box system
US8913667B2 (en) 1999-11-09 2014-12-16 Broadcom Corporation Video decoding system having a programmable variable-length decoder
US7222208B1 (en) * 2000-08-23 2007-05-22 Intel Corporation Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port
US6766464B2 (en) * 2001-02-13 2004-07-20 Sun Microsystems, Inc. Method and apparatus for deskewing multiple incoming signals
CN1547677B (zh) * 2001-07-03 2012-05-23 布朗大学研究基金会 利用超光栅处理光信号的方法和设备
US6693477B2 (en) * 2001-10-22 2004-02-17 Research In Motion Limited Clock circuit for a microprocessor
US7039839B2 (en) * 2002-12-23 2006-05-02 Intel Corporation Method and apparatus for enhanced parallel port JTAG interface
EP1445705A1 (de) * 2003-02-04 2004-08-11 Thomson Licensing S.A. Signalverarbeitungssystem
US6928027B2 (en) * 2003-04-11 2005-08-09 Qualcomm Inc Virtual dual-port synchronous RAM architecture
US7667710B2 (en) * 2003-04-25 2010-02-23 Broadcom Corporation Graphics display system with line buffer control scheme
DE10334838B4 (de) 2003-07-30 2005-06-16 Infineon Technologies Ag Sende-/Empfangsanordnung und Verfahren zum bidirektionalen Übertragen von Daten über eine digitale Schnittstelle in einem Funkgerät
US8063916B2 (en) 2003-10-22 2011-11-22 Broadcom Corporation Graphics layer reduction for video composition
US7711878B2 (en) * 2004-05-21 2010-05-04 Intel Corporation Method and apparatus for acknowledgement-based handshake mechanism for interactively training links
US20050262184A1 (en) * 2004-05-21 2005-11-24 Naveen Cherukuri Method and apparatus for interactively training links in a lockstep fashion
US8183982B2 (en) * 2007-08-14 2012-05-22 Infineon Technologies Ag System including reply signal that at least partially overlaps request
CN101478785B (zh) * 2009-01-21 2010-08-04 华为技术有限公司 资源池管理系统及信号处理方法
US8570790B2 (en) * 2011-01-13 2013-10-29 Cypress Semiconductor Corporation Memory devices and methods for high random transaction rate
US20120300129A1 (en) * 2011-05-24 2012-11-29 Hetke Theodore S System and method for controlling audio/video data streams
EP3343386B1 (de) * 2016-12-30 2020-02-05 GN Audio A/S Vorrichtung mit untereinander kommunizierenden prozessoren
DE102017217432A1 (de) * 2017-09-29 2019-04-04 Siemens Mobility GmbH Konzept zum unidirektionalen Übertragen von Daten

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
US4574345A (en) * 1981-04-01 1986-03-04 Advanced Parallel Systems, Inc. Multiprocessor computer system utilizing a tapped delay line instruction bus
US4439839A (en) * 1981-08-24 1984-03-27 International Telephone And Telegraph Corporation Dynamically programmable processing element
US4550402A (en) * 1983-12-22 1985-10-29 Ford Motor Company Data communication system
US4754394A (en) * 1984-10-24 1988-06-28 International Business Machines Corporation Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage
US4641238A (en) * 1984-12-10 1987-02-03 Itt Corporation Multiprocessor system employing dynamically programmable processing elements controlled by a master processor
US4809217A (en) * 1985-10-31 1989-02-28 Allen-Bradley Company, Inc. Remote I/O port for transfer of I/O data in a programmable controller
US4800524A (en) * 1985-12-20 1989-01-24 Analog Devices, Inc. Modulo address generator
US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
US5099417A (en) * 1987-03-13 1992-03-24 Texas Instruments Incorporated Data processing device with improved direct memory access
US4908748A (en) * 1987-07-28 1990-03-13 Texas Instruments Incorporated Data processing device with parallel circular addressing hardware
GB8808353D0 (en) * 1988-04-09 1988-05-11 Int Computers Ltd Data processing system
US5056000A (en) * 1988-06-21 1991-10-08 International Parallel Machines, Inc. Synchronized parallel processing with shared memory
JPH02132514A (ja) * 1988-07-04 1990-05-22 Canon Inc ドライブインターフェイス
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5117350A (en) * 1988-12-15 1992-05-26 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
US5187795A (en) * 1989-01-27 1993-02-16 Hughes Aircraft Company Pipelined signal processor having a plurality of bidirectional configurable parallel ports that are configurable as individual ports or as coupled pair of ports
DE69022716T2 (de) * 1990-03-19 1996-03-14 Bull Hn Information Syst Mehrrechnersystem mit verteilten gemeinsamen Betriebsmitteln und dynamischer und selektiver Vervielfältigung globaler Daten und Verfahren dafür.
US5280532A (en) * 1990-04-09 1994-01-18 Dsc Communications Corporation N:1 bit compression apparatus and method
US5390304A (en) * 1990-09-28 1995-02-14 Texas Instruments, Incorporated Method and apparatus for processing block instructions in a data processor
USH1291H (en) * 1990-12-20 1994-02-01 Hinton Glenn J Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions
JPH0520263A (ja) * 1991-07-15 1993-01-29 Nec Corp データ転送制御装置
JP3029886B2 (ja) * 1991-07-23 2000-04-10 富士通株式会社 混成多重同期方式
CA2069711C (en) * 1991-09-18 1999-11-30 Donald Edward Carmon Multi-media signal processor computer system
US5361370A (en) * 1991-10-24 1994-11-01 Intel Corporation Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port
US5423010A (en) * 1992-01-24 1995-06-06 C-Cube Microsystems Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words
GB9210414D0 (en) * 1992-05-15 1992-07-01 Texas Instruments Ltd Method and apparatus for interfacing a serial data signal
EP0589499B1 (de) * 1992-08-12 1999-04-07 Koninklijke Philips Electronics N.V. Mehrstationskommunikationsbussystem, sowie eine Master-Station und eine Slave-Station für den Einsatz in einem solchen System
US5471607A (en) * 1993-04-22 1995-11-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
US5537576A (en) * 1993-06-23 1996-07-16 Dsp Semiconductors Ltd. Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space
US5608885A (en) * 1994-03-01 1997-03-04 Intel Corporation Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions
US5619720A (en) * 1994-10-04 1997-04-08 Analog Devices, Inc. Digital signal processor having link ports for point-to-point communication
US5696994A (en) * 1995-05-26 1997-12-09 National Semiconductor Corporation Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes
US5649138A (en) * 1996-01-04 1997-07-15 Advanced Micro Devices Time dependent rerouting of instructions in plurality of reservation stations of a superscalar microprocessor

Also Published As

Publication number Publication date
US6002882A (en) 1999-12-14
WO1999023787A2 (en) 1999-05-14
EP1027786A2 (de) 2000-08-16
DE69806497T2 (de) 2003-03-27
EP1027786B1 (de) 2002-07-10
JP2001522116A (ja) 2001-11-13
JP4267818B2 (ja) 2009-05-27
WO1999023787A3 (en) 1999-07-15

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