DE69807412T2 - Prozessorarchitekturschema und Befehlssatz zur Maximierung verfügbarer Opcodes und zum Einsetzen verschiedener Adressierungsmodi - Google Patents
Prozessorarchitekturschema und Befehlssatz zur Maximierung verfügbarer Opcodes und zum Einsetzen verschiedener AdressierungsmodiInfo
- Publication number
- DE69807412T2 DE69807412T2 DE69807412T DE69807412T DE69807412T2 DE 69807412 T2 DE69807412 T2 DE 69807412T2 DE 69807412 T DE69807412 T DE 69807412T DE 69807412 T DE69807412 T DE 69807412T DE 69807412 T2 DE69807412 T2 DE 69807412T2
- Authority
- DE
- Germany
- Prior art keywords
- addressing modes
- processor architecture
- instruction set
- different addressing
- architecture scheme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/959,942 US5987583A (en) | 1997-10-07 | 1997-10-29 | Processor architecture scheme and instruction set for maximizing available opcodes and address selection modes |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69807412D1 DE69807412D1 (de) | 2002-10-02 |
DE69807412T2 true DE69807412T2 (de) | 2003-04-17 |
Family
ID=25502611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69807412T Expired - Fee Related DE69807412T2 (de) | 1997-10-29 | 1998-10-14 | Prozessorarchitekturschema und Befehlssatz zur Maximierung verfügbarer Opcodes und zum Einsetzen verschiedener Adressierungsmodi |
Country Status (7)
Country | Link |
---|---|
US (1) | US5987583A (de) |
EP (1) | EP0913766B1 (de) |
JP (1) | JPH11212787A (de) |
KR (1) | KR19990037573A (de) |
AT (1) | ATE223082T1 (de) |
DE (1) | DE69807412T2 (de) |
TW (1) | TW408282B (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6098160A (en) * | 1997-10-28 | 2000-08-01 | Microchip Technology Incorporated | Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor |
IL126043A (en) * | 1998-09-02 | 2003-01-12 | D S P Group Ltd | Method and system for setting a new memory address pointer in a dsp |
US6708268B1 (en) * | 1999-03-26 | 2004-03-16 | Microchip Technology Incorporated | Microcontroller instruction set |
JP2003528389A (ja) * | 2000-03-21 | 2003-09-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | アドレスモード拡張手段を有するデータキャリアおよびコマンド拡張手段を有するデータキャリア |
US7437532B1 (en) * | 2003-05-07 | 2008-10-14 | Marvell International Ltd. | Memory mapped register file |
GB2402763B (en) * | 2003-06-13 | 2006-03-01 | Advanced Risc Mach Ltd | Data access program instruction encoding |
KR100897857B1 (ko) | 2003-10-23 | 2009-05-15 | 마이크로칩 테크놀로지 인코포레이티드 | 마이크로컨트롤러 명령어 셋트 |
US20050138330A1 (en) * | 2003-12-23 | 2005-06-23 | Maxim Integrated Products, Inc. | MAXQ microcontroller |
US7996651B2 (en) * | 2007-11-30 | 2011-08-09 | Microchip Technology Incorporated | Enhanced microprocessor or microcontroller |
US8539210B2 (en) | 2007-11-30 | 2013-09-17 | Microchip Technology Incorporated | Context switching with automatic saving of special function registers memory-mapped to all banks |
JP5757320B2 (ja) * | 2013-12-12 | 2015-07-29 | 日本電気株式会社 | データ処理装置、データ処理方法およびデータ処理プログラム |
CN106293627B (zh) * | 2016-07-27 | 2019-01-11 | 珠海市杰理科技股份有限公司 | 寄存器调用及调用指令编码的方法、装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3946366A (en) * | 1973-01-26 | 1976-03-23 | Sanders Associates, Inc. | Addressing technique employing both direct and indirect register addressing |
US4047245A (en) * | 1976-07-12 | 1977-09-06 | Western Electric Company, Incorporated | Indirect memory addressing |
US4240142A (en) * | 1978-12-29 | 1980-12-16 | Bell Telephone Laboratories, Incorporated | Data processing apparatus providing autoincrementing of memory pointer registers |
US5367648A (en) * | 1991-02-20 | 1994-11-22 | International Business Machines Corporation | General purpose memory access scheme using register-indirect mode |
US5717908A (en) * | 1993-02-25 | 1998-02-10 | Intel Corporation | Pattern recognition system using a four address arithmetic logic unit |
US5832533A (en) * | 1995-01-04 | 1998-11-03 | International Business Machines Corporation | Method and system for addressing registers in a data processing unit in an indexed addressing mode |
US5860155A (en) * | 1995-11-16 | 1999-01-12 | Utek Semiconductor Corporation | Instruction decoding mechanism for reducing execution time by earlier detection and replacement of indirect addresses with direct addresses |
-
1997
- 1997-10-29 US US08/959,942 patent/US5987583A/en not_active Expired - Lifetime
-
1998
- 1998-10-14 EP EP98119376A patent/EP0913766B1/de not_active Expired - Lifetime
- 1998-10-14 DE DE69807412T patent/DE69807412T2/de not_active Expired - Fee Related
- 1998-10-14 AT AT98119376T patent/ATE223082T1/de not_active IP Right Cessation
- 1998-10-27 JP JP10306134A patent/JPH11212787A/ja not_active Withdrawn
- 1998-10-29 KR KR1019980046746A patent/KR19990037573A/ko not_active Application Discontinuation
- 1998-11-16 TW TW087117921A patent/TW408282B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0913766B1 (de) | 2002-08-28 |
KR19990037573A (ko) | 1999-05-25 |
US5987583A (en) | 1999-11-16 |
ATE223082T1 (de) | 2002-09-15 |
DE69807412D1 (de) | 2002-10-02 |
JPH11212787A (ja) | 1999-08-06 |
EP0913766A3 (de) | 1999-12-29 |
TW408282B (en) | 2000-10-11 |
EP0913766A2 (de) | 1999-05-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8339 | Ceased/non-payment of the annual fee |