DE69808362D1 - Multiplizierverfahren und Multiplizierschaltung - Google Patents

Multiplizierverfahren und Multiplizierschaltung

Info

Publication number
DE69808362D1
DE69808362D1 DE69808362T DE69808362T DE69808362D1 DE 69808362 D1 DE69808362 D1 DE 69808362D1 DE 69808362 T DE69808362 T DE 69808362T DE 69808362 T DE69808362 T DE 69808362T DE 69808362 D1 DE69808362 D1 DE 69808362D1
Authority
DE
Germany
Prior art keywords
multiplication
circuit
multiplication circuit
multiplication method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69808362T
Other languages
English (en)
Other versions
DE69808362T2 (de
Inventor
Mana Saishi
Shunichi Kurohmaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69808362D1 publication Critical patent/DE69808362D1/de
Publication of DE69808362T2 publication Critical patent/DE69808362T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest
DE69808362T 1997-04-01 1998-03-31 Multiplizierverfahren und Multiplizierschaltung Expired - Lifetime DE69808362T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8255997 1997-04-01

Publications (2)

Publication Number Publication Date
DE69808362D1 true DE69808362D1 (de) 2002-11-07
DE69808362T2 DE69808362T2 (de) 2003-03-06

Family

ID=13777860

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69808362T Expired - Lifetime DE69808362T2 (de) 1997-04-01 1998-03-31 Multiplizierverfahren und Multiplizierschaltung

Country Status (4)

Country Link
US (2) US6167419A (de)
EP (1) EP0869432B1 (de)
KR (1) KR100556568B1 (de)
DE (1) DE69808362T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062526B1 (en) * 2000-02-18 2006-06-13 Texas Instruments Incorporated Microprocessor with rounding multiply instructions
US7890566B1 (en) * 2000-02-18 2011-02-15 Texas Instruments Incorporated Microprocessor with rounding dot product instruction
TW484092B (en) * 2001-01-31 2002-04-21 Nat Science Council Reduced-width low-error multiplier
US7340495B2 (en) * 2001-10-29 2008-03-04 Intel Corporation Superior misaligned memory load and copy using merge hardware
US6941335B2 (en) * 2001-11-29 2005-09-06 International Business Machines Corporation Random carry-in for floating-point operations
US7689641B2 (en) * 2003-06-30 2010-03-30 Intel Corporation SIMD integer multiply high with round and shift
JP4571903B2 (ja) * 2005-12-02 2010-10-27 富士通株式会社 演算処理装置，情報処理装置，及び演算処理方法
US20080034027A1 (en) * 2006-08-01 2008-02-07 Linfeng Guo Method for reducing round-off error in fixed-point arithmetic
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
US9032009B2 (en) 2013-03-11 2015-05-12 Freescale Semicondutor, Inc. Multiplier circuit
US8933731B2 (en) 2013-03-11 2015-01-13 Freescale Semiconductor, Inc. Binary adder and multiplier circuit
US20150095396A1 (en) * 2013-10-01 2015-04-02 Rockwell Automation Technologies, Inc. Multiplying varying fixed-point binary numbers
RU2625528C1 (ru) * 2016-05-17 2017-07-14 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кубанский государственный технологический университет" (ФГБОУ ВО "КубГТУ") Арифметическое устройство
RU2749647C1 (ru) * 2020-11-17 2021-06-16 Федеральное государственное бюджетное учреждение науки Институт космических исследований Российской академии наук Способ умножения чисел в позиционном коде

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61188624A (ja) * 1985-02-15 1986-08-22 Fujitsu Ltd 固定小数点演算装置
JPS6285333A (ja) * 1985-10-11 1987-04-18 Oki Electric Ind Co Ltd 浮動小数点乗算器丸め処理方式
US4876660A (en) * 1987-03-20 1989-10-24 Bipolar Integrated Technology, Inc. Fixed-point multiplier-accumulator architecture
US4841468A (en) * 1987-03-20 1989-06-20 Bipolar Integrated Technology, Inc. High-speed digital multiplier architecture
JPS63298526A (ja) * 1987-05-29 1988-12-06 Yokogawa Medical Syst Ltd 浮動小数点加算装置
JPH01111229A (ja) * 1987-10-26 1989-04-27 Nec Corp 浮動小数点加減算器
US4958312A (en) * 1987-11-09 1990-09-18 Lsi Logic Corporation Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults
US4999801A (en) * 1988-07-15 1991-03-12 Fujitsu Limited Floating point operation unit in division and square root operations
US4926370A (en) * 1989-04-17 1990-05-15 International Business Machines Corporation Method and apparatus for processing postnormalization and rounding in parallel
US4941120A (en) * 1989-04-17 1990-07-10 International Business Machines Corporation Floating point normalization and rounding prediction circuit
US5208770A (en) * 1989-05-30 1993-05-04 Fujitsu Limited Accumulation circuit having a round-off function
US5128889A (en) * 1990-02-22 1992-07-07 Matsushita Electric Industrial Co., Ltd. Floating-point arithmetic apparatus with compensation for mantissa truncation
JPH0473249A (ja) * 1990-07-14 1992-03-09 Oji Paper Co Ltd 不織布の製造方法及び装置
JP3199371B2 (ja) * 1990-07-30 2001-08-20 松下電器産業株式会社 丸め装置
EP0973089B1 (de) * 1990-08-24 2002-07-17 Matsushita Electric Industrial Co., Ltd. Verfahren und Gerät zur Berechnung von Gleitkommadaten
JPH0580978A (ja) * 1991-09-18 1993-04-02 Fujitsu Ltd 演算処理回路
US5521855A (en) * 1991-11-29 1996-05-28 Sony Corporation Multiplying circuit
JPH05224888A (ja) * 1992-02-13 1993-09-03 Fujitsu Ltd 小数点位置可変型データの乗算回路
US5341319A (en) * 1993-02-10 1994-08-23 Digital Equipment Corporation Method and apparatus for controlling a rounding operation in a floating point multiplier circuit
JP3222313B2 (ja) * 1993-04-27 2001-10-29 松下電器産業株式会社 演算装置及び演算方法
JPH06348455A (ja) * 1993-06-14 1994-12-22 Matsushita Electric Ind Co Ltd 乗算における丸め込み方法及び乗算回路
JPH07114454A (ja) * 1993-10-14 1995-05-02 Sony Corp 乗算回路および乗算方法
US6038583A (en) * 1997-10-23 2000-03-14 Advanced Micro Devices, Inc. Method and apparatus for simultaneously multiplying two or more independent pairs of operands and calculating a rounded products

Also Published As

Publication number Publication date
KR100556568B1 (ko) 2006-07-03
US6167419A (en) 2000-12-26
KR19980080981A (ko) 1998-11-25
DE69808362T2 (de) 2003-03-06
EP0869432A1 (de) 1998-10-07
EP0869432B1 (de) 2002-10-02
US6167420A (en) 2000-12-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP