DE69815482D1 - Computer Anordnung mit Prozessor und Speicher-Hierarchie und sein Betriebsverfahren - Google Patents

Computer Anordnung mit Prozessor und Speicher-Hierarchie und sein Betriebsverfahren

Info

Publication number
DE69815482D1
DE69815482D1 DE69815482T DE69815482T DE69815482D1 DE 69815482 D1 DE69815482 D1 DE 69815482D1 DE 69815482 T DE69815482 T DE 69815482T DE 69815482 T DE69815482 T DE 69815482T DE 69815482 D1 DE69815482 D1 DE 69815482D1
Authority
DE
Germany
Prior art keywords
processor
operating method
memory hierarchy
computer arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69815482T
Other languages
English (en)
Other versions
DE69815482T2 (de
Inventor
Steven D Krueger
Jonathan H Shiell
Ian Nmi Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69815482D1 publication Critical patent/DE69815482D1/de
Application granted granted Critical
Publication of DE69815482T2 publication Critical patent/DE69815482T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Image Input (AREA)
DE69815482T 1997-12-24 1998-12-10 Computer Anordnung mit Prozessor und Speicher-Hierarchie und sein Betriebsverfahren Expired - Lifetime DE69815482T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7144697P 1997-12-24 1997-12-24
US71446P 1997-12-24

Publications (2)

Publication Number Publication Date
DE69815482D1 true DE69815482D1 (de) 2003-07-17
DE69815482T2 DE69815482T2 (de) 2004-04-29

Family

ID=22101380

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69815482T Expired - Lifetime DE69815482T2 (de) 1997-12-24 1998-12-10 Computer Anordnung mit Prozessor und Speicher-Hierarchie und sein Betriebsverfahren

Country Status (4)

Country Link
US (1) US6449692B1 (de)
EP (1) EP0926600B1 (de)
JP (1) JPH11288386A (de)
DE (1) DE69815482T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000003381A1 (fr) * 1998-07-09 2000-01-20 Seiko Epson Corporation Circuit d'attaque et dispositif a cristal liquide
US6801207B1 (en) 1998-10-09 2004-10-05 Advanced Micro Devices, Inc. Multimedia processor employing a shared CPU-graphics cache
US6483516B1 (en) * 1998-10-09 2002-11-19 National Semiconductor Corporation Hierarchical texture cache
US7206344B1 (en) * 2000-01-05 2007-04-17 Genesis Microchip Inc. Method and apparatus for displaying video
US6801208B2 (en) * 2000-12-27 2004-10-05 Intel Corporation System and method for cache sharing
EP1769360A4 (de) * 2004-07-14 2008-08-06 Silicon Optix Inc Cache-speicher-verwaltungssystem und -verfahren
US7589738B2 (en) * 2004-07-14 2009-09-15 Integrated Device Technology, Inc. Cache memory management system and method
CN100527099C (zh) 2005-02-15 2009-08-12 皇家飞利浦电子股份有限公司 用于提高数据处理设备的存储单元的性能的装置和方法
US7764289B2 (en) * 2005-04-22 2010-07-27 Apple Inc. Methods and systems for processing objects in memory
US9131004B2 (en) * 2009-04-26 2015-09-08 Jeffrey Alan Carley Method and apparatus for network address resolution
US10599433B2 (en) * 2013-07-15 2020-03-24 Texas Instruments Incorported Cache management operations using streaming engine
US9954533B2 (en) 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
US11398453B2 (en) 2018-01-09 2022-07-26 Samsung Electronics Co., Ltd. HBM silicon photonic TSV architecture for lookup computing AI accelerator
US11625332B2 (en) * 2020-01-14 2023-04-11 Arm Limited Cache miss handling for read operations in data processing systems
US11789867B2 (en) 2020-01-14 2023-10-17 Arm Limited Cache arrangement for data processing systems
US11205243B2 (en) 2020-01-14 2021-12-21 Arm Limited Data processing systems

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
FR2664719A1 (fr) 1990-07-10 1992-01-17 Philips Electronique Lab Dispositif de controle pour une memoire tampon a partitionnement reconfigurable.
JPH0799508B2 (ja) * 1990-10-15 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション キャッシュ記憶機構を動的に区分する方法およびキャッシュ記憶機構システム
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
JPH06110781A (ja) * 1992-09-30 1994-04-22 Nec Corp キャッシュメモリ装置
US5751995A (en) * 1994-01-04 1998-05-12 Intel Corporation Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively
US5544306A (en) * 1994-05-03 1996-08-06 Sun Microsystems, Inc. Flexible dram access in a frame buffer memory and system
US5579473A (en) * 1994-07-18 1996-11-26 Sun Microsystems, Inc. Interface controller for frame buffer random access memory devices
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US6038645A (en) * 1996-08-28 2000-03-14 Texas Instruments Incorporated Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache

Also Published As

Publication number Publication date
US6449692B1 (en) 2002-09-10
JPH11288386A (ja) 1999-10-19
DE69815482T2 (de) 2004-04-29
EP0926600B1 (de) 2003-06-11
EP0926600A1 (de) 1999-06-30

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Legal Events

Date Code Title Description
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