DE69817170D1 - Emulation von unterbrechungsmechanismus in einem multiprozessorsystem - Google Patents

Emulation von unterbrechungsmechanismus in einem multiprozessorsystem

Info

Publication number
DE69817170D1
DE69817170D1 DE69817170T DE69817170T DE69817170D1 DE 69817170 D1 DE69817170 D1 DE 69817170D1 DE 69817170 T DE69817170 T DE 69817170T DE 69817170 T DE69817170 T DE 69817170T DE 69817170 D1 DE69817170 D1 DE 69817170D1
Authority
DE
Germany
Prior art keywords
emulation
multiprocessor system
interruption mechanism
interruption
multiprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69817170T
Other languages
English (en)
Other versions
DE69817170T2 (de
Inventor
Muthurajan Jayakumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69817170D1 publication Critical patent/DE69817170D1/de
Publication of DE69817170T2 publication Critical patent/DE69817170T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45554—Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS
DE69817170T 1997-04-18 1998-04-16 Emulation von unterbrechungsmechanismus in einem multiprozessorsystem Expired - Fee Related DE69817170T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/843,996 US5889978A (en) 1997-04-18 1997-04-18 Emulation of interrupt control mechanism in a multiprocessor system
US843996 1997-04-18
PCT/US1998/007708 WO1998048346A2 (en) 1997-04-18 1998-04-16 Emulation of interrupt control mechanism in a multiprocessor system

Publications (2)

Publication Number Publication Date
DE69817170D1 true DE69817170D1 (de) 2003-09-18
DE69817170T2 DE69817170T2 (de) 2004-06-17

Family

ID=25291513

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69817170T Expired - Fee Related DE69817170T2 (de) 1997-04-18 1998-04-16 Emulation von unterbrechungsmechanismus in einem multiprozessorsystem

Country Status (6)

Country Link
US (1) US5889978A (de)
EP (1) EP0976036B1 (de)
AU (1) AU7249598A (de)
DE (1) DE69817170T2 (de)
HK (1) HK1025642A1 (de)
WO (1) WO1998048346A2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093213A (en) * 1995-10-06 2000-07-25 Advanced Micro Devices, Inc. Flexible implementation of a system management mode (SMM) in a processor
US6571206B1 (en) * 1998-01-15 2003-05-27 Phoenix Technologies Ltd. Apparatus and method for emulating an I/O instruction for the correct processor and for servicing software SMI's in a multi-processor environment
US6173248B1 (en) * 1998-02-09 2001-01-09 Hewlett-Packard Company Method and apparatus for handling masked exceptions in an instruction interpreter
US6167479A (en) * 1998-08-03 2000-12-26 Unisys Corporation System and method for testing interrupt processing logic within an instruction processor
US6694457B2 (en) * 2001-03-06 2004-02-17 Hewlett-Packard Development Company, L.P. System and method for monitoring execution of privileged instructions
US7187209B2 (en) * 2003-08-13 2007-03-06 Via Technologies, Inc. Non-inverting domino register
US20040162888A1 (en) * 2003-02-17 2004-08-19 Reasor Jason W. Remote access to a firmware developer user interface
US20040162978A1 (en) * 2003-02-17 2004-08-19 Reasor Jason W. Firmware developer user interface
US7386712B2 (en) * 2003-02-17 2008-06-10 Hewlett-Packard Development Company, L.P. Firmware developer user interface with break command polling
US7222064B1 (en) * 2003-10-10 2007-05-22 Unisys Corporation Instruction processor emulation having inter-processor messaging accounting
US20050102457A1 (en) * 2003-11-12 2005-05-12 Dell Products L.P. System and method for interrupt processing in a multiple processor system
US7721024B2 (en) * 2003-11-12 2010-05-18 Dell Products L.P. System and method for exiting from an interrupt mode in a multiple processor system
US20050132022A1 (en) * 2003-12-12 2005-06-16 International Business Machines Corporation Computer system with LAN-based I/O
US7260752B2 (en) 2004-02-19 2007-08-21 International Business Machines Corporation Method and apparatus for responding to critical abstracted platform events in a data processing system
JP4265440B2 (ja) * 2004-02-24 2009-05-20 株式会社デンソー マイクロコンピュータ及びエミュレーション装置
US8853746B2 (en) * 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US7594144B2 (en) 2006-08-14 2009-09-22 International Business Machines Corporation Handling fatal computer hardware errors
US7734873B2 (en) * 2007-05-29 2010-06-08 Advanced Micro Devices, Inc. Caching of microcode emulation memory
US7996595B2 (en) * 2009-04-14 2011-08-09 Lstar Technologies Llc Interrupt arbitration for multiprocessors
US8260996B2 (en) * 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors
US8321614B2 (en) * 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
US8234431B2 (en) * 2009-10-13 2012-07-31 Empire Technology Development Llc Interrupt masking for multi-core processors
CN103425541A (zh) * 2012-05-25 2013-12-04 鸿富锦精密工业（深圳）有限公司 异常处理机制检测电子装置、系统及方法
US10884751B2 (en) 2018-07-13 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for virtualizing the micro-op cache

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763242A (en) * 1985-10-23 1988-08-09 Hewlett-Packard Company Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility
US5327567A (en) * 1989-11-16 1994-07-05 Texas Instruments Incorporated Method and system for returning emulated results from a trap handler
US5517626A (en) * 1990-05-07 1996-05-14 S3, Incorporated Open high speed bus for microcomputer system
US5410709A (en) * 1992-12-17 1995-04-25 Bull Hn Information System Inc. Mechanism for rerouting and dispatching interrupts in a hybrid system environment
US5440747A (en) * 1993-09-27 1995-08-08 Hitachi America, Ltd. Data processor with control logic for storing operation mode status and associated method
JPH07334372A (ja) * 1993-12-24 1995-12-22 Seiko Epson Corp エミュレートシステム及びエミュレート方法
US5487146A (en) * 1994-03-08 1996-01-23 Texas Instruments Incorporated Plural memory access address generation employing guide table entries forming linked list

Also Published As

Publication number Publication date
EP0976036A4 (de) 2001-11-14
EP0976036A2 (de) 2000-02-02
HK1025642A1 (en) 2000-11-17
WO1998048346A2 (en) 1998-10-29
AU7249598A (en) 1998-11-13
WO1998048346A3 (en) 1999-02-18
US5889978A (en) 1999-03-30
EP0976036B1 (de) 2003-08-13
DE69817170T2 (de) 2004-06-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806

8339 Ceased/non-payment of the annual fee