DE69829738D1 - Verfahren zur Entfernung einer porösen Halbleiterzone und Verfahren zur Herstellung eines halbleitenden Substrats - Google Patents
Verfahren zur Entfernung einer porösen Halbleiterzone und Verfahren zur Herstellung eines halbleitenden SubstratsInfo
- Publication number
- DE69829738D1 DE69829738D1 DE69829738T DE69829738T DE69829738D1 DE 69829738 D1 DE69829738 D1 DE 69829738D1 DE 69829738 T DE69829738 T DE 69829738T DE 69829738 T DE69829738 T DE 69829738T DE 69829738 D1 DE69829738 D1 DE 69829738D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- porous semiconductor
- semiconductor zone
- semiconductive substrate
- ultrasonic wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000011148 porous material Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 229910021426 porous silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP339798 | 1998-01-09 | ||
JP00339798A JP3847935B2 (ja) | 1998-01-09 | 1998-01-09 | 多孔質領域の除去方法及び半導体基体の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69829738D1 true DE69829738D1 (de) | 2005-05-19 |
DE69829738T2 DE69829738T2 (de) | 2006-02-09 |
Family
ID=11556241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69829738T Expired - Lifetime DE69829738T2 (de) | 1998-01-09 | 1998-12-18 | Verfahren zur Entfernung einer porösen Halbleiterzone und Verfahren zur Herstellung eines halbleitenden Substrats |
Country Status (9)
Country | Link |
---|---|
US (1) | US6127281A (de) |
EP (1) | EP0938132B1 (de) |
JP (1) | JP3847935B2 (de) |
KR (1) | KR100354918B1 (de) |
AT (1) | ATE293284T1 (de) |
AU (1) | AU745396B2 (de) |
DE (1) | DE69829738T2 (de) |
SG (1) | SG75147A1 (de) |
TW (1) | TW440950B (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7148119B1 (en) * | 1994-03-10 | 2006-12-12 | Canon Kabushiki Kaisha | Process for production of semiconductor substrate |
JPH10223585A (ja) | 1997-02-04 | 1998-08-21 | Canon Inc | ウェハ処理装置及びその方法並びにsoiウェハの製造方法 |
US6391067B2 (en) | 1997-02-04 | 2002-05-21 | Canon Kabushiki Kaisha | Wafer processing apparatus and method, wafer convey robot, semiconductor substrate fabrication method, and semiconductor fabrication apparatus |
US6767840B1 (en) * | 1997-02-21 | 2004-07-27 | Canon Kabushiki Kaisha | Wafer processing apparatus, wafer processing method, and semiconductor substrate fabrication method |
JP3218564B2 (ja) | 1998-01-14 | 2001-10-15 | キヤノン株式会社 | 多孔質領域の除去方法及び半導体基体の製造方法 |
ATE251340T1 (de) * | 1999-04-27 | 2003-10-15 | Decker Gmbh & Co Kg Geb | Behandlungsvorrichtung für silizium-scheiben |
JP3810968B2 (ja) * | 1999-12-03 | 2006-08-16 | 東京エレクトロン株式会社 | 液処理装置および液処理方法 |
JP2004228150A (ja) * | 2003-01-20 | 2004-08-12 | Canon Inc | エッチング方法 |
US7040330B2 (en) * | 2003-02-20 | 2006-05-09 | Lam Research Corporation | Method and apparatus for megasonic cleaning of patterned substrates |
TWI227932B (en) * | 2003-06-23 | 2005-02-11 | Promos Technologies Inc | Method for forming a bottle-shaped trench |
US20050132332A1 (en) * | 2003-12-12 | 2005-06-16 | Abhay Sathe | Multi-location coordinated test apparatus |
US20050181572A1 (en) * | 2004-02-13 | 2005-08-18 | Verhoeven Tracy B. | Method for acoustically isolating an acoustic resonator from a substrate |
JP2005327856A (ja) * | 2004-05-13 | 2005-11-24 | Komatsu Electronic Metals Co Ltd | 半導体ウェーハのエッチング装置 |
JP4955264B2 (ja) | 2005-03-11 | 2012-06-20 | エルピーダメモリ株式会社 | 多孔質単結晶層を備えた半導体チップおよびその製造方法 |
US8327861B2 (en) * | 2006-12-19 | 2012-12-11 | Lam Research Corporation | Megasonic precision cleaning of semiconductor process equipment components and parts |
DE102008003453A1 (de) * | 2008-01-08 | 2009-07-09 | Robert Bosch Gmbh | Verfahren zur Herstellung poröser Mikrostrukturen, nach diesem Verfahren hergestellte poröse Mikrostrukturen sowie deren Verwendung |
CN102125921B (zh) * | 2010-01-20 | 2012-09-05 | 常州瑞择微电子科技有限公司 | 一种光掩模在清洗过程中的传输方法 |
JP7276036B2 (ja) * | 2019-09-19 | 2023-05-18 | 大日本印刷株式会社 | エッチング装置およびエッチング方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05217824A (ja) * | 1992-01-31 | 1993-08-27 | Canon Inc | 半導体ウエハ及びその製造方法 |
US5593505A (en) * | 1995-04-19 | 1997-01-14 | Memc Electronic Materials, Inc. | Method for cleaning semiconductor wafers with sonic energy and passing through a gas-liquid-interface |
US6103598A (en) * | 1995-07-13 | 2000-08-15 | Canon Kabushiki Kaisha | Process for producing semiconductor substrate |
CN1132223C (zh) * | 1995-10-06 | 2003-12-24 | 佳能株式会社 | 半导体衬底及其制造方法 |
JPH09331049A (ja) * | 1996-04-08 | 1997-12-22 | Canon Inc | 貼り合わせsoi基板の作製方法及びsoi基板 |
-
1998
- 1998-01-09 JP JP00339798A patent/JP3847935B2/ja not_active Expired - Fee Related
- 1998-12-15 US US09/211,559 patent/US6127281A/en not_active Expired - Fee Related
- 1998-12-15 SG SG1998005829A patent/SG75147A1/en unknown
- 1998-12-16 TW TW087120966A patent/TW440950B/zh not_active IP Right Cessation
- 1998-12-18 AT AT98310437T patent/ATE293284T1/de not_active IP Right Cessation
- 1998-12-18 DE DE69829738T patent/DE69829738T2/de not_active Expired - Lifetime
- 1998-12-18 EP EP98310437A patent/EP0938132B1/de not_active Expired - Lifetime
- 1998-12-24 AU AU98188/98A patent/AU745396B2/en not_active Ceased
- 1998-12-26 KR KR1019980058992A patent/KR100354918B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
ATE293284T1 (de) | 2005-04-15 |
US6127281A (en) | 2000-10-03 |
EP0938132A2 (de) | 1999-08-25 |
JPH11204494A (ja) | 1999-07-30 |
TW440950B (en) | 2001-06-16 |
EP0938132A3 (de) | 1999-12-22 |
SG75147A1 (en) | 2000-09-19 |
KR19990066873A (ko) | 1999-08-16 |
EP0938132B1 (de) | 2005-04-13 |
AU745396B2 (en) | 2002-03-21 |
KR100354918B1 (ko) | 2002-11-18 |
AU9818898A (en) | 1999-07-29 |
JP3847935B2 (ja) | 2006-11-22 |
DE69829738T2 (de) | 2006-02-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |