DE69830772D1 - Integrierte Halbleiterschaltungsanordnung - Google Patents

Integrierte Halbleiterschaltungsanordnung

Info

Publication number
DE69830772D1
DE69830772D1 DE69830772T DE69830772T DE69830772D1 DE 69830772 D1 DE69830772 D1 DE 69830772D1 DE 69830772 T DE69830772 T DE 69830772T DE 69830772 T DE69830772 T DE 69830772T DE 69830772 D1 DE69830772 D1 DE 69830772D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69830772T
Other languages
English (en)
Inventor
Taketo Maesako
Kouki Yamamoto
Yoshinori Matsui
Kenichi Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Electronics Corp
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp, NEC Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69830772D1 publication Critical patent/DE69830772D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
DE69830772T 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsanordnung Expired - Lifetime DE69830772D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29023497A JP3161384B2 (ja) 1997-09-16 1997-09-16 半導体記憶装置とそのアクセス方法

Publications (1)

Publication Number Publication Date
DE69830772D1 true DE69830772D1 (de) 2005-08-11

Family

ID=17753499

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69830772T Expired - Lifetime DE69830772D1 (de) 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsanordnung

Country Status (7)

Country Link
US (2) US6377501B2 (de)
EP (1) EP0908887B1 (de)
JP (1) JP3161384B2 (de)
KR (1) KR100366839B1 (de)
CN (1) CN1273991C (de)
DE (1) DE69830772D1 (de)
TW (1) TW397991B (de)

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JP3092557B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体記憶装置
JP3178423B2 (ja) 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルｓｄｒａｍ
JP3358612B2 (ja) * 1999-03-15 2002-12-24 日本電気株式会社 半導体集積回路
US6530045B1 (en) * 1999-12-03 2003-03-04 Micron Technology, Inc. Apparatus and method for testing rambus DRAMs
KR100353563B1 (ko) * 1999-12-24 2002-09-26 주식회사 하이닉스반도체 반도체 메모리의 기록 제어회로
US6728798B1 (en) 2000-07-28 2004-04-27 Micron Technology, Inc. Synchronous flash memory with status burst output
KR20020014563A (ko) * 2000-08-18 2002-02-25 윤종용 반도체 메모리 장치
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
US20020147884A1 (en) * 2001-04-05 2002-10-10 Michael Peters Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
JP3931593B2 (ja) * 2001-07-02 2007-06-20 ヤマハ株式会社 データ書込回路
US6452865B1 (en) * 2001-08-09 2002-09-17 International Business Machines Corporation Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus width
US6493285B1 (en) * 2001-08-09 2002-12-10 International Business Machines Corporation Method and apparatus for sampling double data rate memory read data
GB0123416D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Non-volatile memory control
US6940748B2 (en) * 2002-05-16 2005-09-06 Micron Technology, Inc. Stacked 1T-nMTJ MRAM structure
AU2003243244A1 (en) * 2002-05-16 2003-12-02 Micron Technology, Inc. STACKED 1T-nMEMORY CELL STRUCTURE
US7042749B2 (en) * 2002-05-16 2006-05-09 Micron Technology, Inc. Stacked 1T-nmemory cell structure
JP3913108B2 (ja) * 2002-05-22 2007-05-09 松下電器産業株式会社 半導体集積回路装置の製造方法
JP4160790B2 (ja) 2002-06-28 2008-10-08 株式会社ルネサステクノロジ 半導体装置
KR100484254B1 (ko) * 2002-10-31 2005-04-22 주식회사 하이닉스반도체 반도체 메모리 장치의 리던던시 회로 및 그를 이용한 페일구제방법
JP4439838B2 (ja) 2003-05-26 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
US6977860B1 (en) * 2004-05-22 2005-12-20 Virtual Silicon Technology, Inc. SRAM power reduction
EP1781372A1 (de) * 2004-07-20 2007-05-09 Medtronic, Inc. Therapie-programmierführung auf basis von gespeicherter programmierhistorie
WO2008032987A1 (en) * 2006-09-12 2008-03-20 Mtek Vision Co., Ltd. Dual port memory device, memory device and method of operating the dual port memory device
US7936201B2 (en) * 2006-12-22 2011-05-03 Qimonda Ag Apparatus and method for providing a signal for transmission via a signal line
JP5731730B2 (ja) * 2008-01-11 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びその半導体記憶装置を含むデータ処理システム
JP2011023084A (ja) * 2009-07-17 2011-02-03 Toshiba Corp 半導体記憶装置
US8102690B2 (en) * 2009-10-12 2012-01-24 Nanya Technology Corp. Bank re-assignment in chip to reduce IR drop
US9202532B2 (en) * 2012-09-13 2015-12-01 Winbond Electronics Corp. Burst sequence control and multi-valued fuse scheme in memory device
US9449720B1 (en) * 2015-11-17 2016-09-20 Macronix International Co., Ltd. Dynamic redundancy repair
JP6370953B1 (ja) * 2017-03-23 2018-08-08 ファナック株式会社 マルチランクｓｄｒａｍ制御方法及びｓｄｒａｍコントローラ
DE112018006449T5 (de) 2017-12-19 2020-09-03 Panasonic Intellectual Property Management Co., Ltd. Diamantbeschichtete verbundwerkstoff-kühlkörper für hochleistungs-lasersysteme
US11226909B2 (en) 2018-08-24 2022-01-18 Rambus Inc. DRAM interface mode with interruptible internal transfer operation
US11360704B2 (en) * 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
CN112579002B (zh) * 2020-12-14 2024-02-13 北京北大众志微系统科技有限责任公司 一种在位线结构中设置有传输门的sram及存取提升方法
US11380372B1 (en) * 2020-12-17 2022-07-05 Micron Technology, Inc. Transferring data between DRAM and SRAM

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KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
JPS5720983A (en) 1980-07-15 1982-02-03 Hitachi Ltd Memory chip
JPH069114B2 (ja) 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS6238590A (ja) 1985-08-13 1987-02-19 Fujitsu Ltd 半導体記憶装置
US5293598A (en) * 1986-07-30 1994-03-08 Mitsubishi Denki Kabushiki Kaisha Random access memory with a plurality of amplifier groups
US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
JPH01146187A (ja) 1987-12-02 1989-06-08 Mitsubishi Electric Corp キヤッシュメモリ内蔵半導体記憶装置
JPH05258081A (ja) * 1990-11-16 1993-10-08 Seiko Epson Corp シングルチップ・マイクロコンピュータ及びそれを内蔵した電子機器
EP0492776B1 (de) * 1990-12-25 1998-05-13 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher
JP3268785B2 (ja) 1990-12-25 2002-03-25 三菱電機株式会社 半導体記憶装置
JP3238717B2 (ja) 1991-04-16 2001-12-17 三菱電機株式会社 半導体記憶装置におけるデータ転送装置
JP3240161B2 (ja) 1991-04-18 2001-12-17 三菱電機エンジニアリング株式会社 半導体記憶装置
JPH05210974A (ja) 1991-10-03 1993-08-20 Smc Standard Microsyst Corp 同一チップ上でのスタティックキャッシュメモリとダイナミックメインメモリとの結合システム
JP3304413B2 (ja) * 1992-09-17 2002-07-22 三菱電機株式会社 半導体記憶装置
JP3426693B2 (ja) * 1994-03-07 2003-07-14 株式会社日立製作所 半導体記憶装置
CN1146249A (zh) * 1994-04-13 1997-03-26 艾利森公司 大存储器的高效寻址
US6006310A (en) * 1995-09-20 1999-12-21 Micron Electronics, Inc. Single memory device that functions as a multi-way set associative cache memory
JP2940457B2 (ja) * 1996-01-23 1999-08-25 日本電気株式会社 半導体メモリ
JPH10208468A (ja) 1997-01-28 1998-08-07 Hitachi Ltd 半導体記憶装置並びに同期型半導体記憶装置
JPH10340578A (ja) 1997-06-04 1998-12-22 Fujitsu Ltd シンクロナスｄｒａｍ

Also Published As

Publication number Publication date
TW397991B (en) 2000-07-11
JP3161384B2 (ja) 2001-04-25
CN1212430A (zh) 1999-03-31
EP0908887A3 (de) 1999-04-28
EP0908887A2 (de) 1999-04-14
EP0908887B1 (de) 2005-07-06
US6377501B2 (en) 2002-04-23
US6735144B2 (en) 2004-05-11
CN1273991C (zh) 2006-09-06
JPH1186532A (ja) 1999-03-30
US20020136081A1 (en) 2002-09-26
US20020003741A1 (en) 2002-01-10
KR19990029788A (ko) 1999-04-26
KR100366839B1 (ko) 2003-02-19

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