DE69831467D1 - Mehrschicht-Schaltungsplatte - Google Patents

Mehrschicht-Schaltungsplatte

Info

Publication number
DE69831467D1
DE69831467D1 DE69831467T DE69831467T DE69831467D1 DE 69831467 D1 DE69831467 D1 DE 69831467D1 DE 69831467 T DE69831467 T DE 69831467T DE 69831467 T DE69831467 T DE 69831467T DE 69831467 D1 DE69831467 D1 DE 69831467D1
Authority
DE
Germany
Prior art keywords
circuit board
layer circuit
layer
board
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69831467T
Other languages
English (en)
Other versions
DE69831467T2 (de
Inventor
Michio Horiuchi
Yukiharu Takeuchi
Chiaki Takubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Application granted granted Critical
Publication of DE69831467D1 publication Critical patent/DE69831467D1/de
Publication of DE69831467T2 publication Critical patent/DE69831467T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
DE69831467T 1997-11-19 1998-11-18 Mehrschicht-Schaltungsplatte Expired - Fee Related DE69831467T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31831397A JP3466443B2 (ja) 1997-11-19 1997-11-19 多層回路基板
JP31831397 1997-11-19

Publications (2)

Publication Number Publication Date
DE69831467D1 true DE69831467D1 (de) 2005-10-13
DE69831467T2 DE69831467T2 (de) 2006-02-23

Family

ID=18097812

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831467T Expired - Fee Related DE69831467T2 (de) 1997-11-19 1998-11-18 Mehrschicht-Schaltungsplatte

Country Status (5)

Country Link
US (1) US6271478B1 (de)
EP (1) EP0921567B1 (de)
JP (1) JP3466443B2 (de)
KR (1) KR19990045494A (de)
DE (1) DE69831467T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000174153A (ja) 1998-12-01 2000-06-23 Shinko Electric Ind Co Ltd 多層配線基板
US6489574B1 (en) * 1999-11-02 2002-12-03 Canon Kabushiki Kaisha Printed-wiring board
US6538213B1 (en) * 2000-02-18 2003-03-25 International Business Machines Corporation High density design for organic chip carriers
JP3407025B2 (ja) * 2000-06-08 2003-05-19 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6459039B1 (en) * 2000-06-19 2002-10-01 International Business Machines Corporation Method and apparatus to manufacture an electronic package with direct wiring pattern
US7069646B2 (en) * 2000-06-19 2006-07-04 Nortel Networks Limited Techniques for reducing the number of layers in a multilayer signal routing device
US20040212103A1 (en) * 2000-06-19 2004-10-28 Herman Kwong Techniques for pin arrangements in circuit chips
US7281326B1 (en) 2000-06-19 2007-10-16 Nortel Network Limited Technique for routing conductive traces between a plurality of electronic components of a multilayer signal routing device
US6388890B1 (en) * 2000-06-19 2002-05-14 Nortel Networks Limited Technique for reducing the number of layers in a multilayer circuit board
US7725860B1 (en) 2000-06-19 2010-05-25 Herman Kwong Contact mapping using channel routing
US7259336B2 (en) 2000-06-19 2007-08-21 Nortel Networks Limited Technique for improving power and ground flooding
US7107673B2 (en) * 2000-06-19 2006-09-19 Nortel Networks Limited Technique for accommodating electronic components on a multiplayer signal routing device
US6762366B1 (en) * 2001-04-27 2004-07-13 Lsi Logic Corporation Ball assignment for ball grid array package
US6384341B1 (en) * 2001-04-30 2002-05-07 Tyco Electronics Corporation Differential connector footprint for a multi-layer circuit board
US6664483B2 (en) 2001-05-15 2003-12-16 Intel Corporation Electronic package with high density interconnect and associated methods
US7061116B2 (en) * 2001-09-26 2006-06-13 Intel Corporation Arrangement of vias in a substrate to support a ball grid array
US20030102159A1 (en) * 2001-12-04 2003-06-05 Loo Mike C. Optimum power and ground bump pad and bump patterns for flip chip packaging
WO2003063242A1 (en) * 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6814463B2 (en) 2002-02-14 2004-11-09 Tektite Industries, Inc. LED flashlight and printed circuit board therefor
US7227254B2 (en) * 2002-04-02 2007-06-05 Agilent Technologies, Inc. Integrated circuit package
JP4559163B2 (ja) * 2004-08-31 2010-10-06 ルネサスエレクトロニクス株式会社 半導体装置用パッケージ基板およびその製造方法と半導体装置
DE102004047753B4 (de) 2004-09-30 2009-01-02 Advanced Micro Devices, Inc., Sunnyvale Verbesserte Chip-Kontaktierungsanordnung für Chip-Träger für Flip-Chip-Anwendungen
JP4860994B2 (ja) * 2005-12-06 2012-01-25 ルネサスエレクトロニクス株式会社 半導体装置
US7838778B1 (en) 2006-04-26 2010-11-23 Marvell Israel (M.I.S.L.) Ltd. Circuit board layout
US8053349B2 (en) * 2007-11-01 2011-11-08 Texas Instruments Incorporated BGA package with traces for plating pads under the chip
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
CN102097333B (zh) * 2010-11-01 2012-10-17 华为终端有限公司 电路板设计方法、电路板及电子设备
US9466578B2 (en) * 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
CN105513498B (zh) * 2016-02-04 2018-12-25 京东方科技集团股份有限公司 一种覆晶薄膜及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4202007A (en) * 1978-06-23 1980-05-06 International Business Machines Corporation Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers
US4782193A (en) * 1987-09-25 1988-11-01 Ibm Corp. Polygonal wiring for improved package performance
US4887148A (en) * 1988-07-15 1989-12-12 Advanced Micro Devices, Inc. Pin grid array package structure
US5467252A (en) * 1993-10-18 1995-11-14 Motorola, Inc. Method for plating using nested plating buses and semiconductor device having the same
US5650660A (en) * 1995-12-20 1997-07-22 Intel Corp Circuit pattern for a ball grid array integrated circuit package
JP3050807B2 (ja) * 1996-06-19 2000-06-12 イビデン株式会社 多層プリント配線板
US5812379A (en) * 1996-08-13 1998-09-22 Intel Corporation Small diameter ball grid array pad size for improved motherboard routing
JP2000100851A (ja) * 1998-09-25 2000-04-07 Sony Corp 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法

Also Published As

Publication number Publication date
KR19990045494A (ko) 1999-06-25
EP0921567A3 (de) 2000-05-10
DE69831467T2 (de) 2006-02-23
JP3466443B2 (ja) 2003-11-10
EP0921567B1 (de) 2005-09-07
EP0921567A2 (de) 1999-06-09
JPH11150158A (ja) 1999-06-02
US6271478B1 (en) 2001-08-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee