DE69831652D1 - Serielle Busbeschleunigungsschaltung - Google Patents

Serielle Busbeschleunigungsschaltung

Info

Publication number
DE69831652D1
DE69831652D1 DE69831652T DE69831652T DE69831652D1 DE 69831652 D1 DE69831652 D1 DE 69831652D1 DE 69831652 T DE69831652 T DE 69831652T DE 69831652 T DE69831652 T DE 69831652T DE 69831652 D1 DE69831652 D1 DE 69831652D1
Authority
DE
Germany
Prior art keywords
serial bus
acceleration circuit
bus acceleration
circuit
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69831652T
Other languages
English (en)
Other versions
DE69831652T2 (de
Inventor
Naoyuki Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69831652D1 publication Critical patent/DE69831652D1/de
Publication of DE69831652T2 publication Critical patent/DE69831652T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
DE69831652T 1998-03-02 1998-10-05 Serielle Busbeschleunigungsschaltung Expired - Fee Related DE69831652T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4971998 1998-03-02
JP04971998A JP3964528B2 (ja) 1998-03-02 1998-03-02 シリアルバス高速化回路

Publications (2)

Publication Number Publication Date
DE69831652D1 true DE69831652D1 (de) 2005-10-27
DE69831652T2 DE69831652T2 (de) 2006-03-16

Family

ID=12839007

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831652T Expired - Fee Related DE69831652T2 (de) 1998-03-02 1998-10-05 Serielle Busbeschleunigungsschaltung

Country Status (5)

Country Link
US (1) US6140850A (de)
EP (2) EP1594067A1 (de)
JP (1) JP3964528B2 (de)
CN (1) CN1107914C (de)
DE (1) DE69831652T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6675244B1 (en) * 1999-02-19 2004-01-06 Hewlett-Packard Development Company, L.P. SCSI data rate speed determination
FR2819071A1 (fr) 2000-12-28 2002-07-05 Koninkl Philips Electronics Nv Transfert d'une serie de donnees
US6680631B2 (en) * 2001-03-27 2004-01-20 Intel Corporation Setting the speed of clocked circuitry
US6910089B2 (en) * 2001-06-01 2005-06-21 Hewlett-Packard Development Company, L.P. Fault tolerant bus for highly available storage enclosure
EP1283626A1 (de) * 2001-08-09 2003-02-12 Hewlett-Packard Company (a Delaware corporation) Verbessertes Synchron-Datenübertragungssystem
KR100785286B1 (ko) * 2001-08-09 2007-12-12 삼성전자주식회사 동기식전송시스템의 인터페이스용 변환회로
JP4012032B2 (ja) * 2001-11-20 2007-11-21 キヤノン株式会社 データ通信装置
US7400276B1 (en) * 2002-01-28 2008-07-15 Massachusetts Institute Of Technology Method and apparatus for reducing delay in a bus provided from parallel, capacitively coupled transmission lines
CN1301458C (zh) * 2002-12-12 2007-02-21 华邦电子股份有限公司 单线串列传输协定方法与电路
CN1661576B (zh) * 2004-02-25 2010-04-28 中国科学院计算技术研究所 Soc架构下的高速总线动态变频装置和处理器核接口
US7725759B2 (en) 2005-06-29 2010-05-25 Sigmatel, Inc. System and method of managing clock speed in an electronic device
US20070101168A1 (en) * 2005-10-31 2007-05-03 Lee Atkinson Method and system of controlling data transfer speed and power consumption of a bus
US7805558B2 (en) * 2005-10-31 2010-09-28 Hewlett-Packard Development Company, L.P. Method and system of controlling transfer speed of bus transactions
JP2007312300A (ja) * 2006-05-22 2007-11-29 Matsushita Electric Ind Co Ltd データ転送システム及びデータ処理装置
US7536490B2 (en) * 2006-07-20 2009-05-19 Via Technologies, Inc. Method for link bandwidth management
WO2009044438A1 (ja) * 2007-10-01 2009-04-09 Fujitsu Microelectronics Limited 半導体装置
JP2012034375A (ja) * 2011-08-22 2012-02-16 Hitachi Automotive Systems Ltd データ通信装置及びそれを用いたコントローラ
JP5742693B2 (ja) * 2011-12-05 2015-07-01 株式会社デンソー 通信装置及びクロック同期式通信システム
WO2013125557A1 (ja) * 2012-02-21 2013-08-29 株式会社ニコン 通信装置、レンズ鏡筒、及び撮像装置
US8971321B2 (en) * 2012-12-11 2015-03-03 Futurewei Technologies, Inc. System and method for accelerating and decelerating packets
CN106201955B (zh) * 2015-04-29 2021-05-11 罗伯特·博世有限公司 一种总线装置
JP6673021B2 (ja) * 2016-05-31 2020-03-25 富士通株式会社 メモリおよび情報処理装置
CN107704701A (zh) * 2017-10-19 2018-02-16 郑州云海信息技术有限公司 一种针对低速信号中不同上拉电阻的分析方法与系统
CN113612955A (zh) * 2021-08-09 2021-11-05 北京数码视讯技术有限公司 多接口转换装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6381556A (ja) * 1986-09-26 1988-04-12 Hitachi Ltd 可変クロツクバスシステム
US5559502A (en) * 1993-01-14 1996-09-24 Schutte; Herman Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses
JP3302073B2 (ja) * 1993-01-21 2002-07-15 富士通株式会社 データ識別回路及びこれを用いた並列データ受信器
EP0614283B1 (de) * 1993-03-01 1997-10-29 Nippon Telegraph And Telephone Corporation Phasenregelkreis mit Abtast- und Halteschaltung

Also Published As

Publication number Publication date
JP3964528B2 (ja) 2007-08-22
EP1594067A1 (de) 2005-11-09
JPH11250006A (ja) 1999-09-17
CN1107914C (zh) 2003-05-07
CN1227933A (zh) 1999-09-08
US6140850A (en) 2000-10-31
EP0940758B1 (de) 2005-09-21
EP0940758A2 (de) 1999-09-08
EP0940758A3 (de) 2002-07-10
DE69831652T2 (de) 2006-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee