DE69831900D1 - Programmier-Modus- Auswahl mit JTAG Schaltungen - Google Patents

Programmier-Modus- Auswahl mit JTAG Schaltungen

Info

Publication number
DE69831900D1
DE69831900D1 DE69831900T DE69831900T DE69831900D1 DE 69831900 D1 DE69831900 D1 DE 69831900D1 DE 69831900 T DE69831900 T DE 69831900T DE 69831900 T DE69831900 T DE 69831900T DE 69831900 D1 DE69831900 D1 DE 69831900D1
Authority
DE
Germany
Prior art keywords
pins
jtag
user
programming mode
technique
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69831900T
Other languages
English (en)
Other versions
DE69831900T2 (de
Inventor
Xiaobao Wang
Bonnie Wang
Chiakang Sung
Khai Nguyen
Joseph Huang
Richard G Cliff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27574345&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69831900(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of DE69831900D1 publication Critical patent/DE69831900D1/de
Publication of DE69831900T2 publication Critical patent/DE69831900T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
DE69831900T 1997-06-10 1998-06-10 Programmier-Modus-Auswahl mit JTAG Schaltungen Expired - Lifetime DE69831900T2 (de)

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
US4927597P 1997-06-10 1997-06-10
US4924397P 1997-06-10 1997-06-10
US5299097P 1997-06-10 1997-06-10
US4924597P 1997-06-10 1997-06-10
US4924697P 1997-06-10 1997-06-10
US4924797P 1997-06-10 1997-06-10
US52990P 1997-06-10
US49275P 1997-06-10
US49243P 1997-06-10
US49247P 1997-06-10
US49245P 1997-06-10
US49246P 1997-06-10
US4947897P 1997-06-13 1997-06-13
US5095397P 1997-06-13 1997-06-13
US50953P 1997-06-13
US49478P 1997-06-13

Publications (2)

Publication Number Publication Date
DE69831900D1 true DE69831900D1 (de) 2005-11-24
DE69831900T2 DE69831900T2 (de) 2006-05-24

Family

ID=27574345

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831900T Expired - Lifetime DE69831900T2 (de) 1997-06-10 1998-06-10 Programmier-Modus-Auswahl mit JTAG Schaltungen

Country Status (4)

Country Link
US (3) US6421812B1 (de)
EP (1) EP0884599B1 (de)
JP (1) JPH1172541A (de)
DE (1) DE69831900T2 (de)

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US7913220B2 (en) * 2006-12-04 2011-03-22 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method
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US8176457B2 (en) * 2006-12-04 2012-05-08 Fujitsu Limited Apparatus and method updating diagram of circuit based on pin swap performed in package design with respect to PLD
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Also Published As

Publication number Publication date
EP0884599B1 (de) 2005-10-19
EP0884599A1 (de) 1998-12-16
DE69831900T2 (de) 2006-05-24
JPH1172541A (ja) 1999-03-16
US6681378B2 (en) 2004-01-20
US6314550B1 (en) 2001-11-06
US20020157078A1 (en) 2002-10-24
US6421812B1 (en) 2002-07-16

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