DE69832943D1 - Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem - Google Patents

Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem

Info

Publication number
DE69832943D1
DE69832943D1 DE69832943T DE69832943T DE69832943D1 DE 69832943 D1 DE69832943 D1 DE 69832943D1 DE 69832943 T DE69832943 T DE 69832943T DE 69832943 T DE69832943 T DE 69832943T DE 69832943 D1 DE69832943 D1 DE 69832943D1
Authority
DE
Germany
Prior art keywords
switch
control mechanism
sequence control
multiprocessor system
based multiprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69832943T
Other languages
English (en)
Other versions
DE69832943T2 (de
Inventor
Stephen R Vandoren
Simon C Steely
Madhumitra Sharma
David M Fenwick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of DE69832943D1 publication Critical patent/DE69832943D1/de
Application granted granted Critical
Publication of DE69832943T2 publication Critical patent/DE69832943T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
DE69832943T 1997-10-24 1998-10-12 Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem Expired - Lifetime DE69832943T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/957,298 US6122714A (en) 1997-10-24 1997-10-24 Order supporting mechanisms for use in a switch-based multi-processor system
US957298 1997-10-24

Publications (2)

Publication Number Publication Date
DE69832943D1 true DE69832943D1 (de) 2006-02-02
DE69832943T2 DE69832943T2 (de) 2006-06-29

Family

ID=25499385

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69832943T Expired - Lifetime DE69832943T2 (de) 1997-10-24 1998-10-12 Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem

Country Status (4)

Country Link
US (1) US6122714A (de)
EP (1) EP0911731B1 (de)
JP (1) JP4700773B2 (de)
DE (1) DE69832943T2 (de)

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US6467012B1 (en) 1999-07-08 2002-10-15 International Business Machines Corporation Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors
US6779036B1 (en) 1999-07-08 2004-08-17 International Business Machines Corporation Method and apparatus for achieving correct order among bus memory transactions in a physically distributed SMP system
US6591348B1 (en) 1999-09-09 2003-07-08 International Business Machines Corporation Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system
US6587930B1 (en) 1999-09-23 2003-07-01 International Business Machines Corporation Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock
US6725307B1 (en) 1999-09-23 2004-04-20 International Business Machines Corporation Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
US6457085B1 (en) 1999-11-04 2002-09-24 International Business Machines Corporation Method and system for data bus latency reduction using transfer size prediction for split bus designs
US6523076B1 (en) 1999-11-08 2003-02-18 International Business Machines Corporation Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks
US6529990B1 (en) 1999-11-08 2003-03-04 International Business Machines Corporation Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
US7529799B2 (en) 1999-11-08 2009-05-05 International Business Machines Corporation Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
US6516379B1 (en) 1999-11-08 2003-02-04 International Business Machines Corporation Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system
US6684279B1 (en) 1999-11-08 2004-01-27 International Business Machines Corporation Method, apparatus, and computer program product for controlling data transfer
US6606676B1 (en) 1999-11-08 2003-08-12 International Business Machines Corporation Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system
DE19956829A1 (de) * 1999-11-25 2001-06-07 Siemens Ag Speichereinrichtung für Prozessorsysteme
US6633960B1 (en) * 2000-08-31 2003-10-14 Hewlett-Packard Development Company, L.P. Scalable directory based cache coherence protocol
US6892279B2 (en) 2000-11-30 2005-05-10 Mosaid Technologies Incorporated Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency
US6587920B2 (en) 2000-11-30 2003-07-01 Mosaid Technologies Incorporated Method and apparatus for reducing latency in a memory system
US6493801B2 (en) 2001-01-26 2002-12-10 Compaq Computer Corporation Adaptive dirty-block purging
US6842830B2 (en) * 2001-03-31 2005-01-11 Intel Corporation Mechanism for handling explicit writeback in a cache coherent multi-node architecture
US7237016B1 (en) * 2001-09-07 2007-06-26 Palau Acquisition Corporation (Delaware) Method and system to manage resource requests utilizing link-list queues within an arbiter associated with an interconnect device
US8189591B2 (en) * 2001-10-30 2012-05-29 Exar Corporation Methods, systems and computer program products for packet ordering for parallel packet transform processing
US6961827B2 (en) * 2001-11-13 2005-11-01 Sun Microsystems, Inc. Victim invalidation
US20030196081A1 (en) * 2002-04-11 2003-10-16 Raymond Savarda Methods, systems, and computer program products for processing a packet-object using multiple pipelined processing modules
US6892290B2 (en) * 2002-10-03 2005-05-10 Hewlett-Packard Development Company, L.P. Linked-list early race resolution mechanism
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
JP2004171209A (ja) * 2002-11-19 2004-06-17 Matsushita Electric Ind Co Ltd 共有メモリデータ転送装置
US7636815B1 (en) * 2003-04-09 2009-12-22 Klaiber Alexander C System and method for handling direct memory accesses
US8751753B1 (en) 2003-04-09 2014-06-10 Guillermo J. Rozas Coherence de-coupling buffer
US8117392B2 (en) * 2003-10-22 2012-02-14 Intel Corporation Method and apparatus for efficient ordered stores over an interconnection network
US7856534B2 (en) * 2004-01-15 2010-12-21 Hewlett-Packard Development Company, L.P. Transaction references for requests in a multi-processor network
US7971002B1 (en) 2005-04-07 2011-06-28 Guillermo Rozas Maintaining instruction coherency in a translation-based computer system architecture
US7519778B2 (en) * 2005-08-10 2009-04-14 Faraday Technology Corp. System and method for cache coherence
US7958513B2 (en) * 2005-11-17 2011-06-07 International Business Machines Corporation Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment
JP5076418B2 (ja) * 2006-09-19 2012-11-21 ソニー株式会社 共有メモリ装置
US20080098178A1 (en) * 2006-10-23 2008-04-24 Veazey Judson E Data storage on a switching system coupling multiple processors of a computer system
US9075723B2 (en) * 2011-06-17 2015-07-07 International Business Machines Corporation Efficient discard scans

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US5655100A (en) * 1995-03-31 1997-08-05 Sun Microsystems, Inc. Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system

Also Published As

Publication number Publication date
EP0911731A2 (de) 1999-04-28
JP4700773B2 (ja) 2011-06-15
JPH11282820A (ja) 1999-10-15
EP0911731A3 (de) 2000-08-09
EP0911731B1 (de) 2005-12-28
DE69832943T2 (de) 2006-06-29
US6122714A (en) 2000-09-19

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