DE69835203D1 - Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschritten - Google Patents
Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschrittenInfo
- Publication number
- DE69835203D1 DE69835203D1 DE69835203T DE69835203T DE69835203D1 DE 69835203 D1 DE69835203 D1 DE 69835203D1 DE 69835203 T DE69835203 T DE 69835203T DE 69835203 T DE69835203 T DE 69835203T DE 69835203 D1 DE69835203 D1 DE 69835203D1
- Authority
- DE
- Germany
- Prior art keywords
- nmos
- manufacturing
- masking steps
- reduced masking
- pmos components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/844,924 US6060345A (en) | 1997-04-21 | 1997-04-21 | Method of making NMOS and PMOS devices with reduced masking steps |
| US844924 | 1997-04-21 | ||
| PCT/US1998/005516 WO1998048457A1 (en) | 1997-04-21 | 1998-03-19 | Method of making nmos and pmos devices with reduced masking steps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69835203D1 true DE69835203D1 (de) | 2006-08-24 |
| DE69835203T2 DE69835203T2 (de) | 2007-07-05 |
Family
ID=25293980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69835203T Expired - Lifetime DE69835203T2 (de) | 1997-04-21 | 1998-03-19 | Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschritten |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6060345A (de) |
| EP (1) | EP0978141B1 (de) |
| JP (1) | JP2001524263A (de) |
| KR (1) | KR100512029B1 (de) |
| DE (1) | DE69835203T2 (de) |
| WO (1) | WO1998048457A1 (de) |
Families Citing this family (62)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6821852B2 (en) * | 2001-02-13 | 2004-11-23 | Micron Technology, Inc. | Dual doped gates |
| JP2002299469A (ja) * | 2001-04-04 | 2002-10-11 | Seiko Instruments Inc | 半導体装置 |
| US6531365B2 (en) * | 2001-06-22 | 2003-03-11 | International Business Machines Corporation | Anti-spacer structure for self-aligned independent gate implantation |
| KR100388464B1 (ko) * | 2001-06-30 | 2003-06-25 | 주식회사 하이닉스반도체 | 반도체 메모리장치의 제조방법 |
| US6642147B2 (en) | 2001-08-23 | 2003-11-04 | International Business Machines Corporation | Method of making thermally stable planarizing films |
| JP2003179071A (ja) * | 2001-10-25 | 2003-06-27 | Sharp Corp | Ｍｄｄおよび選択ｃｖｄシリサイドを用いて深いサブミクロンｃｍｏｓソース／ドレインを製造する方法 |
| US6882013B2 (en) * | 2002-01-31 | 2005-04-19 | Texas Instruments Incorporated | Transistor with reduced short channel effects and method |
| US6562713B1 (en) | 2002-02-19 | 2003-05-13 | International Business Machines Corporation | Method of protecting semiconductor areas while exposing a gate |
| US20040152331A1 (en) * | 2003-01-31 | 2004-08-05 | Applied Materials, Inc. | Process for etching polysilicon gates with good mask selectivity, critical dimension control, and cleanliness |
| KR100598033B1 (ko) * | 2004-02-03 | 2006-07-07 | 삼성전자주식회사 | 반도체 소자의 듀얼 게이트 산화막 형성 방법 |
| KR100800683B1 (ko) * | 2006-08-31 | 2008-02-01 | 동부일렉트로닉스 주식회사 | 반도체 소자의 형성방법 |
| US8431972B2 (en) * | 2006-12-13 | 2013-04-30 | Infineon Technologies Ag | Semiconductor ESD device and method of making same |
| TW200903655A (en) * | 2007-07-02 | 2009-01-16 | Promos Technologies Inc | Method of fabricating high-voltage MOS having doubled-diffused drain |
| US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
| US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
| US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
| CN101866931A (zh) * | 2010-05-19 | 2010-10-20 | 中国科学院微电子研究所 | 半导体结构及其形成方法 |
| US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
| US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
| US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
| KR101195269B1 (ko) * | 2011-02-15 | 2012-11-14 | 에스케이하이닉스 주식회사 | 낮은 컨택저항을 갖는 반도체소자의 제조방법 |
| US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
| US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
| US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
| US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
| US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
| US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
| US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
| US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
| US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
| US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
| US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
| WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
| US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
| US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
| US8557647B2 (en) * | 2011-09-09 | 2013-10-15 | International Business Machines Corporation | Method for fabricating field effect transistor devices with high-aspect ratio mask |
| US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
| US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
| US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
| US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
| US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
| US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
| US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
| US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
| US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
| US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
| US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
| US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
| US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
| US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
| US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
| WO2014071049A2 (en) | 2012-10-31 | 2014-05-08 | Suvolta, Inc. | Dram-type device with low variation transistor peripheral circuits, and related methods |
| US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
| US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
| US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
| US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
| US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
| US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
| US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
| RU2702101C2 (ru) * | 2014-07-09 | 2019-10-04 | Пьер Фабр Медикамент | Способ лечения двигательных расстройств бефирадолом |
| US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
| US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825270A (ja) * | 1981-08-07 | 1983-02-15 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| US4599789A (en) * | 1984-06-15 | 1986-07-15 | Harris Corporation | Process of making twin well VLSI CMOS |
| US4561170A (en) * | 1984-07-02 | 1985-12-31 | Texas Instruments Incorporated | Method of making field-plate isolated CMOS devices |
| EP0173953B1 (de) * | 1984-08-28 | 1991-07-17 | Kabushiki Kaisha Toshiba | Verfahren zum Herstellen einer Halbleiteranordnung mit Gateelektrode |
| US4621412A (en) * | 1984-09-17 | 1986-11-11 | Sony Corporation | Manufacturing a complementary MOSFET |
| JPS63196070A (ja) * | 1987-02-10 | 1988-08-15 | Sony Corp | Ｃｍｏｓの製造方法 |
| IT1225614B (it) * | 1988-08-04 | 1990-11-22 | Sgs Thomson Microelectronics | Processo per la fabbricazione di dispositivi integrati cmos con lunghezze di gate ridotte e drain leggermente drogato |
| JPH0770727B2 (ja) * | 1989-06-16 | 1995-07-31 | 日本電装株式会社 | Ｍｉｓトランジスタ及び相補形ｍｉｓトランジスタの製造方法 |
| US4956311A (en) * | 1989-06-27 | 1990-09-11 | National Semiconductor Corporation | Double-diffused drain CMOS process using a counterdoping technique |
| KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
| US5282972A (en) * | 1991-12-18 | 1994-02-01 | Kelco Water Engineering, Inc. | Method and apparatus for recycling R/O waste water |
| JP3055424B2 (ja) * | 1994-04-28 | 2000-06-26 | 株式会社デンソー | Ｍｉｓ型半導体装置の製造方法 |
| US5457060A (en) * | 1994-06-20 | 1995-10-10 | Winbond Electronics Corporation | Process for manufactuirng MOSFET having relatively shallow junction of doped region |
| US5512506A (en) * | 1995-04-06 | 1996-04-30 | Advanced Micro Devices, Inc. | Lightly doped drain profile optimization with high energy implants |
| US5624863A (en) * | 1995-07-17 | 1997-04-29 | Micron Technology, Inc. | Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate |
| US5686324A (en) * | 1996-03-28 | 1997-11-11 | Mosel Vitelic, Inc. | Process for forming LDD CMOS using large-tilt-angle ion implantation |
| US5677224A (en) * | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
-
1997
- 1997-04-21 US US08/844,924 patent/US6060345A/en not_active Expired - Lifetime
-
1998
- 1998-03-19 EP EP98912999A patent/EP0978141B1/de not_active Expired - Lifetime
- 1998-03-19 KR KR10-1999-7009695A patent/KR100512029B1/ko not_active IP Right Cessation
- 1998-03-19 DE DE69835203T patent/DE69835203T2/de not_active Expired - Lifetime
- 1998-03-19 JP JP54583398A patent/JP2001524263A/ja active Pending
- 1998-03-19 WO PCT/US1998/005516 patent/WO1998048457A1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010020140A (ko) | 2001-03-15 |
| EP0978141A1 (de) | 2000-02-09 |
| EP0978141B1 (de) | 2006-07-12 |
| US6060345A (en) | 2000-05-09 |
| JP2001524263A (ja) | 2001-11-27 |
| KR100512029B1 (ko) | 2005-09-05 |
| DE69835203T2 (de) | 2007-07-05 |
| WO1998048457A1 (en) | 1998-10-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY |
|
| 8328 | Change in the person/name/address of the agent |
Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, |