DE69837028D1 - Herstellungsverfahren eines festwertspeichers das den epromprozess mit dem standard-cmos-prozess kombiniert - Google Patents
Herstellungsverfahren eines festwertspeichers das den epromprozess mit dem standard-cmos-prozess kombiniertInfo
- Publication number
- DE69837028D1 DE69837028D1 DE69837028T DE69837028T DE69837028D1 DE 69837028 D1 DE69837028 D1 DE 69837028D1 DE 69837028 T DE69837028 T DE 69837028T DE 69837028 T DE69837028 T DE 69837028T DE 69837028 D1 DE69837028 D1 DE 69837028D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- eprom
- fixed memory
- standard cmos
- memory combining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97200945 | 1997-04-01 | ||
EP97200945 | 1997-04-01 | ||
PCT/IB1998/000284 WO1998044552A2 (en) | 1997-04-01 | 1998-03-05 | Method of manufacturing a non-volatile memory combining an eprom with a standard cmos process |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69837028D1 true DE69837028D1 (de) | 2007-03-22 |
DE69837028T2 DE69837028T2 (de) | 2008-01-10 |
Family
ID=8228159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69837028T Expired - Lifetime DE69837028T2 (de) | 1997-04-01 | 1998-03-05 | Herstellungsverfahren eines festwertspeichers das den epromprozess mit dem standard-cmos-prozess kombiniert |
Country Status (6)
Country | Link |
---|---|
US (1) | US6069033A (de) |
EP (1) | EP0914679B1 (de) |
JP (1) | JP2000511707A (de) |
DE (1) | DE69837028T2 (de) |
TW (1) | TW360951B (de) |
WO (1) | WO1998044552A2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW420874B (en) * | 1998-05-04 | 2001-02-01 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device |
KR100269510B1 (ko) * | 1998-05-20 | 2000-10-16 | 윤종용 | 반도체 장치의 제조 방법 |
GB2359662B (en) * | 1998-05-20 | 2002-01-16 | Samsung Electronics Co Ltd | A semiconductor device |
TW415045B (en) * | 1999-08-10 | 2000-12-11 | United Microelectronics Corp | Manufacture of embedded flash memory |
EP1156524B1 (de) * | 2000-05-15 | 2014-10-22 | Micron Technology, Inc. | Herstellungsverfahren für einen integrierten Schaltkreis mit Hochdichte- und Logik-Bauelementeteil |
US6277690B1 (en) * | 2000-11-02 | 2001-08-21 | Advanced Micro Devices, Inc. | Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant |
CN100372068C (zh) * | 2002-06-20 | 2008-02-27 | Nxp股份有限公司 | 导电间隔物延伸的浮栅 |
EP1569274B1 (de) | 2004-02-24 | 2010-01-20 | STMicroelectronics S.r.l. | Herstellungsverfahren für integrierte Halbleiter-Festwertspeicherbauelemente |
US7101748B2 (en) * | 2004-02-26 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company | Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices |
US8035156B2 (en) * | 2008-09-30 | 2011-10-11 | Freescale Semiconductor, Inc. | Split-gate non-volatile memory cell and method |
KR20170007928A (ko) * | 2015-07-13 | 2017-01-23 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 소자 제조 방법 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1196997B (it) * | 1986-07-25 | 1988-11-25 | Sgs Microelettronica Spa | Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati |
US5223451A (en) * | 1989-10-06 | 1993-06-29 | Kabushiki Kaisha Toshiba | Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and nonvolatile memory cell are formed in one chip and method of making it |
US5153143A (en) * | 1990-02-26 | 1992-10-06 | Delco Electronics Corporation | Method of manufacturing CMOS integrated circuit with EEPROM |
KR960009995B1 (ko) * | 1992-07-31 | 1996-07-25 | 삼성전자 주식회사 | 반도체 장치의 제조 방법 및 그 구조 |
CA2107602C (en) * | 1992-10-07 | 2004-01-20 | Andrew Jan Walker | Method of manufacturing an integrated circuit and integrated circuit obtained by this method |
EP0595250B1 (de) * | 1992-10-27 | 1999-01-07 | Nec Corporation | Verfahren zur Herstellung eines nicht-flüchtigen Halbleiter-Speicherbauteils |
TW347567B (en) * | 1996-03-22 | 1998-12-11 | Philips Eloctronics N V | Semiconductor device and method of manufacturing a semiconductor device |
-
1997
- 1997-09-11 TW TW086113183A patent/TW360951B/zh not_active IP Right Cessation
-
1998
- 1998-03-05 WO PCT/IB1998/000284 patent/WO1998044552A2/en active IP Right Grant
- 1998-03-05 JP JP10529306A patent/JP2000511707A/ja not_active Ceased
- 1998-03-05 DE DE69837028T patent/DE69837028T2/de not_active Expired - Lifetime
- 1998-03-05 EP EP98903265A patent/EP0914679B1/de not_active Expired - Lifetime
- 1998-03-19 US US09/044,544 patent/US6069033A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6069033A (en) | 2000-05-30 |
JP2000511707A (ja) | 2000-09-05 |
TW360951B (en) | 1999-06-11 |
WO1998044552A2 (en) | 1998-10-08 |
DE69837028T2 (de) | 2008-01-10 |
WO1998044552A3 (en) | 1999-01-21 |
EP0914679B1 (de) | 2007-02-07 |
EP0914679A2 (de) | 1999-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de | ||
8370 | Indication related to discontinuation of the patent is to be deleted | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |