DE69837980D1 - Struktur und Verfahren zum Reparieren einer integrierten Schaltung - Google Patents

Struktur und Verfahren zum Reparieren einer integrierten Schaltung

Info

Publication number
DE69837980D1
DE69837980D1 DE69837980T DE69837980T DE69837980D1 DE 69837980 D1 DE69837980 D1 DE 69837980D1 DE 69837980 T DE69837980 T DE 69837980T DE 69837980 T DE69837980 T DE 69837980T DE 69837980 D1 DE69837980 D1 DE 69837980D1
Authority
DE
Germany
Prior art keywords
repairing
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69837980T
Other languages
English (en)
Inventor
Philippe Chaisemartin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69837980D1 publication Critical patent/DE69837980D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69837980T 1997-09-25 1998-09-24 Struktur und Verfahren zum Reparieren einer integrierten Schaltung Expired - Lifetime DE69837980D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9712168A FR2768860B1 (fr) 1997-09-25 1997-09-25 Structure et procede de reparation de circuits integres

Publications (1)

Publication Number Publication Date
DE69837980D1 true DE69837980D1 (de) 2007-08-09

Family

ID=9511644

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837980T Expired - Lifetime DE69837980D1 (de) 1997-09-25 1998-09-24 Struktur und Verfahren zum Reparieren einer integrierten Schaltung

Country Status (4)

Country Link
US (2) US6236228B1 (de)
EP (1) EP0905766B1 (de)
DE (1) DE69837980D1 (de)
FR (1) FR2768860B1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2768860B1 (fr) 1997-09-25 1999-11-26 Sgs Thomson Microelectronics Structure et procede de reparation de circuits integres
US7287177B2 (en) * 2003-12-04 2007-10-23 International Business Machines Corporation Digital reliability monitor having autonomic repair and notification capability
US20050144524A1 (en) * 2003-12-04 2005-06-30 International Business Machines Corporation Digital reliability monitor having autonomic repair and notification capability
KR100718216B1 (ko) * 2004-12-13 2007-05-15 가부시끼가이샤 도시바 반도체 장치, 패턴 레이아웃 작성 방법, 노광 마스크
US9236343B2 (en) * 2013-05-03 2016-01-12 Blackcomb Design Automation Inc. Architecture of spare wiring structures for improved engineering change orders

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679967A (en) * 1985-01-20 1997-10-21 Chip Express (Israel) Ltd. Customizable three metal layer gate array devices
US5512397A (en) 1988-05-16 1996-04-30 Leedy; Glenn J. Stepper scanner discretionary lithography and common mask discretionary lithography for integrated circuits
EP0557079B1 (de) * 1992-02-18 1998-12-23 Elm Technology Corporation Lithographie nach Bedarf für integrierte Schaltungen
JPH06125067A (ja) * 1992-10-12 1994-05-06 Mitsubishi Electric Corp 半導体集積回路及びその設計方法
JP2909328B2 (ja) * 1992-11-02 1999-06-23 株式会社東芝 フィールドプログラマブルゲートアレイ
US5777887A (en) * 1995-05-12 1998-07-07 Crosspoint Solutions, Inc. FPGA redundancy
US5798937A (en) * 1995-09-28 1998-08-25 Motorola, Inc. Method and apparatus for forming redundant vias between conductive layers of an integrated circuit
FR2741475B1 (fr) * 1995-11-17 2000-05-12 Commissariat Energie Atomique Procede de fabrication d'un dispositif de micro-electronique comportant sur un substrat une pluralite d'elements interconnectes
US5892249A (en) * 1996-02-23 1999-04-06 National Semiconductor Corporation Integrated circuit having reprogramming cell
FR2768860B1 (fr) 1997-09-25 1999-11-26 Sgs Thomson Microelectronics Structure et procede de reparation de circuits integres
US6404226B1 (en) * 1999-09-21 2002-06-11 Lattice Semiconductor Corporation Integrated circuit with standard cell logic and spare gates

Also Published As

Publication number Publication date
FR2768860B1 (fr) 1999-11-26
EP0905766B1 (de) 2007-06-27
FR2768860A1 (fr) 1999-03-26
EP0905766A1 (de) 1999-03-31
US6236228B1 (en) 2001-05-22
US6586961B2 (en) 2003-07-01
US20020093037A1 (en) 2002-07-18

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Legal Events

Date Code Title Description
8332 No legal effect for de