DE69904241D1 - Konfigurierbarer logischer block in einem nutzerprogrammierbaren gatterfeld mit einer vielzwecklogig/speicherschaltung - Google Patents

Konfigurierbarer logischer block in einem nutzerprogrammierbaren gatterfeld mit einer vielzwecklogig/speicherschaltung

Info

Publication number
DE69904241D1
DE69904241D1 DE69904241T DE69904241T DE69904241D1 DE 69904241 D1 DE69904241 D1 DE 69904241D1 DE 69904241 T DE69904241 T DE 69904241T DE 69904241 T DE69904241 T DE 69904241T DE 69904241 D1 DE69904241 D1 DE 69904241D1
Authority
DE
Germany
Prior art keywords
gatter
multipurpose
log
field
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69904241T
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English (en)
Other versions
DE69904241T2 (de
Inventor
D Wittig
Sundararajarao Mohan
A Carberry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE69904241D1 publication Critical patent/DE69904241D1/de
Publication of DE69904241T2 publication Critical patent/DE69904241T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed
DE69904241T 1999-02-25 1999-09-21 Konfigurierbarer logischer block in einem nutzerprogrammierbaren gatterfeld mit einer vielzwecklogig/speicherschaltung Expired - Lifetime DE69904241T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/258,024 US6150838A (en) 1999-02-25 1999-02-25 FPGA configurable logic block with multi-purpose logic/memory circuit
PCT/US1999/021993 WO2000051239A1 (en) 1999-02-25 1999-09-21 Fpga configurable logic block with multi-purpose logic/memory circuit

Publications (2)

Publication Number Publication Date
DE69904241D1 true DE69904241D1 (de) 2003-01-09
DE69904241T2 DE69904241T2 (de) 2003-09-11

Family

ID=22978780

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69904241T Expired - Lifetime DE69904241T2 (de) 1999-02-25 1999-09-21 Konfigurierbarer logischer block in einem nutzerprogrammierbaren gatterfeld mit einer vielzwecklogig/speicherschaltung

Country Status (5)

Country Link
US (4) US6150838A (de)
EP (1) EP1163725B1 (de)
JP (1) JP4319786B2 (de)
DE (1) DE69904241T2 (de)
WO (1) WO2000051239A1 (de)

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DE69904241T2 (de) 2003-09-11
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US6208163B1 (en) 2001-03-27
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US20010043082A1 (en) 2001-11-22
US6150838A (en) 2000-11-21

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