DE69913500D1 - Mehrprozessor-Anordnung mit geteiltem Speicherzugriff unter Vorrang-Kontrolle - Google Patents

Mehrprozessor-Anordnung mit geteiltem Speicherzugriff unter Vorrang-Kontrolle

Info

Publication number
DE69913500D1
DE69913500D1 DE69913500T DE69913500T DE69913500D1 DE 69913500 D1 DE69913500 D1 DE 69913500D1 DE 69913500 T DE69913500 T DE 69913500T DE 69913500 T DE69913500 T DE 69913500T DE 69913500 D1 DE69913500 D1 DE 69913500D1
Authority
DE
Germany
Prior art keywords
data memory
processors
present
processor
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69913500T
Other languages
English (en)
Other versions
DE69913500T2 (de
Inventor
Hook J Van
Gulbin Ezer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Corp
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Application granted granted Critical
Publication of DE69913500D1 publication Critical patent/DE69913500D1/de
Publication of DE69913500T2 publication Critical patent/DE69913500T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
DE69913500T 1998-03-05 1999-03-02 Mehrprozessor-Anordnung mit geteiltem Speicherzugriff unter Vorrang-Kontrolle Expired - Lifetime DE69913500T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US35687 1987-04-02
US09/035,687 US6567426B1 (en) 1998-03-05 1998-03-05 Preemptive timer multiplexed shared memory access
PCT/US1999/004615 WO1999045472A1 (en) 1998-03-05 1999-03-02 Multi-processor system with shared memory

Publications (2)

Publication Number Publication Date
DE69913500D1 true DE69913500D1 (de) 2004-01-22
DE69913500T2 DE69913500T2 (de) 2004-09-16

Family

ID=21884216

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69913500T Expired - Lifetime DE69913500T2 (de) 1998-03-05 1999-03-02 Mehrprozessor-Anordnung mit geteiltem Speicherzugriff unter Vorrang-Kontrolle

Country Status (6)

Country Link
US (1) US6567426B1 (de)
EP (1) EP1058891B1 (de)
JP (1) JP4426099B2 (de)
AT (1) ATE256311T1 (de)
DE (1) DE69913500T2 (de)
WO (1) WO1999045472A1 (de)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7003593B2 (en) * 1997-12-17 2006-02-21 Src Computers, Inc. Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port
TW448365B (en) * 1999-11-15 2001-08-01 Via Tech Inc Bus arbitration method providing preemption function between control chip sets
US6473821B1 (en) * 1999-12-21 2002-10-29 Visteon Global Technologies, Inc. Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems
JP5185478B2 (ja) * 2000-02-29 2013-04-17 富士通セミコンダクター株式会社 パイプライン処理方法並びにその方法を利用するパイプライン処理装置
US7360028B1 (en) * 2000-05-05 2008-04-15 Sun Microsystems, Inc. Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol
US7096324B1 (en) 2000-06-12 2006-08-22 Altera Corporation Embedded processor with dual-port SRAM for programmable logic
US6868486B1 (en) * 2000-08-25 2005-03-15 Ncr Corporation Providing multiple memory controllers on a memory bus
US8160864B1 (en) 2000-10-26 2012-04-17 Cypress Semiconductor Corporation In-circuit emulator and pod synchronized boot
US8103496B1 (en) 2000-10-26 2012-01-24 Cypress Semicondutor Corporation Breakpoint control in an in-circuit emulation system
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US7765095B1 (en) 2000-10-26 2010-07-27 Cypress Semiconductor Corporation Conditional branching in an in-circuit emulation system
US6950954B1 (en) * 2000-10-26 2005-09-27 Cypress Semiconductor Corporation Method and circuit for synchronizing a write operation between an on-chip microprocessor and an on-chip programmable analog device operating at different frequencies
US8149048B1 (en) 2000-10-26 2012-04-03 Cypress Semiconductor Corporation Apparatus and method for programmable power management in a programmable analog circuit block
US6675268B1 (en) * 2000-12-11 2004-01-06 Lsi Logic Corporation Method and apparatus for handling transfers of data volumes between controllers in a storage environment having multiple paths to the data volumes
US7675972B1 (en) * 2001-07-30 2010-03-09 Vixs Systems, Inc. System and method for multiple channel video transcoding
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
US8078970B1 (en) 2001-11-09 2011-12-13 Cypress Semiconductor Corporation Graphical user interface with user-selectable list-box
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US7770113B1 (en) 2001-11-19 2010-08-03 Cypress Semiconductor Corporation System and method for dynamically generating a configuration datasheet
US7774190B1 (en) 2001-11-19 2010-08-10 Cypress Semiconductor Corporation Sleep and stall in an in-circuit emulation system
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US7844437B1 (en) 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US8069405B1 (en) 2001-11-19 2011-11-29 Cypress Semiconductor Corporation User interface for efficiently browsing an electronic document using data-driven tabs
JP4335516B2 (ja) * 2001-12-04 2009-09-30 パナソニック株式会社 複数のプロセッサを用いた動画像符号化装置およびその方法
US8103497B1 (en) 2002-03-28 2012-01-24 Cypress Semiconductor Corporation External interface for event architecture
US7308608B1 (en) 2002-05-01 2007-12-11 Cypress Semiconductor Corporation Reconfigurable testing system and method
US7761845B1 (en) 2002-09-09 2010-07-20 Cypress Semiconductor Corporation Method for parameterizing a user module
EP1550953A1 (de) * 2003-12-29 2005-07-06 CNX S.p.A. Verfahren und Vorrichtung zur Implementierung von zeit-multiplex Zugriff auf einen Dual-port RAM von verschiedenen Datenquellen mit eigenem Taktsignal
US7295049B1 (en) 2004-03-25 2007-11-13 Cypress Semiconductor Corporation Method and circuit for rapid alignment of signals
US8286125B2 (en) 2004-08-13 2012-10-09 Cypress Semiconductor Corporation Model for a hardware device-independent method of defining embedded firmware for programmable systems
US8082531B2 (en) * 2004-08-13 2011-12-20 Cypress Semiconductor Corporation Method and an apparatus to design a processing system using a graphical user interface
US8069436B2 (en) 2004-08-13 2011-11-29 Cypress Semiconductor Corporation Providing hardware independence to automate code generation of processing device firmware
US7587310B2 (en) * 2004-08-30 2009-09-08 Lsi Corporation Sound processor architecture using single port memory unit
US7281093B1 (en) * 2004-12-21 2007-10-09 Xilinx, Inc. Memory apparatus for a message processing system and method of providing same
US8279886B2 (en) * 2004-12-30 2012-10-02 Intel Corporation Dataport and methods thereof
US7332976B1 (en) 2005-02-04 2008-02-19 Cypress Semiconductor Corporation Poly-phase frequency synthesis oscillator
US7500066B2 (en) * 2005-04-30 2009-03-03 Tellabs Operations, Inc. Method and apparatus for sharing instruction memory among a plurality of processors
WO2006117746A1 (en) * 2005-05-04 2006-11-09 Nxp B.V. Memory controller and method for controlling access to a memory, as well as system comprising a memory controller
US7400183B1 (en) 2005-05-05 2008-07-15 Cypress Semiconductor Corporation Voltage controlled oscillator delay cell and method
US8089461B2 (en) 2005-06-23 2012-01-03 Cypress Semiconductor Corporation Touch wake for electronic devices
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
US8067948B2 (en) 2006-03-27 2011-11-29 Cypress Semiconductor Corporation Input/output multiplexer bus
JP2007265019A (ja) * 2006-03-28 2007-10-11 Sony Computer Entertainment Inc 演算処理装置
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8516025B2 (en) 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US8130025B2 (en) 2007-04-17 2012-03-06 Cypress Semiconductor Corporation Numerical band gap
US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
US9720805B1 (en) 2007-04-25 2017-08-01 Cypress Semiconductor Corporation System and method for controlling a target device
US8049569B1 (en) 2007-09-05 2011-11-01 Cypress Semiconductor Corporation Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
KR101949123B1 (ko) * 2012-02-27 2019-02-18 삼성전자주식회사 데이터 복호화 장치 및 방법
BR112016000972A2 (pt) * 2013-07-18 2017-08-22 Benjamin A Gittins Computing architecture with peripherals

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854478A (ja) * 1981-09-29 1983-03-31 Fujitsu Ltd 主記憶制御方法
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US5623628A (en) * 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5651137A (en) * 1995-04-12 1997-07-22 Intel Corporation Scalable cache attributes for an input/output bus
US5682484A (en) 1995-11-20 1997-10-28 Advanced Micro Devices, Inc. System and method for transferring data streams simultaneously on multiple buses in a computer system

Also Published As

Publication number Publication date
JP4426099B2 (ja) 2010-03-03
DE69913500T2 (de) 2004-09-16
EP1058891B1 (de) 2003-12-10
US6567426B1 (en) 2003-05-20
WO1999045472A1 (en) 1999-09-10
JP2002506251A (ja) 2002-02-26
ATE256311T1 (de) 2003-12-15
EP1058891A1 (de) 2000-12-13

Similar Documents

Publication Publication Date Title
DE69913500D1 (de) Mehrprozessor-Anordnung mit geteiltem Speicherzugriff unter Vorrang-Kontrolle
US5367690A (en) Multiprocessing system using indirect addressing to access respective local semaphore registers bits for setting the bit or branching if the bit is set
US4449183A (en) Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
AU590626B2 (en) Method and apparatus for implementing a bus protocol
DE69701078D1 (de) Mikroprozessorarchitektur mit der Möglichkeit zur Unterstützung mehrerer verschiedener Prozessoren
CA2245106A1 (en) Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access
GB2074762A (en) Multi-processor systems
JPH03154910A (ja) システムメモリ装置に記憶されたコード化プログラム命令に応答して動作する型のコンピュータシステム
JPH0354660A (ja) マルチプロセッサシステムにおける共有メモリ管理方式
EP1132818B1 (de) Verfahren und Anordnung zum Arbitrieren des Zugriffes eines Zeitmutiplex-verteilten Speichers von mehreren Prozessoren in einem Echtzeitsystem
SE9203016L (sv) Signalbehandlingssystem med delat dataminne
US6499087B1 (en) Synchronous memory sharing based on cycle stealing
DE60019324D1 (de) Teilen von resourcen zwischen einheiten
KR100307620B1 (ko) 백플레인버스를시분할방식으로사용하기위한버스용모듈
JPS62194568A (ja) システム・バス権制御回路
KR940008484B1 (ko) 하이파이 버스를 채용한 다중처리기 시스템의 데이타 응답시간 최소화 방법
JPH02133856A (ja) データ転送装置
Chandwani et al. A multiple-PC based architecture for global database access
JPS5469923A (en) Memory shared device
JPS61264463A (ja) バス制御方式
Cross et al. Modelling the vocal tract using multiple digital signal processors
JPS5553720A (en) Data transfer control system
JPS6082349U (ja) 共有メモリのアクセス制御装置
JPH08235125A (ja) マルチプロセッサ装置
JP2000020491A (ja) マルチプロセッサシステム

Legal Events

Date Code Title Description
8364 No opposition during term of opposition