DE69925991D1 - Verfahren und vorrichtung zur zugangsarbitrierung zu mehreren bussen in einem datenverarbeitungssystem - Google Patents

Verfahren und vorrichtung zur zugangsarbitrierung zu mehreren bussen in einem datenverarbeitungssystem

Info

Publication number
DE69925991D1
DE69925991D1 DE69925991T DE69925991T DE69925991D1 DE 69925991 D1 DE69925991 D1 DE 69925991D1 DE 69925991 T DE69925991 T DE 69925991T DE 69925991 T DE69925991 T DE 69925991T DE 69925991 D1 DE69925991 D1 DE 69925991D1
Authority
DE
Germany
Prior art keywords
data processing
processing system
access arbitration
several buses
buses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69925991T
Other languages
English (en)
Inventor
M Gehman
R Settles
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE69925991D1 publication Critical patent/DE69925991D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/4031Coupling between buses using bus bridges with arbitration
DE69925991T 1998-03-31 1999-03-29 Verfahren und vorrichtung zur zugangsarbitrierung zu mehreren bussen in einem datenverarbeitungssystem Expired - Lifetime DE69925991D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/052,853 US6260093B1 (en) 1998-03-31 1998-03-31 Method and apparatus for arbitrating access to multiple buses in a data processing system
PCT/US1999/006774 WO1999050753A1 (en) 1998-03-31 1999-03-29 Method and apparatus for arbitrating access to multiple buses in a data processing system

Publications (1)

Publication Number Publication Date
DE69925991D1 true DE69925991D1 (de) 2005-08-04

Family

ID=21980323

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69925991T Expired - Lifetime DE69925991D1 (de) 1998-03-31 1999-03-29 Verfahren und vorrichtung zur zugangsarbitrierung zu mehreren bussen in einem datenverarbeitungssystem

Country Status (4)

Country Link
US (1) US6260093B1 (de)
EP (1) EP1068573B1 (de)
DE (1) DE69925991D1 (de)
WO (1) WO1999050753A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6895456B2 (en) * 1998-12-01 2005-05-17 Hewlett-Packard Development Company, L.P. System supporting multicast master cycles between different busses in a computer system
US6442642B1 (en) * 1999-09-30 2002-08-27 Conexant Systems, Inc. System and method for providing an improved synchronous operation of an advanced peripheral bus with backward compatibility
US6757762B1 (en) * 1999-10-29 2004-06-29 Unisys Corporation Multi-mode processor bus bridge
US6760802B2 (en) * 2000-09-08 2004-07-06 Texas Instruments Incorporated Time-out counter for multiple transaction bus system bus bridge
US6859852B2 (en) 2000-09-08 2005-02-22 Texas Instruments Incorporated Immediate grant bus arbiter for bus system
US6775732B2 (en) * 2000-09-08 2004-08-10 Texas Instruments Incorporated Multiple transaction bus system
US6691193B1 (en) * 2000-10-18 2004-02-10 Sony Corporation Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses
US7036033B1 (en) * 2001-01-04 2006-04-25 3Pardata, Inc. Disk enclosure with multiplexers for connecting 12C buses in multiple power domains
US6976108B2 (en) * 2001-01-31 2005-12-13 Samsung Electronics Co., Ltd. System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities
US6959354B2 (en) * 2001-03-08 2005-10-25 Sony Corporation Effective bus utilization using multiple bus interface circuits and arbitration logic circuit
US7020733B2 (en) * 2002-10-09 2006-03-28 Samsung Electronics Co., Ltd. Data bus system and method for performing cross-access between buses
US7007122B2 (en) * 2002-11-27 2006-02-28 Lsi Logic Corporation Method for pre-emptive arbitration
JP2005332145A (ja) * 2004-05-19 2005-12-02 Nec Electronics Corp データ転送制御回路及びデータ転送方法
US20060168382A1 (en) * 2005-01-25 2006-07-27 International Business Machines Corporation Resolving conflicting requests for use of shared resources
EP2529313A4 (de) * 2010-01-29 2016-03-16 Hewlett Packard Development Co Verfahren und system für eine zwischenkarte
US20130191572A1 (en) * 2012-01-23 2013-07-25 Qualcomm Incorporated Transaction ordering to avoid bus deadlocks

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4373183A (en) 1980-08-20 1983-02-08 Ibm Corporation Bus interface units sharing a common bus using distributed control for allocation of the bus
JPS5945527A (ja) 1982-09-07 1984-03-14 Hitachi Ltd バス制御方法
US4930102A (en) 1983-04-29 1990-05-29 The Regents Of The University Of California Dynamic activity-creating data-driven computer architecture
EP0357075A3 (de) 1988-09-02 1991-12-11 Fujitsu Limited Datensteuerungsvorrichtung und System mit Anwendung dieser Vorrichtung
EP0391537B1 (de) 1989-04-07 1995-06-21 Tektronix Inc. Bus-zu-Bus Schnittstellensystem mit Konvertierung der Verriegelung
US5301333A (en) 1990-06-14 1994-04-05 Bell Communications Research, Inc. Tree structured variable priority arbitration implementing a round-robin scheduling policy
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
US5420985A (en) 1992-07-28 1995-05-30 Texas Instruments Inc. Bus arbiter system and method utilizing hardware and software which is capable of operation in distributed mode or central mode
US5353415A (en) 1992-10-02 1994-10-04 Compaq Computer Corporation Method and apparatus for concurrency of bus operations
US5511165A (en) 1992-10-23 1996-04-23 International Business Machines Corporation Method and apparatus for communicating data across a bus bridge upon request
US5396602A (en) 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
US5708794A (en) * 1993-08-10 1998-01-13 Dell Usa, L.P. Multi-purpose usage of transaction backoff and bus architecture supporting same
US5717873A (en) * 1993-09-30 1998-02-10 Intel Corporation Deadlock avoidance mechanism and method for multiple bus topology
US5857084A (en) * 1993-11-02 1999-01-05 Klein; Dean A. Hierarchical bus structure access system
EP0654743A1 (de) 1993-11-19 1995-05-24 International Business Machines Corporation Rechnersystem mit einem lokalen Bus eines Digitalsignalprozessors
US5546546A (en) 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
JP3454294B2 (ja) * 1994-06-20 2003-10-06 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプル・バス情報処理システム及びブリッジ回路
US5555383A (en) * 1994-11-07 1996-09-10 International Business Machines Corporation Peripheral component interconnect bus system having latency and shadow timers
US5621900A (en) * 1995-05-17 1997-04-15 Intel Corporation Method and apparatus for claiming bus access from a first bus to a second bus prior to the subtractive decode agent claiming the transaction without decoding the transaction
US5619661A (en) 1995-06-05 1997-04-08 Vlsi Technology, Inc. Dynamic arbitration system and method
US5838935A (en) * 1995-06-15 1998-11-17 Intel Corporation Method and apparatus providing programmable decode modes for secondary PCI bus interfaces
AU6334496A (en) * 1995-06-15 1997-01-15 Intel Corporation Architecture for an i/o processor that integrates a pci to pci bridge
US5734850A (en) * 1995-07-05 1998-03-31 National Semiconductor Corporation Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus
US5632021A (en) * 1995-10-25 1997-05-20 Cisco Systems Inc. Computer system with cascaded peripheral component interconnect (PCI) buses
US5737545A (en) * 1996-05-21 1998-04-07 Vlsi Technology, Inc. Computer bus mastery system and method having a lock mechanism
JPH103447A (ja) 1996-06-18 1998-01-06 Matsushita Electric Ind Co Ltd バスブリッジ装置
US5748918A (en) * 1996-06-28 1998-05-05 Intel Corporation Method and apparatus for supporting two subtractive decode agents on the same bus in a computer system
US5864688A (en) * 1996-07-19 1999-01-26 Compaq Computer Corporation Apparatus and method for positively and subtractively decoding addresses on a bus
US5761454A (en) * 1996-08-27 1998-06-02 Vlsi Technology, Inc. Deadlock resolution methods and apparatus for interfacing concurrent and asynchronous buses
US5838932A (en) * 1996-12-23 1998-11-17 Compaq Computer Corporation Transparent PCI to PCI bridge with dynamic memory and I/O map programming

Also Published As

Publication number Publication date
EP1068573B1 (de) 2005-06-29
WO1999050753A1 (en) 1999-10-07
US6260093B1 (en) 2001-07-10
EP1068573A1 (de) 2001-01-17

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