DE69931882D1 - Schaltungsanordnung und Verfahren zum Implementieren autonomer sequentieller Logik - Google Patents

Schaltungsanordnung und Verfahren zum Implementieren autonomer sequentieller Logik

Info

Publication number
DE69931882D1
DE69931882D1 DE69931882T DE69931882T DE69931882D1 DE 69931882 D1 DE69931882 D1 DE 69931882D1 DE 69931882 T DE69931882 T DE 69931882T DE 69931882 T DE69931882 T DE 69931882T DE 69931882 D1 DE69931882 D1 DE 69931882D1
Authority
DE
Germany
Prior art keywords
logic
clock
logic functions
becoming
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69931882T
Other languages
English (en)
Other versions
DE69931882T2 (de
Inventor
Carro Fernando Incertis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69931882D1 publication Critical patent/DE69931882D1/de
Application granted granted Critical
Publication of DE69931882T2 publication Critical patent/DE69931882T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
DE69931882T 1998-12-29 1999-09-23 Schaltungsanordnung und Verfahren zum Implementieren autonomer sequentieller Logik Expired - Lifetime DE69931882T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98480106 1998-12-29
EP98480106 1998-12-29

Publications (2)

Publication Number Publication Date
DE69931882D1 true DE69931882D1 (de) 2006-07-27
DE69931882T2 DE69931882T2 (de) 2006-11-30

Family

ID=8235794

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69931882T Expired - Lifetime DE69931882T2 (de) 1998-12-29 1999-09-23 Schaltungsanordnung und Verfahren zum Implementieren autonomer sequentieller Logik

Country Status (4)

Country Link
US (1) US6515504B1 (de)
JP (1) JP2000278115A (de)
AT (1) ATE330361T1 (de)
DE (1) DE69931882T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867617B2 (en) * 2003-07-18 2005-03-15 Agere Systems Inc. Half-rate clock logic block and method for forming same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237701A (en) 1989-03-31 1993-08-17 Ampex Systems Corporation Data unpacker using a pack ratio control signal for unpacked parallel fixed m-bit width into parallel variable n-bit width word
US5289403A (en) 1991-07-08 1994-02-22 Hewlett-Packard Company Self-timed content addressable memory access mechanism with built-in margin test feature
US5387825A (en) 1992-08-20 1995-02-07 Texas Instruments Incorporated Glitch-eliminator circuit
JPH06334513A (ja) 1993-05-13 1994-12-02 Intel Corp データ処理装置
US5394407A (en) 1993-07-01 1995-02-28 Motorola, Inc. Method of transferring error correcting code and circuit therefor
CA2145363C (en) 1994-03-24 1999-07-13 Anthony Mark Jones Ram interface
US5565798A (en) 1995-08-21 1996-10-15 International Business Machines Corporation Self-timed control circuit for self-resetting logic circuitry
US5870411A (en) * 1996-12-13 1999-02-09 International Business Machines Corporation Method and system for testing self-timed circuitry
US6133758A (en) * 1998-05-29 2000-10-17 International Business Machines Corporation Selectable self-timed replacement for self-resetting circuitry
US6169422B1 (en) * 1998-07-20 2001-01-02 Sun Microsystems, Inc. Apparatus and methods for high throughput self-timed domino circuits
IT1301879B1 (it) * 1998-07-30 2000-07-07 St Microelectronics Srl Circuiteria a generatore di impulsi per temporizzare un dispositivodi memoria a basso consumo

Also Published As

Publication number Publication date
DE69931882T2 (de) 2006-11-30
JP2000278115A (ja) 2000-10-06
US6515504B1 (en) 2003-02-04
ATE330361T1 (de) 2006-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)