DE69933933D1 - Verfahren zur herstellung einer leiterbahnstruktur für eine integrierte schaltung - Google Patents

Verfahren zur herstellung einer leiterbahnstruktur für eine integrierte schaltung

Info

Publication number
DE69933933D1
DE69933933D1 DE69933933T DE69933933T DE69933933D1 DE 69933933 D1 DE69933933 D1 DE 69933933D1 DE 69933933 T DE69933933 T DE 69933933T DE 69933933 T DE69933933 T DE 69933933T DE 69933933 D1 DE69933933 D1 DE 69933933D1
Authority
DE
Germany
Prior art keywords
producing
integrated circuit
track structure
ladder track
ladder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69933933T
Other languages
English (en)
Other versions
DE69933933T2 (de
Inventor
Mehul Naik
Samuel Broydo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of DE69933933D1 publication Critical patent/DE69933933D1/de
Publication of DE69933933T2 publication Critical patent/DE69933933T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
DE69933933T 1998-07-23 1999-07-01 Verfahren zur herstellung einer leiterbahnstruktur für eine integrierte schaltung Expired - Fee Related DE69933933T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US122080 1993-09-15
US09/122,080 US6245662B1 (en) 1998-07-23 1998-07-23 Method of producing an interconnect structure for an integrated circuit
PCT/US1999/015073 WO2000005763A1 (en) 1998-07-23 1999-07-01 Method of producing an interconnect structure for an integrated circuit

Publications (2)

Publication Number Publication Date
DE69933933D1 true DE69933933D1 (de) 2006-12-21
DE69933933T2 DE69933933T2 (de) 2007-08-02

Family

ID=22400481

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69933933T Expired - Fee Related DE69933933T2 (de) 1998-07-23 1999-07-01 Verfahren zur herstellung einer leiterbahnstruktur für eine integrierte schaltung

Country Status (7)

Country Link
US (2) US6245662B1 (de)
EP (1) EP1101247B1 (de)
JP (1) JP2002521821A (de)
KR (1) KR100633979B1 (de)
DE (1) DE69933933T2 (de)
TW (1) TW457675B (de)
WO (1) WO2000005763A1 (de)

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Also Published As

Publication number Publication date
US20020048929A1 (en) 2002-04-25
DE69933933T2 (de) 2007-08-02
US6548396B2 (en) 2003-04-15
EP1101247B1 (de) 2006-11-08
JP2002521821A (ja) 2002-07-16
WO2000005763A9 (en) 2000-08-03
TW457675B (en) 2001-10-01
WO2000005763A1 (en) 2000-02-03
EP1101247A1 (de) 2001-05-23
KR100633979B1 (ko) 2006-10-16
KR20010072034A (ko) 2001-07-31
US6245662B1 (en) 2001-06-12

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