DE69937909D1 - Taktsynchrone Speicheranordnung mit Hochgeschwindigkeitszyklus - Google Patents

Taktsynchrone Speicheranordnung mit Hochgeschwindigkeitszyklus

Info

Publication number
DE69937909D1
DE69937909D1 DE69937909T DE69937909T DE69937909D1 DE 69937909 D1 DE69937909 D1 DE 69937909D1 DE 69937909 T DE69937909 T DE 69937909T DE 69937909 T DE69937909 T DE 69937909T DE 69937909 D1 DE69937909 D1 DE 69937909D1
Authority
DE
Germany
Prior art keywords
memory arrangement
clock synchronous
synchronous memory
speed cycle
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69937909T
Other languages
English (en)
Other versions
DE69937909T2 (de
Inventor
Haruki Toda
Kenji Tsuchida
Hitoshi Kuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69937909D1 publication Critical patent/DE69937909D1/de
Application granted granted Critical
Publication of DE69937909T2 publication Critical patent/DE69937909T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
DE69937909T 1998-07-17 1999-07-16 Taktsynchrone Speicheranordnung mit Hochgeschwindigkeitszyklus Expired - Lifetime DE69937909T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20345498 1998-07-17
JP20345498 1998-07-17

Publications (2)

Publication Number Publication Date
DE69937909D1 true DE69937909D1 (de) 2008-02-14
DE69937909T2 DE69937909T2 (de) 2008-12-24

Family

ID=16474398

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69937909T Expired - Lifetime DE69937909T2 (de) 1998-07-17 1999-07-16 Taktsynchrone Speicheranordnung mit Hochgeschwindigkeitszyklus
DE69938762T Expired - Lifetime DE69938762D1 (de) 1998-07-17 1999-07-16 Taktsynchrone Speicheranordnung mit Hochgeschwindigkeitszyklus

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69938762T Expired - Lifetime DE69938762D1 (de) 1998-07-17 1999-07-16 Taktsynchrone Speicheranordnung mit Hochgeschwindigkeitszyklus

Country Status (5)

Country Link
US (3) US6295231B1 (de)
EP (2) EP0973167B1 (de)
KR (2) KR100337768B1 (de)
DE (2) DE69937909T2 (de)
TW (1) TW439064B (de)

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JP4083944B2 (ja) 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
KR100699810B1 (ko) * 2000-08-05 2007-03-27 삼성전자주식회사 버스 효율을 향상시키는 반도체 메모리장치 및 메모리시스템
US6452869B1 (en) * 2001-02-26 2002-09-17 Advanced Micro Devices, Inc. Address broadcasting to a paged memory device to eliminate access latency penalty
US6549479B2 (en) 2001-06-29 2003-04-15 Micron Technology, Inc. Memory device and method having reduced-power self-refresh mode
US6985388B2 (en) * 2001-09-17 2006-01-10 Sandisk Corporation Dynamic column block selection
US7170802B2 (en) * 2003-12-31 2007-01-30 Sandisk Corporation Flexible and area efficient column redundancy for non-volatile memories
US6459648B1 (en) * 2001-10-13 2002-10-01 Josh N. Hogan Fault-tolerant address logic for solid state memory
US7076674B2 (en) * 2001-12-19 2006-07-11 Hewlett-Packard Development Company L.P. Portable computer having dual clock mode
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KR100525460B1 (ko) * 2003-05-23 2005-10-31 (주)실리콘세븐 2개의 메모리 블락 사이에 3개의 센스앰프를 가지며,인출과 기입 동작 구간이 분리되는 리프레쉬 동작을수행하는 에스램 호환 메모리 및 그 구동방법
JP3967693B2 (ja) * 2003-05-23 2007-08-29 株式会社東芝 半導体メモリ
US6928013B2 (en) * 2003-08-12 2005-08-09 Elite Semiconductor Memory Technology Inc. Timing control method for operating synchronous memory
US7379330B2 (en) * 2005-11-08 2008-05-27 Sandisk Corporation Retargetable memory cell redundancy methods
DE102008007004B4 (de) * 2008-01-31 2010-09-23 Advanced Micro Devices, Inc., Sunnyvale Integrierte Schaltung mit einem Speicher mit mehreren Speicherzellen mit synchronem Aufbau, die mit Taktausblendeeinheiten verbunden sind, sowie Verfahren zum Entwerfen einer solchen Schaltung
US8102705B2 (en) 2009-06-05 2012-01-24 Sandisk Technologies Inc. Structure and method for shuffling data within non-volatile memory devices
US8027195B2 (en) 2009-06-05 2011-09-27 SanDisk Technologies, Inc. Folding data stored in binary format into multi-state format within non-volatile memory devices
US7974124B2 (en) 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
US20110002169A1 (en) 2009-07-06 2011-01-06 Yan Li Bad Column Management with Bit Information in Non-Volatile Memory Systems
US8144512B2 (en) 2009-12-18 2012-03-27 Sandisk Technologies Inc. Data transfer flows for on-chip folding
US8725935B2 (en) 2009-12-18 2014-05-13 Sandisk Technologies Inc. Balanced performance for on-chip folding of non-volatile memories
US8468294B2 (en) 2009-12-18 2013-06-18 Sandisk Technologies Inc. Non-volatile memory with multi-gear control using on-chip folding of data
JP4947395B2 (ja) * 2010-01-07 2012-06-06 横河電機株式会社 半導体試験装置
US9342446B2 (en) 2011-03-29 2016-05-17 SanDisk Technologies, Inc. Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache
US8842473B2 (en) 2012-03-15 2014-09-23 Sandisk Technologies Inc. Techniques for accessing column selecting shift register with skipped entries in non-volatile memories
US8681548B2 (en) 2012-05-03 2014-03-25 Sandisk Technologies Inc. Column redundancy circuitry for non-volatile memory
US9076506B2 (en) 2012-09-28 2015-07-07 Sandisk Technologies Inc. Variable rate parallel to serial shift register
US8897080B2 (en) 2012-09-28 2014-11-25 Sandisk Technologies Inc. Variable rate serial to parallel shift register
US9490035B2 (en) 2012-09-28 2016-11-08 SanDisk Technologies, Inc. Centralized variable rate serializer and deserializer for bad column management
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
CN104637522B (zh) * 2014-12-26 2017-09-05 北京时代民芯科技有限公司 一种脉宽自适应的可配置存储器ip结构
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US10032524B2 (en) 2015-02-09 2018-07-24 Sandisk Technologies Llc Techniques for determining local interconnect defects
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US10373665B2 (en) * 2016-03-10 2019-08-06 Micron Technology, Inc. Parallel access techniques within memory sections through section independence
TWI751048B (zh) * 2021-03-04 2021-12-21 旺宏電子股份有限公司 記憶體裝置及其操作方法
US11482282B2 (en) 2021-03-04 2022-10-25 Macronix International Co., Ltd. Memory device and operation method thereof
CN117189649B (zh) * 2023-11-08 2024-01-05 永联科技(常熟)有限公司 一种风机矩阵控制方法及相关设备

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US5126973A (en) * 1990-02-14 1992-06-30 Texas Instruments Incorporated Redundancy scheme for eliminating defects in a memory device
JPH05189996A (ja) * 1991-09-05 1993-07-30 Hitachi Ltd 半導体記憶装置
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US5594704A (en) 1992-04-27 1997-01-14 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
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KR100391805B1 (ko) * 1994-03-22 2003-10-22 하퍼칩, 인코포레이티드 직접대체셀(cell)을갖는결함허용(faulttolerance)아키텍쳐자료처리시스템
JPH07334999A (ja) * 1994-06-07 1995-12-22 Hitachi Ltd 不揮発性半導体記憶装置及びデータプロセッサ
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JP4226686B2 (ja) 1998-05-07 2009-02-18 株式会社東芝 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
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Also Published As

Publication number Publication date
KR20010113566A (ko) 2001-12-28
EP1223583A3 (de) 2003-02-26
EP0973167B1 (de) 2008-05-21
US6480423B2 (en) 2002-11-12
US6295231B1 (en) 2001-09-25
US20030026163A1 (en) 2003-02-06
TW439064B (en) 2001-06-07
KR20000011760A (ko) 2000-02-25
EP1223583B1 (de) 2008-01-02
EP0973167A2 (de) 2000-01-19
DE69938762D1 (de) 2008-07-03
US6556507B2 (en) 2003-04-29
KR100337767B1 (ko) 2002-05-24
EP1223583A2 (de) 2002-07-17
US20010028579A1 (en) 2001-10-11
EP0973167A3 (de) 2000-05-17
KR100337768B1 (ko) 2002-05-24
DE69937909T2 (de) 2008-12-24

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Legal Events

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8364 No opposition during term of opposition