DE69941464D1 - Schnelles Ethernet mit einer Bitfolgefrequenz von 150 Mps - Google Patents

Schnelles Ethernet mit einer Bitfolgefrequenz von 150 Mps

Info

Publication number
DE69941464D1
DE69941464D1 DE69941464T DE69941464T DE69941464D1 DE 69941464 D1 DE69941464 D1 DE 69941464D1 DE 69941464 T DE69941464 T DE 69941464T DE 69941464 T DE69941464 T DE 69941464T DE 69941464 D1 DE69941464 D1 DE 69941464D1
Authority
DE
Germany
Prior art keywords
mps
bit rate
fast ethernet
ethernet
fast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69941464T
Other languages
English (en)
Inventor
Cypryan T Klish
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia International Inc
Original Assignee
Nvidia International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia International Inc filed Critical Nvidia International Inc
Application granted granted Critical
Publication of DE69941464D1 publication Critical patent/DE69941464D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00—Multiplex communications
    • Y10S370/901—Wide area network
    • Y10S370/902—Packet switching
    • Y10S370/903—Osi compliant network
    • Y10S370/907—Synchronous optical network, SONET
DE69941464T 1998-02-19 1999-02-12 Schnelles Ethernet mit einer Bitfolgefrequenz von 150 Mps Expired - Lifetime DE69941464D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/025,923 US6014708A (en) 1998-02-19 1998-02-19 Adaptor and method for mapping a fast ethernet payload input signal to a synchronous payload envelope, as well as a clock selector for use therewith

Publications (1)

Publication Number Publication Date
DE69941464D1 true DE69941464D1 (de) 2009-11-12

Family

ID=21828811

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69941464T Expired - Lifetime DE69941464D1 (de) 1998-02-19 1999-02-12 Schnelles Ethernet mit einer Bitfolgefrequenz von 150 Mps

Country Status (4)

Country Link
US (1) US6014708A (de)
EP (1) EP0944290B1 (de)
CA (1) CA2261225A1 (de)
DE (1) DE69941464D1 (de)

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Also Published As

Publication number Publication date
CA2261225A1 (en) 1999-08-19
EP0944290A2 (de) 1999-09-22
EP0944290A3 (de) 2004-03-03
EP0944290B1 (de) 2009-09-30
US6014708A (en) 2000-01-11

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Legal Events

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