DE96928129T1 - Universeller programmierbarer mediaprozessor - Google Patents
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Abstract
Ausführungseinheit,
die bei der vereinigten Ausführung
mehrerer Mediendatenströme
im Wesentlichen einen Spitzendatendurchsatz aufrechterhalten kann,
wobei die Ausführungseinheit
einen Datenpfad besitzt, mit:
einer Mehrfachgenauigkeits-Arithmetikeinheit, die mit dem Datenpfad gekoppelt ist, wobei die Mehrfachgenauigkeits-Arithmetikeinheit auf der Grundlage der elementaren Breite von von dem Datenpfad empfangenen Daten eine dynamische Partitionierung ausführen kann;
einem Schalter, der mit dem Datenpfad gekoppelt ist und programmierbar ist, um von dem Datenpfad empfangene Daten zu manipulieren, wobei der Schalter Datenströme für den Datenpfad bereitstellt; und
einem erweiterten mathematischen Element, das mit dem Datenpfad gekoppelt ist und programmierbar ist, um zusätzliche mathematische Operationen im Wesentlichen bei Spitzendatendurchsatz zu implementieren.
einer Mehrfachgenauigkeits-Arithmetikeinheit, die mit dem Datenpfad gekoppelt ist, wobei die Mehrfachgenauigkeits-Arithmetikeinheit auf der Grundlage der elementaren Breite von von dem Datenpfad empfangenen Daten eine dynamische Partitionierung ausführen kann;
einem Schalter, der mit dem Datenpfad gekoppelt ist und programmierbar ist, um von dem Datenpfad empfangene Daten zu manipulieren, wobei der Schalter Datenströme für den Datenpfad bereitstellt; und
einem erweiterten mathematischen Element, das mit dem Datenpfad gekoppelt ist und programmierbar ist, um zusätzliche mathematische Operationen im Wesentlichen bei Spitzendatendurchsatz zu implementieren.
Claims (70)
- Ausführungseinheit, die bei der vereinigten Ausführung mehrerer Mediendatenströme im Wesentlichen einen Spitzendatendurchsatz aufrechterhalten kann, wobei die Ausführungseinheit einen Datenpfad besitzt, mit: einer Mehrfachgenauigkeits-Arithmetikeinheit, die mit dem Datenpfad gekoppelt ist, wobei die Mehrfachgenauigkeits-Arithmetikeinheit auf der Grundlage der elementaren Breite von von dem Datenpfad empfangenen Daten eine dynamische Partitionierung ausführen kann; einem Schalter, der mit dem Datenpfad gekoppelt ist und programmierbar ist, um von dem Datenpfad empfangene Daten zu manipulieren, wobei der Schalter Datenströme für den Datenpfad bereitstellt; und einem erweiterten mathematischen Element, das mit dem Datenpfad gekoppelt ist und programmierbar ist, um zusätzliche mathematische Operationen im Wesentlichen bei Spitzendatendurchsatz zu implementieren.
- Ausführungseinheit nach Anspruch 1, bei der die Mehrfachgenauigkeits-Ausführungseinheit konfigurierbar ist, um die Daten in Komponentensymbole verschiedener Größen zu unterteilen, die Komponentensymbole anhand von Befehlen zu analysieren und die Komponentensymbole für die Kommunikation über den Datenpfad zu resynthetisieren.
- Ausführungseinheit nach Anspruch 2, bei der die Mehrfachgenauigkeits-Ausführungseinheit betreibbar ist, um eindeutige Operationen an jedem Komponentensymbol auszuführen.
- Ausführungseinheit nach Anspruch 2, bei der das mathematische Element betreibbar ist, um an den Symbolen Operationen finiter Gruppen, finiter Felder, finiter Ringe und eines Tabellennachschlagens auszuführen.
- Ausführungseinheit nach Anspruch 1, bei der die Arithmetikeinheit programmierbar ist, um mathematische Boolsche, Ganzzahl- und Gleitkommaoperationen auszuführen.
- Ausführungseinheit nach Anspruch 5, bei der die durch die Arithmetikeinheit ausgeführten Operationen auf verschiedenen Genauigkeitsniveaus ausgeführt werden können.
- Ausführungseinheit nach Anspruch 1, bei der die Manipulation der Daten das Kopieren, das Verschieben und das Ändern der Größe der Daten umfasst.
- Ausführungseinheit nach Anspruch 1, die ferner eine Steuerung für die Maximierung der Nutzung der Ausführungseinheit durch Ausführen von Operationen mit Spitzendatenbreite des Datenpfades umfasst.
- Ausführungseinheit nach Anspruch 2, bei der die Größen der Komponentensymbole zusammenpassen.
- Ausführungseinheit mit einem Datenpfad, die umfasst: wenigstens eine Registerdatei, die mit dem Datenpfad gekoppelt ist; eine Mehrfachgenauigkeits-Arithmetikeinheit, die mit dem Datenpfad gekoppelt ist, wobei die Mehrfachgenauigkeits-Arithmetikeinheit anhand der elementaren Breite von von dem Datenpfad empfangenen Daten eine dynamische Partitionierung ausführen kann; einen Schalter, der mit dem Datenpfad gekoppelt ist und programmierbar ist, um von dem Datenpfad empfangene Daten zu manipulieren, wobei der Schalter Datenströme für den Datenpfad bereitstellt; und ein erweitertes mathematisches Element, das mit dem Datenpfad gekoppelt ist und programmierbar ist, um zusätzliche mathematische Operationen im Wesentlichen bei Spitzendatendurchsatz zu implementieren.
- Ausführungseinheit, die einen Datenpfad aufweist und umfasst: eine Mehrfachgenauigkeits-Arithmetikeinheit, die mit dem Datenpfad gekoppelt ist, wobei die Mehrfachgenauigkeits-Arithmetikeinheit auf der Grundlage der elementaren Breite von von dem Datenpfad empfangenen Daten eine dynamische Partitionierung ausführen kann; Mittel, die mit dem Datenpfad gekoppelt sind, um von dem Datenpfad empfangene Daten zu manipulieren, wobei die Mittel zum Manipulieren von Daten programmierbar sind und ein Datensignal für den Datenpfad bereitstellen; und ein erweitertes mathematisches Element, das mit dem Datenpfad gekoppelt ist und programmierbar ist, um zusätzliche mathematische Operationen im Wesentlichen bei Spitzendatendurchsatz zu implementieren.
- Universeller programmierbarer Medienprozessor mit einem Befehlspfad und einem Datenpfad, um mehrere Mediendatenströme digital zu verarbeiten, der umfasst: eine externe Schnittstelle mit hoher Bandbreite, die so betreibbar ist, dass sie mehrere Daten mit unterschiedlichen Größen von einer externen Quelle empfängt und die empfangenen Daten über den Datenpfad mit einer Rate kommuniziert, die im Wesentlichen die Spitzenoperation des Medienprozessors aufrechterhält; wenigstens eine Registerdatei, die konfigurierbar ist, um Daten von dem Datenpfad zu empfangen und zu speichern und um die gespeicherten Daten zu dem Datenpfad zu kommunizieren; und eine Mehrfachgenauigkeits-Ausführungseinheit, die mit dem Datenpfad gekoppelt ist, wobei die Mehrfachgenauigkeits-Ausführungseinheit konfigurierbar ist, um von dem Datenpfad empfangene Daten zu partitionieren, um die elementare Symbolgröße der mehreren Mediendatenströme zu berücksichtigen, und programmierbar ist, um an den Daten Operationen vorzunehmen, um einen vereinheitlichten Symbolausgang auf dem Datenpfad zu erzeugen.
- Medienprozessor nach Anspruch 12, bei dem die Ausführungseinheit dynamisch konfigurierbar ist, um von dem Datenpfad empfangene Daten zu partitionieren.
- Medienprozessor nach Anspruch 12, der ferner umfasst: Mittel zum Bewegen von Daten zwischen Registern und einem Speicher durch Ausführen von Lade- und Speicherungsoperationen und zum Koordinieren der gemeinsamen Nutzung von Daten zwischen mehreren Tasks durch Ausführen von Synchronisationsoperationen auf der Grundlage von Befehlen und Daten, die von der Ausführungseinheit empfangen werden; Mittel zum sicheren Steuern der Ausführungssequenz durch Ausführen von Verzweigungs- und Gateway-Operationen auf der Grundlage von Befehlen und von Daten, die von der Ausführungseinheit empfangen werden; und eine Speichermanagementeinheit, wobei die Speichermanagementeinheit betreibbar ist, um Daten und Befehlen für eine rechtzeitige und sichere Kommunikation über den Datenpfad und den Befehlspfad wiederzugewinnen.
- Medienprozessor nach Anspruch 14, der umfasst: einen kombinierten Befehls-Cache und -Puffer, wobei der kombinierte Befehls-Cache und -Puffer zwischen Cache-Raum und Puffer-Raum dynamisch zugewiesen wird, um eine Echtzeitausführung mehrerer Medienbefehlsströme zu gewährleisten; und einen kombinierten Daten-Cache und -Puffer, wobei der kombinierte Daten-Cache und -Puffer zwischen Cache-Raum und Puffer-Raum dynamisch zugewiesen wird, um eine Echtzeitantwort für mehrere Mediendatenströme zu gewährleisten.
- Medienprozessor nach Anspruch 15, bei dem die Echtzeitausführung durch dynamisches Zuweisen von Befehlspuffer-Raum zu den kleinsten und am häufigsten ausgeführten Blöcken von Medienbefehlen gewährleistet wird.
- Medienprozessor nach Anspruch 15, bei dem die Echtzeitantwort durch dynamisches Zuweisen von Datenpuffer-Raum auf Arbeitssätze, die am kleinsten sind und auf die am häufigsten zugegriffen wird, gewährleistet wird.
- Medienprozessor nach Anspruch 12, bei dem die Mediendatenströme Nyquist-abgetastete Eingänge und Ausgänge umfassen.
- Medienprozessor nach Anspruch 12, bei dem die Mediendatenströme von einem Standardcomputerspeicher und von E/A-Schnittstellen stammen.
- Medienprozessor nach Anspruch 12, bei dem die Mehrfachgenauigkeits-Ausführungseinheit konfigurierbar ist, um die Daten in Komponentensymbole mit unterschiedlichen Größe zu unterteilen, die Komponentensymbole auf der Grundlage von Befehlen zu analysieren und die Komponentensymbole für eine Kommunikation über den Datenpfad zu resynthetisieren.
- Medienprozessor nach Anspruch 12, bei dem die mehreren Mediendatenströme Darstellungs-Medieninformationen, Übertragungs-Medieninformationen und Speicherungs-Medieninformationen umfassen.
- Medienprozessor nach Anspruch 21, bei dem die Darstellungs-Medieninformationen Audio-, Video-, Bild- und Graphikinformationen umfassen.
- Medienprozessor nach Anspruch 21, bei dem die Übertragungs-Medieninformationen Funk- und Netz-Datenübertragungen umfassen.
- Medienprozessor nach Anspruch 21, bei dem die Speicherungs-Medieninformationen Daten umfassen, die in beweglichen Medien und in Festkörperspeichermedien codiert sind.
- Medienprozessor nach Anspruch 12, bei dem die Breite des Datenpfades wenigstens 128 Bits beträgt.
- Medienprozessor nach Anspruch 12, bei dem die Mehrfachgenauigkeits-Ausführungseinheit eine dynamisch partitionierbare Arithmetikeinheit, einen durch Register steuerbaren Kreuzschienenschalter und ein erweitertes mathematisches Element umfasst.
- Medienprozessor nach Anspruch 24, bei dem der durch Register steuerbare Kreuzschienenschalter ein Benes-Netzdesign hat.
- Medienprozessor nach Anspruch 26, bei dem der durch Register steuerbare Kreuzschienenschalter programmierbar ist und betreibbar ist, um Symbole zu manipulieren.
- Medienprozessor nach Anspruch 22, bei dem das erweiterte mathematische Element betreibbar ist, um Operationen finiter Gruppen, finiter Felder, finiter Ringe und eines Tabellennachschlagens an den Symbolen auszuführen.
- Medienprozessor nach Anspruch 12, der ferner einen Satz von im Voraus definierten Befehlen, auf die ein Anwender zugreifen kann, umfasst.
- Medienprozessor nach Anspruch 13, bei dem die Mittel zum Ausführen von Lade-, Speicherungs- und Synchronisationsoperationen und die Mittel zum Ausführen von Verzweigungs- und Gateway-Operationen einen Satz von im Voraus definierten Befehlen, auf die ein Anwender zugreifen kann, umfassen.
- Medienprozessor nach Anspruch 31, bei dem die im Voraus definierten Befehle kombinierbar sind, um zusammengesetzte Funktionen auf den mehreren Mediendatenströmen zu implementieren.
- Prozessorschnittstelle mit hoher Bandbreite zum Empfangen und Senden eines Medienstroms, die umfasst: einen Datenpfad, wobei der Datenpfad betreibbar ist, um Medieninformationen mit Dauerspitzenraten zu übertragen; mehrere Speicher-Controller, wobei die mehreren Speicher-Controller mit dem Datenpfad in Reihe geschaltet sind, um gespeicherte Medieninformationen zu und von dem Datenpfad zu kommunizieren; und mehrere Speicherelemente, die mit jedem der mehreren Speicher-Controller parallelgeschaltet sind, wobei die mehreren Speicherelemente dem Speichern und Wiedergewinnen der Medieninformationen dienen.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 33, bei der der Datenpfad mehrere Datenpfade, die einen Datenkanal mit hoher Bandbreite bilden, umfasst.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 34, bei der der Datenkanal mit hoher Bandbreite unidirektional ist.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 33, die ferner einen universellen programmierbaren Medienprozessor umfasst, der mit dem Datenkanal mit hoher Bandbreite gekoppelt ist, um Medieninformationen im Wesentlichen mit Spitzenraten zu empfangen, zu verarbeiten und zu senden.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 33, bei der die Spitzenrate der Operation wenigstens ein Gigabyte an Informationen pro Sekunde von Punkt zu Punkt umfasst.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 33, bei der die mehreren Speicher-Controller jeweils eine gepaarte Verbindung umfassen, die zwischen jedem Speicher-Controller angeordnet ist, wobei die gepaarten Verbindungen jeweils dem Senden und Empfangen mehrerer Bits von Daten dienen und differentielle Dateneingänge und -ausgänge sowie ein differentielles Taktsignal haben.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 38, bei der die gepaarte Verbindung ferner einen digitalen Abweichungskalibrator umfasst, um die mehreren Datenbits in Bezug auf das differentielle Taktsignal einzustellen, um eine Abweichung zwischen den Daten zu beseitigen.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 38, bei der die gepaarte Verbindung ferner eine Phasenverriegelungsschleife umfasst, um einen Jitter in dem zwischen gepaarten Verbindungen übertragenen differentiellen Taktsignal zu beseitigen.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 38, bei der die mehreren Bits acht Datenbits umfassen.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 38, bei der die gepaarten Verbindungen jeweils ferner Abschlusswiderstände umfassen, um angepasste Impedanzen für jede gepaarte Verbindung zu bilden.
- Prozessorschnittstelle mit hoher Bandbreite nach Anspruch 34, bei der der Datenkanal mit hoher Bandbreite mehrere parallele Datenkanäle mit hoher Bandbreite umfasst.
- System für eine vereinigte Medienverarbeitung, das umfasst: mehrere universelle Medienprozessoren, wobei jeder Medienprozessor mit gehaltenen Spitzendatenraten betreibbar ist und eine dynamisch partitionierte Ausführungseinheit sowie eine Schnittstelle mit hoher Bandbreite besitzt, wobei die Schnittstelle mit hoher Bandbreite mit einem externen Speicher und mit Eingangs/Ausgangs-Elementen gekoppelt ist, um Daten von bzw. zu dem Medienprozessor im Wesentlichen bei Spitzenraten zu empfangen bzw. zu senden; ein bidirektionales Kommunikationsgewebe, wobei die mehreren Medienprozessoren mit dem bidirektionalen Kommunikationsgewebe gekoppelt sind, um wenigstens einen Medienstrom, der Darstellungs-, Übertragungs- und Speicherungs-Medieninformationen enthält, zu senden und zu empfangen.
- System nach Anspruch 44, bei dem das bidirektionale Kommunikationsgewebe ein faseroptisches Netz umfasst.
- System nach Anspruch 44, bei dem das bidirektionale Kommunikationsgewebe ein heterogenes Netz umfasst.
- System nach Anspruch 44, bei dem das bidirektionale Kommunikationsgewebe ein Koaxialkabelnetz umfasst.
- System nach Anspruch 44, bei dem das bidirektionale Kommunikationsgewebe ein drahtloses Netz umfasst.
- System nach Anspruch 44, bei dem eine Untermenge der mehreren Medienprozessoren Netzserver umfasst.
- System nach Anspruch 44, bei dem die mehreren Medienprozessoren durch Herunterladen von Programminformationen über das bidirektionale Kommunikationsgewebe programmierbar sind.
- System nach Anspruch 44, bei dem jeder der mehreren Medienprozessoren auf eine im Leerlauf befindliche Ausführungseinheit eines weiteren Medienprozessors in der Weise einer gemeinsamen Nutzung zugreifen kann, um Darstellungs-, Übertragungs- und Speicherungs-Medieninformationen im Wesentlichen mit Spitzendatenraten effizient zu verarbeiten.
- System nach Anspruch 44, bei dem jeder Medienprozessor ferner einen für ihn bestimmten Speicher umfasst und bei dem jeder der mehreren Medienprozessoren irgendeinen nicht verwendeten Abschnitt des für einen weiteren Medienprozessor bestimmten Speichers in der Weise einer gemeinsamen Nutzung verwenden kann, um Darstellungs-, Übertragungs- und Speicherungs-Medieninformationen im Wesentlichen mit Spitzendatenraten effizient zu speichern und wiederzugewinnen.
- System aus parallelen Multiprozessoren, das bei der vereinigten Ausführung mehrerer Medienströme im Wesentlichen einen Spitzendatendurchsatz aufrechterhält, wobei das System einen Datenpfad besitzt und umfasst: wenigstens eine externe Schnittstelle mit hoher Bandbreite, wobei die wenigstens eine externe Schnittstelle mit hoher Bandbreite mit dem Datenpfad gekoppelt ist und betreibbar ist, um mehrere Daten mit unterschiedlichen Größen von einer externen Quelle zu empfangen und um die empfangenen Daten mit einer Rate zu kommunizieren, die im Wesentlichen eine Spitzenoperation des Systems aus parallelen Multiprozessoren aufrechterhält; mehrere Registerdateien, wobei jede Registerdatei wenigstens ein universelles Register besitzt, das mit dem Datenpfad gekoppelt ist und betreibbar ist, um einen Arbeitssatz von Mediendaten zu speichern; und wenigstens eine Mehrfachgenauigkeits-Ausführungseinheit, die mit dem Datenpfad gekoppelt ist, wobei die wenigstens eine Mehrfachgenauigkeits-Ausführungseinheit dynamisch konfigurierbar ist, um unter Berücksichtigung der elementaren Symbolgröße der mehreren Medienströme Daten innerhalb eines Arbeitssatzes von Mediendaten, die von dem Datenpfad empfangen werden, zu partitionieren, und programmierbar ist, um parallel an Arbeitssätzen von Daten zu arbeiten, die in den mehreren Registerdateien gespeichert sind, um einen vereinigten Symbolausgang für jede Registerdatei zu erzeugen.
- System aus parallelen Multiprozessoren nach Anspruch 53, bei dem die wenigstens eine Ausführungseinheit auf eine Round-Robin-Weise hin und her wechselt, um an Daten zu arbeiten, die in den mehreren Registerdateien gespeichert sind.
- System aus mehreren Multiprozessoren nach Anspruch 53, das ferner eine Befehls-Vorauslesepipeline umfasst.
- System aus parallelen Multiprozessoren nach Anspruch 55, bei dem die Befehls-Vorauslesepipeline eine Superstring-Pipeline umfasst.
- System aus parallelen Multiprozessoren nach Anspruch 55, bei dem die Befehls-Vorauslesepipeline eine Superspring-Pipeline umfasst.
- System aus parallelen Multiprozessoren nach Anspruch 53, das ferner eine Daten-Vorauslesepipeline umfasst.
- System aus parallelen Multiprozessoren nach Anspruch 58, bei dem die Daten-Vorauslesepipeline eine Superstring-Pipeline umfasst.
- System aus parallelen Multiprozessoren nach Anspruch 58, bei dem die Daten-Vorauslesepipeline eine Superspring-Pipeline umfasst.
- System aus parallelen Multiprozessoren nach Anspruch 53, die ferner eine Anforderungseinrichtung, eine Antworteinrichtung und einen Transponder-Dämon umfasst.
- Verfahren zum Verarbeiten vereinigter Ströme von Mediendaten, das die folgenden Schritte umfasst: Empfangen eines Stroms vereinigter Mediendaten einschließlich Darstellungs-, Übertragungs- und Speicherungsinformationen; dynamisches Partitionieren des vereinigten Stroms von Mediendaten in Komponentenfelder aus wenigstens einem Bit auf der Grundlage der elementaren Symbolgröße von empfangenen Daten; und Verarbeiten des vereinigten Stroms von Mediendaten im Wesentlichen bei Spitzenoperation.
- Verfahren nach Anspruch 62, bei dem der Schritt des Verarbeitens des vereinigten Stroms von Mediendaten die folgenden Schritte umfasst: Speichern des Stroms vereinigter Mediendaten in einer allgemeinen Registerdatei; Ausführen von Mehrfachgenauigkeits-Arithmetikoperationen an dem gespeicherten Strom vereinigter Mediendaten auf der Grundlage programmierter Befehle, wobei die Mehrfachgenauigkeits-Arithmetikoperationen mathematische Boolsche, Ganzzahl- und Gleitkommaoperationen umfassen; Manipulieren der Komponentenfelder vereinigter Mediendaten auf der Grundlage programmierter Befehle, die Kopier-, Verschiebungs- und Größenänderungsoperationen implementieren; und Ausführen von mathematischen Mehrfachgenauigkeitsoperationen an dem gespeicherten Strom vereinigter Mediendaten auf der Grundlage programmierter Befehle, wobei die mathematischen Operationen Operationen finiter Gruppen, finiter Felder, finiter Ringe und eines Tabellennachschlagens umfassen.
- Verfahren nach Anspruch 63, das ferner die folgenden Schritte umfasst: Vorauslesen von Befehlen und Daten, um Befehls- und Daten-Pipelines zu füllen; Ausführen von Speichermanagementoperationen, um Befehle und Daten aus einem externen Speicher wiederzugewinnen; Speichern von Befehlen und von Daten in Befehls- und Daten-Caches/Puffern; und dynamisches Zuweisen von Pufferspeicher in den Befehls- und Daten-Caches/Puffern, um eine Echtzeitausführung zu gewährleisten.
- Verfahren nach Anspruch 63, das ferner den Schritt des Bereitstellens einer Gruppe von Befehlen zum Verarbeiten des Stroms vereinigter Mediendaten umfasst, wobei die Gruppe von Befehlen Lade-, Speicherungs-, Synchronisations-, Verzweigungs- und Gateway-Befehle umfasst.
- Verfahren nach Anspruch 65, das ferner den Schritt des Programmierens einer Folge aus wenigstens einem Befehl aus der Gruppe von Befehlen umfasst.
- Verfahren zum Erzielen von Kommunikationen mit hoher Bandbreite zwischen einem universellen Medienprozessor und externen Vorrichtungen, das die folgenden Schritte umfasst: Vorsehen einer Schnittstelle mit hoher Bandbreite, die zwischen dem Medienprozessor und den externen Vorrichtungen angeordnet ist, wobei die Schnittstelle mit hoher Bandbreite wenigstens ein unidirektionales Kanalpaar mit einem Eingangs- und einem Ausgangsanschluss umfasst; und Senden und Empfangen mehrerer Mediendatenströme, die Komponentenfelder mit unterschiedlichen Größen enthalten, zwischen dem Medienprozessor und den externen Vorrichtungen mit einer Rate, die im Wesentlichen einen Spitzendatendurchsatz bei dem Medienprozessor aufrechterhält.
- Verfahren nach Anspruch 67, bei dem der Schritt des Bereitstellens einer Schnittstelle mit hoher Bandbreite ferner das Bereitstellen mehrerer externer Vorrichtungen umfasst, wobei die mehreren externen Vorrichtungen mit dem wenigstens einen unidirektionalen Kanalpaar in Reihe geschaltet sind.
- Verfahren nach Anspruch 67, bei dem der Schritt des Vorsehens einer Schnittstelle mit hoher Bandbreite ferner das Vorsehen mehrerer paralleler unidirektionaler Kanalpaare umfasst.
- Verfahren zum Verarbeiten von Strömen von Mediendaten, das die folgenden Schritte umfasst: Vorsehen eines bidirektionalen Kommunikationsgewebes, um wenigstens einen Strom vereinigter Mediendaten zu senden und zu empfangen, wobei der wenigstens eine Strom vereinigter Mediendaten Darstellungs-, Übertragungs- und Speicherungsinformationen umfasst; und Vorsehen wenigstens eines programmierbaren Medienprozessors in dem Kommunikationsnetz, wobei der wenigstens eine programmierbare Medienprozessor den wenigstens einen Strom vereinigter Mediendaten über das bidirektionale Kommunikationsgewebe empfängt, verarbeitet und sendet.
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Families Citing this family (381)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7380092B2 (en) * | 2002-06-28 | 2008-05-27 | Rambus Inc. | Memory device and system having a variable depth write buffer and preload method |
US7187572B2 (en) | 2002-06-28 | 2007-03-06 | Rambus Inc. | Early read after write operation memory device, system and method |
US6389010B1 (en) * | 1995-10-05 | 2002-05-14 | Intermec Ip Corp. | Hierarchical data collection network supporting packetized voice communications among wireless terminals and telephones |
US7301541B2 (en) * | 1995-08-16 | 2007-11-27 | Microunity Systems Engineering, Inc. | Programmable processor and method with wide operations |
US6295599B1 (en) * | 1995-08-16 | 2001-09-25 | Microunity Systems Engineering | System and method for providing a wide operand architecture |
US6643765B1 (en) * | 1995-08-16 | 2003-11-04 | Microunity Systems Engineering, Inc. | Programmable processor with group floating point operations |
US5742840A (en) * | 1995-08-16 | 1998-04-21 | Microunity Systems Engineering, Inc. | General purpose, multiple precision parallel operation, programmable media processor |
US5953241A (en) * | 1995-08-16 | 1999-09-14 | Microunity Engeering Systems, Inc. | Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction |
US7395298B2 (en) * | 1995-08-31 | 2008-07-01 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed data |
US6385634B1 (en) | 1995-08-31 | 2002-05-07 | Intel Corporation | Method for performing multiply-add operations on packed data |
EP0767544A3 (de) | 1995-10-04 | 2002-02-27 | Interuniversitair Micro-Elektronica Centrum Vzw | Programmierbare Modem unter verwendung von Spreizspektrumnachrichtenübertragung |
US6101590A (en) * | 1995-10-10 | 2000-08-08 | Micro Unity Systems Engineering, Inc. | Virtual memory system with local and global virtual address translation |
US6035369A (en) | 1995-10-19 | 2000-03-07 | Rambus Inc. | Method and apparatus for providing a memory with write enable information |
US6470405B2 (en) | 1995-10-19 | 2002-10-22 | Rambus Inc. | Protocol for communication with dynamic memory |
US6810449B1 (en) | 1995-10-19 | 2004-10-26 | Rambus, Inc. | Protocol for communication with dynamic memory |
US7099949B1 (en) * | 1995-10-23 | 2006-08-29 | Imec Vzw | Interprocess communication protocol system |
US6212566B1 (en) * | 1996-01-26 | 2001-04-03 | Imec | Interprocess communication protocol system modem |
US6792523B1 (en) * | 1995-12-19 | 2004-09-14 | Intel Corporation | Processor with instructions that operate on different data types stored in the same single logical register file |
US5940859A (en) * | 1995-12-19 | 1999-08-17 | Intel Corporation | Emptying packed data state during execution of packed data instructions |
US5864754A (en) * | 1996-02-05 | 1999-01-26 | Hotto; Robert | System and method for radio signal reconstruction using signal processor |
US8280334B2 (en) | 1996-02-05 | 2012-10-02 | American Radio Llc | System and method for radio signal reconstruction using signal processor |
US7099316B1 (en) * | 1996-02-29 | 2006-08-29 | Tomich John L | Photonic home area network |
US6209071B1 (en) * | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
JPH1049356A (ja) * | 1996-07-31 | 1998-02-20 | Matsushita Electric Ind Co Ltd | メディアフロー制御システム |
JP3560423B2 (ja) * | 1996-09-17 | 2004-09-02 | 松下電器産業株式会社 | パケット送受信装置及びパケット受信装置 |
US6016307A (en) | 1996-10-31 | 2000-01-18 | Connect One, Inc. | Multi-protocol telecommunications routing optimization |
US6473404B1 (en) * | 1998-11-24 | 2002-10-29 | Connect One, Inc. | Multi-protocol telecommunications routing optimization |
US6230245B1 (en) | 1997-02-11 | 2001-05-08 | Micron Technology, Inc. | Method and apparatus for generating a variable sequence of memory device command signals |
US6175894B1 (en) | 1997-03-05 | 2001-01-16 | Micron Technology, Inc. | Memory device command buffer apparatus and method and memory devices and computer systems using same |
US6359882B1 (en) | 1997-04-01 | 2002-03-19 | Yipes Communications, Inc. | Method and apparatus for transmitting data |
US6101255A (en) * | 1997-04-30 | 2000-08-08 | Motorola, Inc. | Programmable cryptographic processing system and method |
US6611537B1 (en) * | 1997-05-30 | 2003-08-26 | Centillium Communications, Inc. | Synchronous network for digital media streams |
US5996043A (en) | 1997-06-13 | 1999-11-30 | Micron Technology, Inc. | Two step memory device command buffer apparatus and method and memory devices and computer systems using same |
US6484244B1 (en) | 1997-06-17 | 2002-11-19 | Micron Technology, Inc. | Method and system for storing and processing multiple memory commands |
US6266379B1 (en) | 1997-06-20 | 2001-07-24 | Massachusetts Institute Of Technology | Digital transmitter with equalization |
US6009264A (en) * | 1997-08-28 | 1999-12-28 | Ncr Corporation | Node coordination using a channel object and point-to-point protocol |
US6870419B1 (en) | 1997-08-29 | 2005-03-22 | Rambus Inc. | Memory system including a memory device having a controlled output driver characteristic |
US6067594A (en) * | 1997-09-26 | 2000-05-23 | Rambus, Inc. | High frequency bus system |
US5864703A (en) | 1997-10-09 | 1999-01-26 | Mips Technologies, Inc. | Method for providing extended precision in SIMD vector arithmetic operations |
US7197625B1 (en) | 1997-10-09 | 2007-03-27 | Mips Technologies, Inc. | Alignment and ordering of vector elements for single instruction multiple data processing |
AU9693398A (en) * | 1997-10-10 | 1999-05-03 | Rambus Incorporated | Apparatus and method for pipelined memory operations |
US6401167B1 (en) * | 1997-10-10 | 2002-06-04 | Rambus Incorporated | High performance cost optimized memory |
US6343352B1 (en) * | 1997-10-10 | 2002-01-29 | Rambus Inc. | Method and apparatus for two step memory write operations |
US6757746B2 (en) | 1997-10-14 | 2004-06-29 | Alacritech, Inc. | Obtaining a destination address so that a network interface device can write network data without headers directly into host memory |
US6427173B1 (en) | 1997-10-14 | 2002-07-30 | Alacritech, Inc. | Intelligent network interfaced device and system for accelerated communication |
US7089326B2 (en) * | 1997-10-14 | 2006-08-08 | Alacritech, Inc. | Fast-path processing for receiving data on TCP connection offload devices |
US7284070B2 (en) * | 1997-10-14 | 2007-10-16 | Alacritech, Inc. | TCP offload network interface device |
US6658480B2 (en) | 1997-10-14 | 2003-12-02 | Alacritech, Inc. | Intelligent network interface system and method for accelerated protocol processing |
US6226680B1 (en) * | 1997-10-14 | 2001-05-01 | Alacritech, Inc. | Intelligent network interface system method for protocol processing |
US6434620B1 (en) * | 1998-08-27 | 2002-08-13 | Alacritech, Inc. | TCP/IP offload network interface device |
US6697868B2 (en) | 2000-02-28 | 2004-02-24 | Alacritech, Inc. | Protocol processing stack for use with intelligent network interface device |
US6427171B1 (en) | 1997-10-14 | 2002-07-30 | Alacritech, Inc. | Protocol processing stack for use with intelligent network interface device |
US7185266B2 (en) | 2003-02-12 | 2007-02-27 | Alacritech, Inc. | Network interface device for error detection using partial CRCS of variable length message portions |
US7133940B2 (en) * | 1997-10-14 | 2006-11-07 | Alacritech, Inc. | Network interface device employing a DMA command queue |
US7174393B2 (en) | 2000-12-26 | 2007-02-06 | Alacritech, Inc. | TCP/IP offload network interface device |
US6591302B2 (en) | 1997-10-14 | 2003-07-08 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding to a TCP connection |
US6389479B1 (en) | 1997-10-14 | 2002-05-14 | Alacritech, Inc. | Intelligent network interface device and system for accelerated communication |
US6687758B2 (en) * | 2001-03-07 | 2004-02-03 | Alacritech, Inc. | Port aggregation for network connections that are offloaded to network interface devices |
US7076568B2 (en) * | 1997-10-14 | 2006-07-11 | Alacritech, Inc. | Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket |
US8539112B2 (en) | 1997-10-14 | 2013-09-17 | Alacritech, Inc. | TCP/IP offload device |
US7167927B2 (en) * | 1997-10-14 | 2007-01-23 | Alacritech, Inc. | TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism |
US7237036B2 (en) * | 1997-10-14 | 2007-06-26 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding a TCP connection |
US6470415B1 (en) | 1999-10-13 | 2002-10-22 | Alacritech, Inc. | Queue system involving SRAM head, SRAM tail and DRAM body |
US8782199B2 (en) | 1997-10-14 | 2014-07-15 | A-Tech Llc | Parsing a packet header |
US6807581B1 (en) | 2000-09-29 | 2004-10-19 | Alacritech, Inc. | Intelligent network storage interface system |
US8621101B1 (en) | 2000-09-29 | 2013-12-31 | Alacritech, Inc. | Intelligent network storage interface device |
US7042898B2 (en) | 1997-10-14 | 2006-05-09 | Alacritech, Inc. | Reducing delays associated with inserting a checksum into a network message |
US6353927B1 (en) * | 1997-10-14 | 2002-03-05 | Lucent Technologies Inc. | Data download technique into installed memory |
US6202119B1 (en) * | 1997-12-19 | 2001-03-13 | Micron Technology, Inc. | Method and system for processing pipelined memory commands |
US6279045B1 (en) * | 1997-12-29 | 2001-08-21 | Kawasaki Steel Corporation | Multimedia interface having a multimedia processor and a field programmable gate array |
US6041404A (en) | 1998-03-31 | 2000-03-21 | Intel Corporation | Dual function system and method for shuffling packed data elements |
US7392275B2 (en) * | 1998-03-31 | 2008-06-24 | Intel Corporation | Method and apparatus for performing efficient transformations with horizontal addition and subtraction |
US6230257B1 (en) * | 1998-03-31 | 2001-05-08 | Intel Corporation | Method and apparatus for staggering execution of a single packed data instruction using the same circuit |
US6230253B1 (en) * | 1998-03-31 | 2001-05-08 | Intel Corporation | Executing partial-width packed data instructions |
US6625638B1 (en) * | 1998-04-30 | 2003-09-23 | International Business Machines Corporation | Management of a logical partition that supports different types of processors |
US7100020B1 (en) * | 1998-05-08 | 2006-08-29 | Freescale Semiconductor, Inc. | Digital communications processor |
FR2778762B1 (fr) * | 1998-05-14 | 2000-12-08 | Sgs Thomson Microelectronics | Interface de microprocesseur avec une memoire externe optimisee par un systeme de decodage anticipe |
US6480876B2 (en) * | 1998-05-28 | 2002-11-12 | Compaq Information Technologies Group, L.P. | System for integrating task and data parallelism in dynamic applications |
US6675189B2 (en) * | 1998-05-28 | 2004-01-06 | Hewlett-Packard Development Company, L.P. | System for learning and applying integrated task and data parallel strategies in dynamic applications |
US6650327B1 (en) | 1998-06-16 | 2003-11-18 | Silicon Graphics, Inc. | Display system having floating point rasterization and floating point framebuffering |
US6175905B1 (en) * | 1998-07-30 | 2001-01-16 | Micron Technology, Inc. | Method and system for bypassing pipelines in a pipelined memory command generator |
WO2000008552A1 (en) * | 1998-08-06 | 2000-02-17 | Koninklijke Philips Electronics N.V. | Data processor and method of processing data |
EP2241968B1 (de) * | 1998-08-24 | 2012-06-27 | MicroUnity Systems Engineering, Inc. | System mit breiter Operandenarchitektur und Verfahren |
US6378060B1 (en) | 1998-08-24 | 2002-04-23 | Microunity Systems Engineering, Inc. | System to implement a cross-bar switch of a broadband processor |
US7932911B2 (en) | 1998-08-24 | 2011-04-26 | Microunity Systems Engineering, Inc. | Processor for executing switch and translate instructions requiring wide operands |
JP4933693B2 (ja) * | 1998-08-24 | 2012-05-16 | マイクロユニティ システムズ エンジニアリング インコーポレイテッド | ワイド・オペランド・アーキテクチャを含むシステムおよび方法 |
US6178488B1 (en) | 1998-08-27 | 2001-01-23 | Micron Technology, Inc. | Method and apparatus for processing pipelined memory commands |
US7664883B2 (en) | 1998-08-28 | 2010-02-16 | Alacritech, Inc. | Network interface device that fast-path processes solicited session layer read commands |
US6418518B1 (en) * | 1998-09-18 | 2002-07-09 | National Semiconductor Corporation | Decoupled address and data access to an SDRAM |
JP3164083B2 (ja) * | 1998-10-20 | 2001-05-08 | 日本電気株式会社 | 半導体集積回路 |
JP3374967B2 (ja) * | 1998-10-26 | 2003-02-10 | 日本電気株式会社 | 半導体集積回路 |
US6041400A (en) * | 1998-10-26 | 2000-03-21 | Sony Corporation | Distributed extensible processing architecture for digital signal processing applications |
US6747984B1 (en) | 1998-12-18 | 2004-06-08 | Lsi Logic Corporation | Method and apparatus for transmitting Data |
EP1236090A4 (de) * | 1999-02-12 | 2002-09-04 | Microunity Systems Eng | System und verfahren zum implementieren eines cross-barschalters eines breitbandprozessors |
EP1031994B1 (de) * | 1999-02-23 | 2002-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Speicherschaltungen mit eingebautem Selbsttest |
US7243133B2 (en) * | 1999-03-30 | 2007-07-10 | Sedna Patent Services, Llc | Method and apparatus for reducing latency in an interactive information distribution system |
EP1046998A1 (de) * | 1999-04-22 | 2000-10-25 | Texas Instruments Incorporated | Digitale Signalprozessoren mit virtueller Addressierung |
US7188168B1 (en) | 1999-04-30 | 2007-03-06 | Pmc-Sierra, Inc. | Method and apparatus for grammatical packet classifier |
US7185081B1 (en) | 1999-04-30 | 2007-02-27 | Pmc-Sierra, Inc. | Method and apparatus for programmable lexical packet classifier |
EP1059781B1 (de) * | 1999-05-06 | 2007-09-05 | Siemens Aktiengesellschaft | Kommunikationseinrichtung mit Mitteln zur Echtzeitverarbeitung von zu übertragenden Nutzdaten |
US6463548B1 (en) * | 1999-05-10 | 2002-10-08 | Compaq Information Technologies Group, L.P. | Method and apparatus to enforce clocked circuit functionality at reduced frequency without limiting peak performance |
US6643777B1 (en) * | 1999-05-14 | 2003-11-04 | Acquis Technology, Inc. | Data security method and device for computer modules |
US6718415B1 (en) | 1999-05-14 | 2004-04-06 | Acqis Technology, Inc. | Computer system and method including console housing multiple computer modules having independent processing units, mass storage devices, and graphics controllers |
US6853651B1 (en) | 1999-06-17 | 2005-02-08 | Cingular Wireless Ii, Inc. | System and method for outbox-capable wireless transmission |
US6598166B1 (en) * | 1999-08-18 | 2003-07-22 | Sun Microsystems, Inc. | Microprocessor in which logic changes during execution |
US20020071321A1 (en) * | 2000-11-29 | 2002-06-13 | International Business Machines Corporation | System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories |
US6460120B1 (en) * | 1999-08-27 | 2002-10-01 | International Business Machines Corporation | Network processor, memory organization and methods |
US6321282B1 (en) | 1999-10-19 | 2001-11-20 | Rambus Inc. | Apparatus and method for topography dependent signaling |
US7051130B1 (en) | 1999-10-19 | 2006-05-23 | Rambus Inc. | Integrated circuit device that stores a value representative of a drive strength setting |
US6646953B1 (en) * | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US6643752B1 (en) | 1999-12-09 | 2003-11-04 | Rambus Inc. | Transceiver with latency alignment circuitry |
US7793076B1 (en) * | 1999-12-17 | 2010-09-07 | Intel Corporation | Digital signals processor having a plurality of independent dedicated processors |
US6847365B1 (en) * | 2000-01-03 | 2005-01-25 | Genesis Microchip Inc. | Systems and methods for efficient processing of multimedia data |
US7363422B2 (en) * | 2000-01-05 | 2008-04-22 | Rambus Inc. | Configurable width buffered module |
US7266634B2 (en) * | 2000-01-05 | 2007-09-04 | Rambus Inc. | Configurable width buffered module having flyby elements |
US7356639B2 (en) * | 2000-01-05 | 2008-04-08 | Rambus Inc. | Configurable width buffered module having a bypass circuit |
US7404032B2 (en) * | 2000-01-05 | 2008-07-22 | Rambus Inc. | Configurable width buffered module having switch elements |
US6502161B1 (en) | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US20050010737A1 (en) * | 2000-01-05 | 2005-01-13 | Fred Ware | Configurable width buffered module having splitter elements |
US7010642B2 (en) * | 2000-01-05 | 2006-03-07 | Rambus Inc. | System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices |
US20010028662A1 (en) * | 2000-01-18 | 2001-10-11 | Hunt Paul M. | Method and system of real-time optimization and implementation of content and advertising programming decisions for broadcasts and narrowcasts |
US7082552B2 (en) | 2000-02-08 | 2006-07-25 | Mips Tech Inc | Functional validation of a packet management unit |
US7065096B2 (en) | 2000-06-23 | 2006-06-20 | Mips Technologies, Inc. | Method for allocating memory space for limited packet head and/or tail growth |
US7155516B2 (en) | 2000-02-08 | 2006-12-26 | Mips Technologies, Inc. | Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory |
US7058064B2 (en) * | 2000-02-08 | 2006-06-06 | Mips Technologies, Inc. | Queueing system for processors in packet routing operations |
US7165257B2 (en) * | 2000-02-08 | 2007-01-16 | Mips Technologies, Inc. | Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts |
US20010052053A1 (en) * | 2000-02-08 | 2001-12-13 | Mario Nemirovsky | Stream processing unit for a multi-streaming processor |
US7649901B2 (en) | 2000-02-08 | 2010-01-19 | Mips Technologies, Inc. | Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing |
US7139901B2 (en) * | 2000-02-08 | 2006-11-21 | Mips Technologies, Inc. | Extended instruction set for packet processing applications |
US7032226B1 (en) * | 2000-06-30 | 2006-04-18 | Mips Technologies, Inc. | Methods and apparatus for managing a buffer of events in the background |
US7042887B2 (en) | 2000-02-08 | 2006-05-09 | Mips Technologies, Inc. | Method and apparatus for non-speculative pre-fetch operation in data packet processing |
US7076630B2 (en) * | 2000-02-08 | 2006-07-11 | Mips Tech Inc | Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management |
US7058065B2 (en) * | 2000-02-08 | 2006-06-06 | Mips Tech Inc | Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing |
US7502876B1 (en) | 2000-06-23 | 2009-03-10 | Mips Technologies, Inc. | Background memory manager that determines if data structures fits in memory with memory state transactions map |
CN1184575C (zh) * | 2000-04-07 | 2005-01-12 | 北京华诺信息技术有限公司 | 一种用软件定义的电缆网络系统及方法 |
US7024461B1 (en) * | 2000-04-28 | 2006-04-04 | Nortel Networks Limited | Session initiation protocol enabled set-top device |
US7010788B1 (en) | 2000-05-19 | 2006-03-07 | Hewlett-Packard Development Company, L.P. | System for computing the optimal static schedule using the stored task execution costs with recent schedule execution costs |
US6751746B1 (en) * | 2000-07-31 | 2004-06-15 | Cisco Technology, Inc. | Method and apparatus for uninterrupted packet transfer using replication over disjoint paths |
US7287009B1 (en) * | 2000-09-14 | 2007-10-23 | Raanan Liebermann | System and a method for carrying out personal and business transactions |
US8019901B2 (en) | 2000-09-29 | 2011-09-13 | Alacritech, Inc. | Intelligent network storage interface system |
US6720074B2 (en) * | 2000-10-26 | 2004-04-13 | Inframat Corporation | Insulator coated magnetic nanoparticulate composites with reduced core loss and method of manufacture thereof |
GB0028079D0 (en) * | 2000-11-17 | 2001-01-03 | Imperial College | System and method |
US6839792B2 (en) * | 2000-12-15 | 2005-01-04 | Innovative Concepts, Inc. | Data modem |
US6760772B2 (en) | 2000-12-15 | 2004-07-06 | Qualcomm, Inc. | Generating and implementing a communication protocol and interface for high data rate signal transfer |
US7191244B2 (en) * | 2001-01-19 | 2007-03-13 | Streamworks Technologies, Inc. | System and method for routing media |
US9674575B2 (en) | 2001-01-19 | 2017-06-06 | SITO Mobile R&D IP, LLC | System and method for routing media |
US20040025186A1 (en) * | 2001-01-19 | 2004-02-05 | Jennings Charles A. | System and method for managing media |
US7054949B2 (en) * | 2001-01-19 | 2006-05-30 | World Streaming Network, Inc. | System and method for streaming media |
US7155601B2 (en) | 2001-02-14 | 2006-12-26 | Intel Corporation | Multi-element operand sub-portion shuffle instruction execution |
US7162621B2 (en) | 2001-02-21 | 2007-01-09 | Mips Technologies, Inc. | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration |
US7711763B2 (en) | 2001-02-21 | 2010-05-04 | Mips Technologies, Inc. | Microprocessor instructions for performing polynomial arithmetic operations |
US7123307B1 (en) * | 2001-02-23 | 2006-10-17 | Silicon Image, Inc. | Clock jitter limiting scheme in video transmission through multiple stages |
US6877079B2 (en) * | 2001-03-06 | 2005-04-05 | Samsung Electronics Co., Ltd. | Memory system having point-to-point bus configuration |
US8391039B2 (en) | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US20020194340A1 (en) * | 2001-06-16 | 2002-12-19 | Ebstyne Bryan D. | Enterprise storage resource management system |
US6891845B2 (en) * | 2001-06-29 | 2005-05-10 | Intel Corporation | Method and apparatus for adapting to a clock rate transition in a communications network using idles |
US8576527B2 (en) | 2001-07-06 | 2013-11-05 | Schweitzer Engineering Laboratoris Inc | Apparatus, system, and method for creating one or more slow-speed communications channels utilizing a real-time communication channel |
US8111492B2 (en) * | 2001-07-06 | 2012-02-07 | Schweitzer Engineering Laboratories, Inc. | Apparatus, system, and method for creating one or more slow-speed communications channels utilizing a real-time communication channel |
US7543067B2 (en) * | 2001-08-01 | 2009-06-02 | Canon Kabushiki Kaisha | Flexible secure network data transfer and messaging |
US8812706B1 (en) | 2001-09-06 | 2014-08-19 | Qualcomm Incorporated | Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system |
US20030065803A1 (en) * | 2001-09-28 | 2003-04-03 | Koninklijke Philips Electronics N. V. | Intelligent delivery method for streamed content |
US7032215B2 (en) * | 2001-10-11 | 2006-04-18 | Intel Corporation | Method and system for type demotion of expressions and variables by bitwise constant propagation |
US7430578B2 (en) * | 2001-10-29 | 2008-09-30 | Intel Corporation | Method and apparatus for performing multiply-add operations on packed byte data |
US7154533B2 (en) * | 2001-10-30 | 2006-12-26 | Tandberg Telecom As | System and method for monitoring and diagnosis of video network performance |
US7009978B2 (en) | 2001-12-18 | 2006-03-07 | Nortel Networks Limited | Communications interface for providing a plurality of communication channels to a single port on a processor |
US20030121835A1 (en) * | 2001-12-31 | 2003-07-03 | Peter Quartararo | Apparatus for and method of sieving biocompatible adsorbent beaded polymers |
US7260217B1 (en) * | 2002-03-01 | 2007-08-21 | Cavium Networks, Inc. | Speculative execution for data ciphering operations |
US6839709B2 (en) * | 2002-03-19 | 2005-01-04 | Intel Corporation | Layered resource structure and method |
US7496689B2 (en) | 2002-04-22 | 2009-02-24 | Alacritech, Inc. | TCP/IP offload device |
US7543087B2 (en) | 2002-04-22 | 2009-06-02 | Alacritech, Inc. | Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device |
US7124163B2 (en) | 2002-05-24 | 2006-10-17 | Convedia Corporation | Data server |
US7047383B2 (en) | 2002-07-11 | 2006-05-16 | Intel Corporation | Byte swap operation for a 64 bit operand |
CN1692343A (zh) * | 2002-07-22 | 2005-11-02 | 株式会社瑞萨科技 | 半导体集成电路器件、数据处理系统及存储系统 |
JP4085255B2 (ja) * | 2002-09-26 | 2008-05-14 | 富士フイルム株式会社 | デジタルカメラ及び画像通信方法 |
US7337241B2 (en) * | 2002-09-27 | 2008-02-26 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding to a TCP connection |
US7191241B2 (en) * | 2002-09-27 | 2007-03-13 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding to a TCP connection |
US9088474B2 (en) * | 2002-10-08 | 2015-07-21 | Broadcom Corporation | Advanced processor with interfacing messaging network to a CPU |
US7334086B2 (en) * | 2002-10-08 | 2008-02-19 | Rmi Corporation | Advanced processor with system on a chip interconnect technology |
US6842848B2 (en) * | 2002-10-11 | 2005-01-11 | Sandbridge Technologies, Inc. | Method and apparatus for token triggered multithreading |
US20040088262A1 (en) * | 2002-11-06 | 2004-05-06 | Alacritech, Inc. | Enabling an enhanced function of an electronic device |
US7362697B2 (en) * | 2003-01-09 | 2008-04-22 | International Business Machines Corporation | Self-healing chip-to-chip interface |
WO2004072872A1 (en) * | 2003-02-12 | 2004-08-26 | Research In Motion Limited | An apparatus and methods for managing data used by a mobile device |
US7290192B2 (en) * | 2003-03-31 | 2007-10-30 | Advantest Corporation | Test apparatus and test method for testing plurality of devices in parallel |
US7119549B2 (en) * | 2003-02-25 | 2006-10-10 | Rambus Inc. | Output calibrator with dynamic precision |
US7400586B2 (en) * | 2003-02-25 | 2008-07-15 | Avaya Technology Corp. | Collaborative remote communication circuit diagnostic tool |
US7324555B1 (en) | 2003-03-20 | 2008-01-29 | Infovalue Computing, Inc. | Streaming while fetching broadband video objects using heterogeneous and dynamic optimized segmentation size |
US6922770B2 (en) * | 2003-05-27 | 2005-07-26 | Sony Corporation | Memory controller providing dynamic arbitration of memory commands |
BRPI0410885B1 (pt) | 2003-06-02 | 2018-01-30 | Qualcomm Incorporated | Gerar e implementar um protocolo de sinal e interface para taxas de dados mais altas |
US7194581B2 (en) * | 2003-06-03 | 2007-03-20 | Intel Corporation | Memory channel with hot add/remove |
US7127629B2 (en) * | 2003-06-03 | 2006-10-24 | Intel Corporation | Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal |
US7200787B2 (en) * | 2003-06-03 | 2007-04-03 | Intel Corporation | Memory channel utilizing permuting status patterns |
US7340537B2 (en) * | 2003-06-04 | 2008-03-04 | Intel Corporation | Memory channel with redundant presence detect |
US7165153B2 (en) | 2003-06-04 | 2007-01-16 | Intel Corporation | Memory channel with unidirectional links |
US8171331B2 (en) | 2003-06-04 | 2012-05-01 | Intel Corporation | Memory channel having deskew separate from redrive |
US7386768B2 (en) | 2003-06-05 | 2008-06-10 | Intel Corporation | Memory channel with bit lane fail-over |
US7047385B1 (en) * | 2003-06-16 | 2006-05-16 | Cisco Technology, Inc. | High-speed memory for use in networking systems |
US20070169022A1 (en) * | 2003-06-18 | 2007-07-19 | Jones Anthony M | Processor having multiple instruction sources and execution modes |
US7912218B2 (en) * | 2003-07-04 | 2011-03-22 | Nxp B.V. | Method of broadcasting multimedia content via distribution network |
US7130963B2 (en) * | 2003-07-16 | 2006-10-31 | International Business Machines Corp. | System and method for instruction memory storage and processing based on backwards branch control information |
AU2004300958A1 (en) | 2003-08-13 | 2005-02-24 | Qualcomm, Incorporated | A signal interface for higher data rates |
JP3984206B2 (ja) * | 2003-09-02 | 2007-10-03 | 株式会社東芝 | マイクロプロセッサー及び映像音声システム |
ATE424685T1 (de) | 2003-09-10 | 2009-03-15 | Qualcomm Inc | Schnittstelle für hohe datenrate |
CN1894931A (zh) | 2003-10-15 | 2007-01-10 | 高通股份有限公司 | 高数据速率接口 |
EP1692842A1 (de) * | 2003-10-29 | 2006-08-23 | Qualcomm Incorporated | Schnittstelle für hohe datenrate |
TWI381686B (zh) | 2003-11-12 | 2013-01-01 | Qualcomm Inc | 具有改良的鏈路控制之高資料速率介面 |
US7143207B2 (en) * | 2003-11-14 | 2006-11-28 | Intel Corporation | Data accumulation between data path having redrive circuit and memory device |
US7219294B2 (en) * | 2003-11-14 | 2007-05-15 | Intel Corporation | Early CRC delivery for partial frame |
US7447953B2 (en) | 2003-11-14 | 2008-11-04 | Intel Corporation | Lane testing with variable mapping |
BRPI0416895A (pt) | 2003-11-25 | 2007-03-06 | Qualcomm Inc | interface de alta taxa de dados com sincronização de link melhorada |
US6996070B2 (en) * | 2003-12-05 | 2006-02-07 | Alacritech, Inc. | TCP/IP offload device with reduced sequential processing |
CA2731265A1 (en) | 2003-12-08 | 2005-06-23 | Qualcomm Incorporated | High data rate interface with improved link synchronization |
WO2005066805A1 (ja) * | 2003-12-26 | 2005-07-21 | Fujitsu Limited | 共通メモリアクセス方法及びそれを用いたマルチプロセッサ・システム |
EP1733537A1 (de) | 2004-03-10 | 2006-12-20 | Qualcomm, Incorporated | Schnittstellenvorrichtung und -verfahren mit hoher datenrate |
WO2005091593A1 (en) | 2004-03-17 | 2005-09-29 | Qualcomm Incorporated | High data rate interface apparatus and method |
BRPI0509147A (pt) | 2004-03-24 | 2007-09-11 | Qualcomm Inc | equipamentos e método para interface de alta taxa de dados |
WO2005093654A2 (en) | 2004-03-25 | 2005-10-06 | Fatih Ozluturk | Method and apparatus to correct digital image blur due to motion of subject or imaging device |
US7586951B2 (en) * | 2004-04-27 | 2009-09-08 | Intel Corporation | Method, apparatus, and system for idle state definition for power management |
US7221613B2 (en) * | 2004-05-26 | 2007-05-22 | Freescale Semiconductor, Inc. | Memory with serial input/output terminals for address and data and method therefor |
US7212423B2 (en) * | 2004-05-31 | 2007-05-01 | Intel Corporation | Memory agent core clock aligned to lane |
US8650304B2 (en) | 2004-06-04 | 2014-02-11 | Qualcomm Incorporated | Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system |
KR100914420B1 (ko) | 2004-06-04 | 2009-08-27 | 퀄컴 인코포레이티드 | 고 데이터 레이트 인터페이스 장치 및 방법 |
US7383399B2 (en) * | 2004-06-30 | 2008-06-03 | Intel Corporation | Method and apparatus for memory compression |
US20060004953A1 (en) * | 2004-06-30 | 2006-01-05 | Vogt Pete D | Method and apparatus for increased memory bandwidth |
US7200693B2 (en) * | 2004-08-27 | 2007-04-03 | Micron Technology, Inc. | Memory system and method having unidirectional data buses |
US7941585B2 (en) * | 2004-09-10 | 2011-05-10 | Cavium Networks, Inc. | Local scratchpad and data caching system |
WO2006031551A2 (en) | 2004-09-10 | 2006-03-23 | Cavium Networks | Selective replication of data structure |
US7594081B2 (en) | 2004-09-10 | 2009-09-22 | Cavium Networks, Inc. | Direct access to low-latency memory |
US7301831B2 (en) | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
US8248939B1 (en) | 2004-10-08 | 2012-08-21 | Alacritech, Inc. | Transferring control of TCP connections between hierarchy of processing mechanisms |
US8699330B2 (en) | 2004-11-24 | 2014-04-15 | Qualcomm Incorporated | Systems and methods for digital data transmission rate control |
US8873584B2 (en) | 2004-11-24 | 2014-10-28 | Qualcomm Incorporated | Digital data interface device |
US8667363B2 (en) | 2004-11-24 | 2014-03-04 | Qualcomm Incorporated | Systems and methods for implementing cyclic redundancy checks |
US8723705B2 (en) | 2004-11-24 | 2014-05-13 | Qualcomm Incorporated | Low output skew double data rate serial encoder |
US8692838B2 (en) | 2004-11-24 | 2014-04-08 | Qualcomm Incorporated | Methods and systems for updating a buffer |
US8539119B2 (en) | 2004-11-24 | 2013-09-17 | Qualcomm Incorporated | Methods and apparatus for exchanging messages having a digital data interface device message format |
US8667249B2 (en) | 2004-12-22 | 2014-03-04 | Intel Corporation | Systems and methods exchanging data between processors through concurrent shared memory |
US7490215B2 (en) * | 2004-12-22 | 2009-02-10 | Intel Corporation | Media memory system and method for providing concurrent memory access to a plurality of processors through separate translation table information |
US8279886B2 (en) * | 2004-12-30 | 2012-10-02 | Intel Corporation | Dataport and methods thereof |
US20060179273A1 (en) * | 2005-02-09 | 2006-08-10 | Advanced Micro Devices, Inc. | Data processor adapted for efficient digital signal processing and method therefor |
JP4673408B2 (ja) * | 2005-06-03 | 2011-04-20 | エヌエックスピー ビー ヴィ | データ処理システム及び少なくとも1つの排他的資源の利用をスケジューリングする方法 |
US9459960B2 (en) | 2005-06-03 | 2016-10-04 | Rambus Inc. | Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation |
US7831882B2 (en) | 2005-06-03 | 2010-11-09 | Rambus Inc. | Memory system with error detection and retry modes of operation |
US7562271B2 (en) | 2005-09-26 | 2009-07-14 | Rambus Inc. | Memory system topologies including a buffer device and an integrated circuit memory device |
US7464225B2 (en) * | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US11328764B2 (en) | 2005-09-26 | 2022-05-10 | Rambus Inc. | Memory system topologies including a memory die stack |
EP1932158A4 (de) | 2005-09-30 | 2008-10-15 | Mosaid Technologies Inc | Speicher mit ausgangssteuerung |
US7652922B2 (en) | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
US20070076502A1 (en) | 2005-09-30 | 2007-04-05 | Pyeon Hong B | Daisy chain cascading devices |
US11948629B2 (en) | 2005-09-30 | 2024-04-02 | Mosaid Technologies Incorporated | Non-volatile memory device with concurrent bank operations |
US7747833B2 (en) * | 2005-09-30 | 2010-06-29 | Mosaid Technologies Incorporated | Independent link and bank selection |
US8730069B2 (en) | 2005-11-23 | 2014-05-20 | Qualcomm Incorporated | Double data rate serial encoder |
US8692839B2 (en) | 2005-11-23 | 2014-04-08 | Qualcomm Incorporated | Methods and systems for updating a buffer |
US7738500B1 (en) | 2005-12-14 | 2010-06-15 | Alacritech, Inc. | TCP timestamp synchronization for network connections that are offloaded to network interface devices |
US7516349B2 (en) * | 2005-12-29 | 2009-04-07 | Intel Corporation | Synchronized memory channels with unidirectional links |
US7562285B2 (en) | 2006-01-11 | 2009-07-14 | Rambus Inc. | Unidirectional error code transfer for a bidirectional data link |
US20070201367A1 (en) * | 2006-02-27 | 2007-08-30 | Cisco Technology, Inc. | System and method for interworking H.323 flow control with SIP |
US7404055B2 (en) | 2006-03-28 | 2008-07-22 | Intel Corporation | Memory transfer with early access to critical portion |
US8352805B2 (en) | 2006-05-18 | 2013-01-08 | Rambus Inc. | Memory error detection |
EP2487794A3 (de) * | 2006-08-22 | 2013-02-13 | Mosaid Technologies Incorporated | Modulare Befehlsstruktur für einen Speicher und Speichersystem |
US20080052429A1 (en) * | 2006-08-28 | 2008-02-28 | Tableau, Llc | Off-board computational resources |
US20080126472A1 (en) * | 2006-08-28 | 2008-05-29 | Tableau, Llc | Computer communication |
US20080052525A1 (en) * | 2006-08-28 | 2008-02-28 | Tableau, Llc | Password recovery |
US20080052490A1 (en) * | 2006-08-28 | 2008-02-28 | Tableau, Llc | Computational resource array |
US20080059672A1 (en) * | 2006-08-30 | 2008-03-06 | Irish John D | Methods and Apparatus for Scheduling Prioritized Commands on a Bus |
US8271746B1 (en) * | 2006-11-03 | 2012-09-18 | Nvidia Corporation | Tiering of linear clients |
US8223736B2 (en) * | 2007-01-31 | 2012-07-17 | Broadcom Corporation | Apparatus for managing frequency use |
US9486703B2 (en) * | 2007-01-31 | 2016-11-08 | Broadcom Corporation | Mobile communication device with game application for use in conjunction with a remote mobile communication device and methods for use therewith |
US8238275B2 (en) * | 2007-01-31 | 2012-08-07 | Broadcom Corporation | IC with MMW transceiver communications |
US8121541B2 (en) * | 2007-01-31 | 2012-02-21 | Broadcom Corporation | Integrated circuit with intra-chip and extra-chip RF communication |
US20090011832A1 (en) * | 2007-01-31 | 2009-01-08 | Broadcom Corporation | Mobile communication device with game application for display on a remote monitor and methods for use therewith |
US8239650B2 (en) * | 2007-01-31 | 2012-08-07 | Broadcom Corporation | Wirelessly configurable memory device addressing |
US8289944B2 (en) * | 2007-01-31 | 2012-10-16 | Broadcom Corporation | Apparatus for configuration of wireless operation |
US8200156B2 (en) * | 2007-01-31 | 2012-06-12 | Broadcom Corporation | Apparatus for allocation of wireless resources |
US20090017910A1 (en) * | 2007-06-22 | 2009-01-15 | Broadcom Corporation | Position and motion tracking of an object |
US8254319B2 (en) * | 2007-01-31 | 2012-08-28 | Broadcom Corporation | Wireless programmable logic device |
US8125950B2 (en) * | 2007-01-31 | 2012-02-28 | Broadcom Corporation | Apparatus for wirelessly managing resources |
US8438322B2 (en) * | 2007-01-31 | 2013-05-07 | Broadcom Corporation | Processing module with millimeter wave transceiver interconnection |
US8204075B2 (en) * | 2007-01-31 | 2012-06-19 | Broadcom Corporation | Inter-device wireless communication for intra-device communications |
US20080320293A1 (en) * | 2007-01-31 | 2008-12-25 | Broadcom Corporation | Configurable processing core |
US20090197641A1 (en) * | 2008-02-06 | 2009-08-06 | Broadcom Corporation | Computing device with handheld and extended computing units |
US8280303B2 (en) * | 2007-01-31 | 2012-10-02 | Broadcom Corporation | Distributed digital signal processor |
US8116294B2 (en) * | 2007-01-31 | 2012-02-14 | Broadcom Corporation | RF bus controller |
US8122202B2 (en) * | 2007-02-16 | 2012-02-21 | Peter Gillingham | Reduced pin count interface |
EP2109862A4 (de) * | 2007-02-16 | 2010-08-04 | Mosaid Technologies Inc | Halbleiterbauelement und verfahren zur veringerung des stromverbrauchs in einem system mit verbundenen bauelementen |
CN101617371B (zh) | 2007-02-16 | 2014-03-26 | 莫塞德技术公司 | 具有多个外部电源的非易失性半导体存储器 |
US7957951B2 (en) * | 2007-03-16 | 2011-06-07 | Robert Bosch Gmbh | Address translation system for use in a simulation environment |
US8489825B2 (en) * | 2007-04-16 | 2013-07-16 | St-Ericsson Sa | Method of storing data, method of loading data and signal processor |
US7889578B2 (en) * | 2007-10-17 | 2011-02-15 | Mosaid Technologies Incorporated | Single-strobe operation of memory devices |
US8825939B2 (en) * | 2007-12-12 | 2014-09-02 | Conversant Intellectual Property Management Inc. | Semiconductor memory device suitable for interconnection in a ring topology |
US8399973B2 (en) | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
CN101903953B (zh) | 2007-12-21 | 2013-12-18 | 莫塞德技术公司 | 具有功率节省特性的非易失性半导体存储器设备 |
US8291248B2 (en) | 2007-12-21 | 2012-10-16 | Mosaid Technologies Incorporated | Non-volatile semiconductor memory device with power saving feature |
US8078836B2 (en) * | 2007-12-30 | 2011-12-13 | Intel Corporation | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits |
US8594110B2 (en) * | 2008-01-11 | 2013-11-26 | Mosaid Technologies Incorporated | Ring-of-clusters network topologies |
US8893126B2 (en) * | 2008-02-01 | 2014-11-18 | International Business Machines Corporation | Binding a process to a special purpose processing element having characteristics of a processor |
US8175646B2 (en) * | 2008-02-06 | 2012-05-08 | Broadcom Corporation | Networking of multiple mode handheld computing unit |
US20090198798A1 (en) * | 2008-02-06 | 2009-08-06 | Broadcom Corporation | Handheld computing unit back-up system |
US8717974B2 (en) * | 2008-02-06 | 2014-05-06 | Broadcom Corporation | Handheld computing unit coordination of femtocell AP functions |
US8117370B2 (en) * | 2008-02-06 | 2012-02-14 | Broadcom Corporation | IC for handheld computing unit of a computing device |
US8064952B2 (en) * | 2008-02-06 | 2011-11-22 | Broadcom Corporation | A/V control for a computing device with handheld and extended computing units |
US8195928B2 (en) * | 2008-02-06 | 2012-06-05 | Broadcom Corporation | Handheld computing unit with merged mode |
US8972594B2 (en) * | 2008-02-11 | 2015-03-03 | Microsoft Corporation | Media mix wiring protocol for media control |
US8539513B1 (en) | 2008-04-01 | 2013-09-17 | Alacritech, Inc. | Accelerating data transfer in a virtual computer system with tightly coupled TCP connections |
US8430750B2 (en) * | 2008-05-22 | 2013-04-30 | Broadcom Corporation | Video gaming device with image identification |
US8139390B2 (en) * | 2008-07-08 | 2012-03-20 | Mosaid Technologies Incorporated | Mixed data rates in memory devices and systems |
US8341286B1 (en) | 2008-07-31 | 2012-12-25 | Alacritech, Inc. | TCP offload send optimization |
ES2373810T3 (es) * | 2008-08-09 | 2012-02-08 | Saffron Digital Limited | Procesamiento y suministro de datos de video. |
US10236032B2 (en) * | 2008-09-18 | 2019-03-19 | Novachips Canada Inc. | Mass data storage system with non-volatile memory modules |
US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
US8161313B2 (en) * | 2008-09-30 | 2012-04-17 | Mosaid Technologies Incorporated | Serial-connected memory system with duty cycle correction |
US8181056B2 (en) * | 2008-09-30 | 2012-05-15 | Mosaid Technologies Incorporated | Serial-connected memory system with output delay adjustment |
CN101715145B (zh) * | 2008-10-06 | 2012-08-15 | 辉达公司 | 利用级联存储器评估处理能力的设备和方法 |
US8134852B2 (en) * | 2008-10-14 | 2012-03-13 | Mosaid Technologies Incorporated | Bridge device architecture for connecting discrete memory devices to a system |
US7957173B2 (en) * | 2008-10-14 | 2011-06-07 | Mosaid Technologies Incorporated | Composite memory having a bridging device for connecting discrete memory devices to a system |
US9306793B1 (en) | 2008-10-22 | 2016-04-05 | Alacritech, Inc. | TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies |
US20100115172A1 (en) * | 2008-11-04 | 2010-05-06 | Mosaid Technologies Incorporated | Bridge device having a virtual page buffer |
US8549209B2 (en) * | 2008-11-04 | 2013-10-01 | Mosaid Technologies Incorporated | Bridging device having a configurable virtual page size |
KR101572879B1 (ko) | 2009-04-29 | 2015-12-01 | 삼성전자주식회사 | 병렬 응용 프로그램을 동적으로 병렬처리 하는 시스템 및 방법 |
US8316071B2 (en) * | 2009-05-27 | 2012-11-20 | Advanced Micro Devices, Inc. | Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor |
US8521980B2 (en) * | 2009-07-16 | 2013-08-27 | Mosaid Technologies Incorporated | Simultaneous read and write data transfer |
US20110047358A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication |
US8458684B2 (en) * | 2009-08-19 | 2013-06-04 | International Business Machines Corporation | Insertion of operation-and-indicate instructions for optimized SIMD code |
US8582382B2 (en) * | 2010-03-23 | 2013-11-12 | Mosaid Technologies Incorporated | Memory system having a plurality of serially connected devices |
US8843692B2 (en) | 2010-04-27 | 2014-09-23 | Conversant Intellectual Property Management Inc. | System of interconnected nonvolatile memories having automatic status packet |
US8452948B2 (en) | 2010-06-28 | 2013-05-28 | International Business Machines Corporation | Hybrid compare and swap/perform locked operation queue algorithm |
US8904115B2 (en) * | 2010-09-28 | 2014-12-02 | Texas Instruments Incorporated | Cache with multiple access pipelines |
US8589509B2 (en) | 2011-01-05 | 2013-11-19 | Cloudium Systems Limited | Controlling and optimizing system latency |
TWI448156B (zh) * | 2011-02-25 | 2014-08-01 | Mstar Semiconductor Inc | 校正影音訊號之校正裝置及方法 |
US8825967B2 (en) | 2011-12-08 | 2014-09-02 | Conversant Intellectual Property Management Inc. | Independent write and read control in serially-connected devices |
US20130179642A1 (en) * | 2012-01-10 | 2013-07-11 | Qualcomm Incorporated | Non-Allocating Memory Access with Physical Address |
US8776223B2 (en) * | 2012-01-16 | 2014-07-08 | Qualcomm Incorporated | Dynamic execution prevention to inhibit return-oriented programming |
US9304776B2 (en) | 2012-01-31 | 2016-04-05 | Oracle International Corporation | System and method for mitigating the impact of branch misprediction when exiting spin loops |
US9329863B2 (en) | 2012-03-13 | 2016-05-03 | International Business Machines Corporation | Load register on condition with zero or immediate instruction |
WO2013147882A1 (en) * | 2012-03-30 | 2013-10-03 | Intel Corporation | Efficient locking of memory pages |
US9532080B2 (en) | 2012-05-31 | 2016-12-27 | Sonic Ip, Inc. | Systems and methods for the reuse of encoding information in encoding alternative streams of video data |
US9323529B2 (en) | 2012-07-18 | 2016-04-26 | International Business Machines Corporation | Reducing register read ports for register pairs |
US9323532B2 (en) | 2012-07-18 | 2016-04-26 | International Business Machines Corporation | Predicting register pairs |
US9298459B2 (en) * | 2012-07-18 | 2016-03-29 | International Business Machines Corporation | Managing register pairing |
US9471484B2 (en) | 2012-09-19 | 2016-10-18 | Novachips Canada Inc. | Flash memory controller having dual mode pin-out |
US9632838B2 (en) * | 2012-12-18 | 2017-04-25 | Microsoft Technology Licensing, Llc | Cloud based media processing workflows and module updating |
US9141454B2 (en) * | 2012-12-27 | 2015-09-22 | Intel Corporation | Signaling software recoverable errors |
US9513906B2 (en) | 2013-01-23 | 2016-12-06 | International Business Machines Corporation | Vector checksum instruction |
US9471308B2 (en) | 2013-01-23 | 2016-10-18 | International Business Machines Corporation | Vector floating point test data class immediate instruction |
US9804840B2 (en) | 2013-01-23 | 2017-10-31 | International Business Machines Corporation | Vector Galois Field Multiply Sum and Accumulate instruction |
US9357210B2 (en) | 2013-02-28 | 2016-05-31 | Sonic Ip, Inc. | Systems and methods of encoding multiple video streams for adaptive bitrate streaming |
US9823929B2 (en) * | 2013-03-15 | 2017-11-21 | Qualcomm Incorporated | Optimizing performance for context-dependent instructions |
US9207944B1 (en) | 2013-03-15 | 2015-12-08 | Google Inc. | Doubling thread resources in a processor |
US9116953B2 (en) | 2013-05-17 | 2015-08-25 | Sap Se | Calculation engine with dynamic partitioning of intermediate results |
WO2014189510A1 (en) * | 2013-05-23 | 2014-11-27 | Intel Corporation | Techniques for detecting return-oriented programming |
US9354891B2 (en) * | 2013-05-29 | 2016-05-31 | Apple Inc. | Increasing macroscalar instruction level parallelism |
US9632139B2 (en) * | 2013-06-08 | 2017-04-25 | Silicon Mobility | IO pad circuitry with safety monitoring and control for integrated circuits |
US9461837B2 (en) | 2013-06-28 | 2016-10-04 | Altera Corporation | Central alignment circutry for high-speed serial receiver circuits |
US9582321B2 (en) * | 2013-11-08 | 2017-02-28 | Swarm64 As | System and method of data processing |
WO2015183834A1 (en) | 2014-05-27 | 2015-12-03 | Rambus Inc. | Memory module with reduced read/write turnaround overhead |
US9785565B2 (en) | 2014-06-30 | 2017-10-10 | Microunity Systems Engineering, Inc. | System and methods for expandably wide processor instructions |
US9652262B2 (en) * | 2014-10-09 | 2017-05-16 | The Regents Of The University Of Michigan | Operation parameter control based upon queued instruction characteristics |
US10678544B2 (en) * | 2015-09-19 | 2020-06-09 | Microsoft Technology Licensing, Llc | Initiating instruction block execution using a register access instruction |
US11681531B2 (en) | 2015-09-19 | 2023-06-20 | Microsoft Technology Licensing, Llc | Generation and use of memory access instruction order encodings |
CN105677769B (zh) | 2015-12-29 | 2018-01-05 | 广州神马移动信息科技有限公司 | 一种基于潜在狄利克雷分配(lda)模型的关键词推荐方法和系统 |
KR20170136382A (ko) * | 2016-06-01 | 2017-12-11 | 주식회사 맴레이 | 메모리 컨트롤러, 그리고 이를 포함하는 메모리 모듈 및 프로세서 |
US10120649B2 (en) * | 2016-07-29 | 2018-11-06 | Microunity Systems Engineering, Inc. | Processor and method for outer product accumulate operations |
KR101925681B1 (ko) * | 2016-09-28 | 2018-12-05 | 가천대학교 산학협력단 | 멀티코어 시스템을 이용한 병렬 비디오 처리 |
US10120680B2 (en) * | 2016-12-30 | 2018-11-06 | Intel Corporation | Systems, apparatuses, and methods for arithmetic recurrence |
US10372452B2 (en) * | 2017-03-14 | 2019-08-06 | Samsung Electronics Co., Ltd. | Memory load to load fusing |
US10579499B2 (en) * | 2017-04-04 | 2020-03-03 | International Business Machines Corporation | Task latency debugging in symmetric multiprocessing computer systems |
IT201700050153A1 (it) * | 2017-05-09 | 2018-11-09 | St Microelectronics Srl | Modulo hardware di sicurezza, relativo sistema di elaborazione, circuito integrato e dispositivo |
JP6829838B2 (ja) | 2017-05-12 | 2021-02-17 | 株式会社Preferred Networks | 演算装置及び演算システム |
CN107977231B (zh) * | 2017-12-15 | 2020-10-27 | 安徽寒武纪信息科技有限公司 | 一种计算方法及相关产品 |
WO2019190866A1 (en) | 2018-03-26 | 2019-10-03 | Rambus Inc. | Command/address channel error detection |
US11171983B2 (en) * | 2018-06-29 | 2021-11-09 | Intel Corporation | Techniques to provide function-level isolation with capability-based security |
US10776207B2 (en) | 2018-09-06 | 2020-09-15 | International Business Machines Corporation | Load exploitation and improved pipelineability of hardware instructions |
US11379599B2 (en) * | 2018-09-28 | 2022-07-05 | Amazon Technologies, Inc. | Client-side filesystem for a remote repository |
US11741196B2 (en) | 2018-11-15 | 2023-08-29 | The Research Foundation For The State University Of New York | Detecting and preventing exploits of software vulnerability using instruction tags |
US11768664B2 (en) * | 2019-03-15 | 2023-09-26 | Advanced Micro Devices, Inc. | Processing unit with mixed precision operations |
US20190220278A1 (en) * | 2019-03-27 | 2019-07-18 | Menachem Adelman | Apparatus and method for down-converting and interleaving multiple floating point values |
US11157214B2 (en) * | 2019-05-07 | 2021-10-26 | SK Hynix Inc. | Controller, memory system and operating method thereof |
US11531619B2 (en) * | 2019-12-17 | 2022-12-20 | Meta Platforms, Inc. | High bandwidth memory system with crossbar switch for dynamically programmable distribution scheme |
KR20220046308A (ko) * | 2020-10-07 | 2022-04-14 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
US11947835B2 (en) | 2021-09-21 | 2024-04-02 | Black Sesame Technologies Inc. | High-performance on-chip memory controller |
Family Cites Families (149)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4025772A (en) * | 1974-03-13 | 1977-05-24 | James Nickolas Constant | Digital convolver matched filter and correlator |
JPS5717049A (en) * | 1980-07-04 | 1982-01-28 | Hitachi Ltd | Direct memory access controlling circuit and data processing system |
US4489393A (en) | 1981-12-02 | 1984-12-18 | Trw Inc. | Monolithic discrete-time digital convolution circuit |
US4509119A (en) * | 1982-06-24 | 1985-04-02 | International Business Machines Corporation | Method for managing a buffer pool referenced by batch and interactive processes |
US4595911A (en) * | 1983-07-14 | 1986-06-17 | Sperry Corporation | Programmable data reformat system |
US4888682A (en) | 1983-09-09 | 1989-12-19 | International Business Machines Corp. | Parallel vector processor using multiple dedicated processors and vector registers divided into smaller registers |
DE3485491D1 (de) | 1983-11-26 | 1992-03-12 | Toshiba Kawasaki Kk | Arithmetischer konvolutionskreis. |
US4727505A (en) * | 1984-03-29 | 1988-02-23 | Kabushiki Kaisha Toshiba | Convolution arithmetic circuit for digital signal processing |
JPS60217435A (ja) | 1984-04-12 | 1985-10-31 | Toshiba Corp | 多重精度浮動小数点加算回路 |
US4875161A (en) | 1985-07-31 | 1989-10-17 | Unisys Corporation | Scientific processor vector file organization |
US4953073A (en) * | 1986-02-06 | 1990-08-28 | Mips Computer Systems, Inc. | Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories |
DE3687124T2 (de) * | 1986-02-06 | 1993-03-18 | Mips Computer Systems Inc | Funktionseinheit fuer rechner. |
FR2605769B1 (fr) * | 1986-10-22 | 1988-12-09 | Thomson Csf | Operateur polynomial dans les corps de galois et processeur de traitement de signal numerique comportant un tel operateur |
US4876660A (en) | 1987-03-20 | 1989-10-24 | Bipolar Integrated Technology, Inc. | Fixed-point multiplier-accumulator architecture |
US5132898A (en) | 1987-09-30 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | System for processing data having different formats |
FR2622713A1 (fr) * | 1987-10-30 | 1989-05-05 | Thomson Csf | Circuit de calcul utilisant une arithmetique residuelle |
US5032865A (en) * | 1987-12-14 | 1991-07-16 | General Dynamics Corporation Air Defense Systems Div. | Calculating the dot product of large dimensional vectors in two's complement representation |
US4878190A (en) | 1988-01-29 | 1989-10-31 | Texas Instruments Incorporated | Floating point/integer processor with divide and square root functions |
JP2527458B2 (ja) * | 1988-03-04 | 1996-08-21 | 富士通株式会社 | デ―タ転送制御装置 |
US4943919A (en) * | 1988-10-17 | 1990-07-24 | The Boeing Company | Central maintenance computer system and fault data handling method |
US4893267A (en) * | 1988-11-01 | 1990-01-09 | Motorola, Inc. | Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic |
US5179651A (en) * | 1988-11-08 | 1993-01-12 | Massachusetts General Hospital | Apparatus for retrieval and processing of selected archived images for display at workstation terminals |
CA1311063C (en) | 1988-12-16 | 1992-12-01 | Tokumichi Murakami | Digital signal processor |
US4969118A (en) | 1989-01-13 | 1990-11-06 | International Business Machines Corporation | Floating point unit for calculating A=XY+Z having simultaneous multiply and add |
US5253342A (en) | 1989-01-18 | 1993-10-12 | International Business Machines Corporation | Intermachine communication services |
US5155816A (en) | 1989-02-10 | 1992-10-13 | Intel Corporation | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor |
US5157388A (en) | 1989-02-14 | 1992-10-20 | Intel Corporation | Method and apparatus for graphics data interpolation |
US5081698A (en) * | 1989-02-14 | 1992-01-14 | Intel Corporation | Method and apparatus for graphics display data manipulation |
US5768575A (en) * | 1989-02-24 | 1998-06-16 | Advanced Micro Devices, Inc. | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions |
US4975868A (en) * | 1989-04-17 | 1990-12-04 | International Business Machines Corporation | Floating-point processor having pre-adjusted exponent bias for multiplication and division |
CA1323451C (en) * | 1989-04-21 | 1993-10-19 | Victor Jacques Menasce | Cache-memory architecture |
US5233690A (en) * | 1989-07-28 | 1993-08-03 | Texas Instruments Incorporated | Video graphics display memory swizzle logic and expansion circuit and method |
JPH0398145A (ja) | 1989-09-11 | 1991-04-23 | Hitachi Ltd | マイクロプロセッサ |
US4956801A (en) * | 1989-09-15 | 1990-09-11 | Sun Microsystems, Inc. | Matrix arithmetic circuit for processing matrix transformation operations |
EP0429733B1 (de) * | 1989-11-17 | 1999-04-28 | Texas Instruments Incorporated | Multiprozessor mit Koordinatenschalter zwischen Prozessoren und Speichern |
US5208914A (en) * | 1989-12-29 | 1993-05-04 | Superconductor Systems Limited Partnership | Method and apparatus for non-sequential resource access |
US5241636A (en) * | 1990-02-14 | 1993-08-31 | Intel Corporation | Method for parallel instruction execution in a computer |
KR930008050B1 (ko) * | 1990-02-16 | 1993-08-25 | 가부시끼가이샤 히다찌세이사꾸쇼 | 원칩 마이크로프로세서 및 그 버스시스템 |
US5590365A (en) | 1990-03-30 | 1996-12-31 | Kabushiki Kaisha Toshiba | Pipeline information processing circuit for floating point operations |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US5201056A (en) * | 1990-05-02 | 1993-04-06 | Motorola, Inc. | RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output |
CA2045705A1 (en) * | 1990-06-29 | 1991-12-30 | Richard Lee Sites | In-register data manipulation in reduced instruction set processor |
JPH0484253A (ja) * | 1990-07-26 | 1992-03-17 | Mitsubishi Electric Corp | バス幅制御回路 |
JP2651267B2 (ja) | 1990-07-26 | 1997-09-10 | 富士通株式会社 | 演算処理装置及び演算処理方法 |
EP0474246A2 (de) | 1990-09-06 | 1992-03-11 | Matsushita Electric Industrial Co., Ltd. | Bildsignalverarbeitungsgerät |
US5249132A (en) * | 1990-10-31 | 1993-09-28 | Tektronix, Inc. | Digital pulse generator |
US5809292A (en) | 1990-11-13 | 1998-09-15 | International Business Machines Corporation | Floating point for simid array machine |
US5588152A (en) | 1990-11-13 | 1996-12-24 | International Business Machines Corporation | Advanced parallel processor including advanced support hardware |
JP3100622B2 (ja) * | 1990-11-20 | 2000-10-16 | 沖電気工業株式会社 | 同期型ダイナミックram |
US5268995A (en) | 1990-11-21 | 1993-12-07 | Motorola, Inc. | Method for executing graphics Z-compare and pixel merge instructions in a data processor |
US5367643A (en) * | 1991-02-06 | 1994-11-22 | International Business Machines Corporation | Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets |
ATE179810T1 (de) | 1991-03-01 | 1999-05-15 | Advanced Micro Devices Inc | Mikroprozessor mit externem speicher |
US5408581A (en) * | 1991-03-14 | 1995-04-18 | Technology Research Association Of Medical And Welfare Apparatus | Apparatus and method for speech signal processing |
JP2816624B2 (ja) * | 1991-04-01 | 1998-10-27 | モトローラ・インコーポレイテッド | 2乗演算を実行する速度改良型データ処理システム及びその方法 |
FR2676845B1 (fr) | 1991-05-23 | 1993-09-24 | Sextant Avionique | Dispositif pour la gestion de plusieurs files d'attente independantes dans un espace memoire commun et banalise. |
FR2677200B1 (fr) * | 1991-05-30 | 1993-09-17 | Besnard Christian | Dispositif de securisation de donnees numeriques. |
US5325495A (en) * | 1991-06-28 | 1994-06-28 | Digital Equipment Corporation | Reducing stall delay in pipelined computer system using queue between pipeline stages |
US5493687A (en) * | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
US5327570A (en) * | 1991-07-22 | 1994-07-05 | International Business Machines Corporation | Multiprocessor system having local write cache within each data processor node |
JP3366633B2 (ja) * | 1991-11-27 | 2003-01-14 | セイコーエプソン株式会社 | ピクセル変更システム及びピクセル変更方法 |
US5313626A (en) * | 1991-12-17 | 1994-05-17 | Jones Craig S | Disk drive array with efficient background rebuilding |
US5530960A (en) * | 1991-12-17 | 1996-06-25 | Dell Usa, L.P. | Disk drive controller accepting first commands for accessing composite drives and second commands for individual diagnostic drive control wherein commands are transparent to each other |
US5404469A (en) * | 1992-02-25 | 1995-04-04 | Industrial Technology Research Institute | Multi-threaded microprocessor architecture utilizing static interleaving |
US5231646A (en) * | 1992-03-16 | 1993-07-27 | Kyros Corporation | Communications system |
US5669010A (en) | 1992-05-18 | 1997-09-16 | Silicon Engines | Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units |
US5640543A (en) * | 1992-06-19 | 1997-06-17 | Intel Corporation | Scalable multimedia platform architecture |
US5471628A (en) | 1992-06-30 | 1995-11-28 | International Business Machines Corporation | Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode |
JP3268024B2 (ja) | 1992-08-25 | 2002-03-25 | 日本化学産業株式会社 | 天井の換気構造 |
US5268855A (en) * | 1992-09-14 | 1993-12-07 | Hewlett-Packard Company | Common format for encoding both single and double precision floating point numbers |
US5256994A (en) | 1992-09-21 | 1993-10-26 | Intel Corporation | Programmable secondary clock generator |
US5423051A (en) * | 1992-09-24 | 1995-06-06 | International Business Machines Corporation | Execution unit with an integrated vector operation capability |
JP3369227B2 (ja) | 1992-11-09 | 2003-01-20 | 株式会社東芝 | プロセッサ |
IE922813A1 (en) * | 1992-11-12 | 1994-05-18 | Digital Equipment Internat Ltd | Digital data storage system |
US5440632A (en) * | 1992-12-02 | 1995-08-08 | Scientific-Atlanta, Inc. | Reprogrammable subscriber terminal |
US5519842A (en) * | 1993-02-26 | 1996-05-21 | Intel Corporation | Method and apparatus for performing unaligned little endian and big endian data accesses in a processing system |
US5483640A (en) * | 1993-02-26 | 1996-01-09 | 3Com Corporation | System for managing data flow among devices by storing data and structures needed by the devices and transferring configuration information from processor to the devices |
US5327369A (en) * | 1993-03-31 | 1994-07-05 | Intel Corporation | Digital adder and method for adding 64-bit, 16-bit and 8-bit words |
US5465343A (en) * | 1993-04-30 | 1995-11-07 | Quantum Corporation | Shared memory array for data block and control program storage in disk drive |
US5450607A (en) * | 1993-05-17 | 1995-09-12 | Mips Technologies Inc. | Unified floating point and integer datapath for a RISC processor |
DE69418646T2 (de) | 1993-06-04 | 2000-06-29 | Sun Microsystems Inc | Gleitkommaprozessor für einen hochleistungsfähigen dreidimensionalen Graphikbeschleuniger |
US5522054A (en) * | 1993-09-13 | 1996-05-28 | Compaq Computer Corporation | Dynamic control of outstanding hard disk read requests for sequential and random operations |
US5371772A (en) | 1993-09-14 | 1994-12-06 | Intel Corporation | Programmable divider exhibiting a 50/50 duty cycle |
US5426600A (en) * | 1993-09-27 | 1995-06-20 | Hitachi America, Ltd. | Double precision division circuit and method for digital signal processor |
EP0645699A1 (de) * | 1993-09-29 | 1995-03-29 | International Business Machines Corporation | Instruktionsfolge zur Hochgeschwindigkeits-Multiplizierung-Addierung in einem Pipeline-Gleitkommaprozessor |
US5557724A (en) * | 1993-10-12 | 1996-09-17 | Intel Corporation | User interface, method, and apparatus selecting and playing channels having video, audio, and/or text streams |
JPH07114469A (ja) * | 1993-10-18 | 1995-05-02 | Mitsubishi Electric Corp | データ処理装置 |
EP0779577B1 (de) * | 1993-10-18 | 2002-05-22 | VIA-Cyrix, Inc. | Mikroprozessorpipelinesteuerung und Registerübersetzung |
DE69429061T2 (de) * | 1993-10-29 | 2002-07-18 | Advanced Micro Devices Inc | Superskalarmikroprozessoren |
US5409469A (en) * | 1993-11-04 | 1995-04-25 | Medtronic, Inc. | Introducer system having kink resistant splittable sheath |
EP0974894B1 (de) * | 1993-11-05 | 2002-02-27 | Intergraph Corporation | Befehlscachespeicher mit assoziativem Kreuzschienenschalter |
US6128721A (en) * | 1993-11-17 | 2000-10-03 | Sun Microsystems, Inc. | Temporary pipeline register file for a superpipelined superscalar processor |
EP0924601B1 (de) * | 1993-11-23 | 2001-09-26 | Hewlett-Packard Company, A Delaware Corporation | Parallele Datenverarbeitung in einem Einzelprozessor |
US5390135A (en) * | 1993-11-29 | 1995-02-14 | Hewlett-Packard | Parallel shift and add circuit and method |
US5883824A (en) * | 1993-11-29 | 1999-03-16 | Hewlett-Packard Company | Parallel adding and averaging circuit and method |
US6016538A (en) * | 1993-11-30 | 2000-01-18 | Texas Instruments Incorporated | Method, apparatus and system forming the sum of data in plural equal sections of a single data word |
US5590350A (en) | 1993-11-30 | 1996-12-31 | Texas Instruments Incorporated | Three input arithmetic logic unit with mask generator |
US5448509A (en) * | 1993-12-08 | 1995-09-05 | Hewlett-Packard Company | Efficient hardware handling of positive and negative overflow resulting from arithmetic operations |
US5467131A (en) | 1993-12-30 | 1995-11-14 | Hewlett-Packard Company | Method and apparatus for fast digital signal decoding |
US5541865A (en) * | 1993-12-30 | 1996-07-30 | Intel Corporation | Method and apparatus for performing a population count operation |
US5673407A (en) | 1994-03-08 | 1997-09-30 | Texas Instruments Incorporated | Data processor having capability to perform both floating point operations and memory access in response to a single instruction |
US5751614A (en) * | 1994-03-08 | 1998-05-12 | Exponential Technology, Inc. | Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALU |
JPH07271764A (ja) | 1994-03-24 | 1995-10-20 | Internatl Business Mach Corp <Ibm> | 計算機プロセッサ及びシステム |
JP3547482B2 (ja) * | 1994-04-15 | 2004-07-28 | 株式会社日立製作所 | 情報処理装置 |
US5734874A (en) * | 1994-04-29 | 1998-03-31 | Sun Microsystems, Inc. | Central processing unit with integrated graphics functions |
US5642306A (en) * | 1994-07-27 | 1997-06-24 | Intel Corporation | Method and apparatus for a single instruction multiple data early-out zero-skip multiplier |
US5579253A (en) | 1994-09-02 | 1996-11-26 | Lee; Ruby B. | Computer multiply instruction with a subresult selection option |
US5758176A (en) * | 1994-09-28 | 1998-05-26 | International Business Machines Corporation | Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system |
US5758116A (en) * | 1994-09-30 | 1998-05-26 | Intel Corporation | Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions |
US5477181A (en) | 1994-10-13 | 1995-12-19 | National Semiconductor Corporation | Programmable multiphase clock divider |
WO1996017293A1 (en) | 1994-12-01 | 1996-06-06 | Intel Corporation | A microprocessor having a multiply operation |
ZA9510127B (en) | 1994-12-01 | 1996-06-06 | Intel Corp | Novel processor having shift operations |
WO1996017291A1 (en) | 1994-12-02 | 1996-06-06 | Intel Corporation | Microprocessor with packing operation of composite operands |
US5819101A (en) | 1994-12-02 | 1998-10-06 | Intel Corporation | Method for packing a plurality of packed data elements in response to a pack instruction |
US5598362A (en) * | 1994-12-22 | 1997-01-28 | Motorola Inc. | Apparatus and method for performing both 24 bit and 16 bit arithmetic |
US5680338A (en) | 1995-01-04 | 1997-10-21 | International Business Machines Corporation | Method and system for vector processing utilizing selected vector elements |
US5887183A (en) * | 1995-01-04 | 1999-03-23 | International Business Machines Corporation | Method and system in a data processing system for loading and storing vectors in a plurality of modes |
US5500811A (en) * | 1995-01-23 | 1996-03-19 | Microunity Systems Engineering, Inc. | Finite impulse response filter |
US5826106A (en) | 1995-05-26 | 1998-10-20 | National Semiconductor Corporation | High performance multifunction direct memory access (DMA) controller |
US6381690B1 (en) * | 1995-08-01 | 2002-04-30 | Hewlett-Packard Company | Processor for performing subword permutations and combinations |
US5953241A (en) * | 1995-08-16 | 1999-09-14 | Microunity Engeering Systems, Inc. | Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction |
US5742840A (en) * | 1995-08-16 | 1998-04-21 | Microunity Systems Engineering, Inc. | General purpose, multiple precision parallel operation, programmable media processor |
US6006318A (en) | 1995-08-16 | 1999-12-21 | Microunity Systems Engineering, Inc. | General purpose, dynamic partitioning, programmable media processor |
US6643765B1 (en) | 1995-08-16 | 2003-11-04 | Microunity Systems Engineering, Inc. | Programmable processor with group floating point operations |
US6295599B1 (en) * | 1995-08-16 | 2001-09-25 | Microunity Systems Engineering | System and method for providing a wide operand architecture |
US5721892A (en) * | 1995-08-31 | 1998-02-24 | Intel Corporation | Method and apparatus for performing multiply-subtract operations on packed data |
US5886732A (en) * | 1995-11-22 | 1999-03-23 | Samsung Information Systems America | Set-top electronics and network interface unit arrangement |
US5933160A (en) * | 1995-11-27 | 1999-08-03 | Sun Microsystems | High-performance band combine function |
US5757432A (en) * | 1995-12-18 | 1998-05-26 | Intel Corporation | Manipulating video and audio signals using a processor which supports SIMD instructions |
KR0157924B1 (ko) * | 1995-12-23 | 1998-12-15 | 문정환 | 데이타 전송 시스템 및 그 방법 |
US5983257A (en) | 1995-12-26 | 1999-11-09 | Intel Corporation | System for signal processing using multiply-add operations |
US5835782A (en) | 1996-03-04 | 1998-11-10 | Intel Corporation | Packed/add and packed subtract operations |
US6092094A (en) * | 1996-04-17 | 2000-07-18 | Advanced Micro Devices, Inc. | Execute unit configured to selectably interpret an operand as multiple operands or as a single operand |
US6058465A (en) | 1996-08-19 | 2000-05-02 | Nguyen; Le Trong | Single-instruction-multiple-data processing in a multimedia signal processor |
US6073159A (en) * | 1996-12-31 | 2000-06-06 | Compaq Computer Corporation | Thread properties attribute vector based thread selection in multithreading processor |
US6401194B1 (en) * | 1997-01-28 | 2002-06-04 | Samsung Electronics Co., Ltd. | Execution unit for processing a data stream independently and in parallel |
US5922066A (en) * | 1997-02-24 | 1999-07-13 | Samsung Electronics Co., Ltd. | Multifunction data aligner in wide data width processor |
JP3602293B2 (ja) | 1997-04-22 | 2004-12-15 | 株式会社ソニー・コンピュータエンタテインメント | データ転送方法及び装置 |
US6269426B1 (en) * | 1997-06-24 | 2001-07-31 | Sun Microsystems, Inc. | Method for operating a non-blocking hierarchical cache throttle |
US6144982A (en) | 1997-06-25 | 2000-11-07 | Sun Microsystems, Inc. | Pipeline processor and computing system including an apparatus for tracking pipeline resources |
US6170051B1 (en) * | 1997-08-01 | 2001-01-02 | Micron Technology, Inc. | Apparatus and method for program level parallelism in a VLIW processor |
US5933650A (en) * | 1997-10-09 | 1999-08-03 | Mips Technologies, Inc. | Alignment and ordering of vector elements for single instruction multiple data processing |
US6230257B1 (en) * | 1998-03-31 | 2001-05-08 | Intel Corporation | Method and apparatus for staggering execution of a single packed data instruction using the same circuit |
US6211892B1 (en) * | 1998-03-31 | 2001-04-03 | Intel Corporation | System and method for performing an intra-add operation |
US5996057A (en) | 1998-04-17 | 1999-11-30 | Apple | Data processing system and method of permutation with replication within a vector register file |
US6260116B1 (en) * | 1998-07-01 | 2001-07-10 | International Business Machines Corporation | System and method for prefetching data |
JP3803196B2 (ja) * | 1998-07-03 | 2006-08-02 | 株式会社ソニー・コンピュータエンタテインメント | 情報処理装置、情報処理方法および記録媒体 |
US6272512B1 (en) | 1998-10-12 | 2001-08-07 | Intel Corporation | Data manipulation instruction for enhancing value and efficiency of complex arithmetic |
US6732259B1 (en) * | 1999-07-30 | 2004-05-04 | Mips Technologies, Inc. | Processor having a conditional branch extension of an instruction set architecture |
WO2001067235A2 (en) | 2000-03-08 | 2001-09-13 | Sun Microsystems, Inc. | Processing architecture having sub-word shuffling and opcode modification |
-
1995
- 1995-08-16 US US08/516,036 patent/US5742840A/en not_active Expired - Lifetime
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1996
- 1996-02-23 US US08/606,342 patent/US5778419A/en not_active Expired - Lifetime
- 1996-08-16 EP EP07111476A patent/EP1876536A3/de not_active Withdrawn
- 1996-08-16 EP EP07111480A patent/EP1879397A3/de not_active Withdrawn
- 1996-08-16 AU AU67716/96A patent/AU6771696A/en not_active Abandoned
- 1996-08-16 EP EP07111349A patent/EP1873653A3/de not_active Withdrawn
- 1996-08-16 AT AT07112545T patent/ATE548691T1/de active
- 1996-08-16 EP EP07111344A patent/EP1873628A3/de not_active Withdrawn
- 1996-08-16 AT AT07111352T patent/ATE532130T1/de active
- 1996-08-16 ES ES96928129T patent/ES2275453T1/es active Pending
- 1996-08-16 AT AT07111351T patent/ATE528712T1/de not_active IP Right Cessation
- 1996-08-16 EP EP07111350A patent/EP1873654A3/de not_active Withdrawn
- 1996-08-16 DE DE69638268T patent/DE69638268D1/de not_active Expired - Lifetime
- 1996-08-16 EP EP07111352A patent/EP1873630B8/de not_active Expired - Lifetime
- 1996-08-16 EP EP07112548A patent/EP1879398B1/de not_active Expired - Lifetime
- 1996-08-16 EP EP07112553A patent/EP1879104A3/de not_active Withdrawn
- 1996-08-16 DE DE96928129T patent/DE96928129T1/de active Pending
- 1996-08-16 EP EP07111473A patent/EP1876535A3/de not_active Withdrawn
- 1996-08-16 AT AT07112538T patent/ATE511137T1/de not_active IP Right Cessation
- 1996-08-16 EP EP07112538A patent/EP1879102B1/de not_active Expired - Lifetime
- 1996-08-16 EP EP07111348A patent/EP1873629A3/de not_active Withdrawn
- 1996-08-16 EP EP96928129A patent/EP0845120B1/de not_active Expired - Lifetime
- 1996-08-16 AT AT96928129T patent/ATE484022T1/de not_active IP Right Cessation
- 1996-08-16 EP EP07112545A patent/EP1879103B1/de not_active Expired - Lifetime
- 1996-08-16 WO PCT/US1996/013047 patent/WO1997007450A1/en active Search and Examination
- 1996-08-16 EP EP07111351A patent/EP1876524B8/de not_active Expired - Lifetime
- 1996-11-22 US US08/754,826 patent/US5794060A/en not_active Expired - Lifetime
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- 1996-11-22 US US08/754,827 patent/US5822603A/en not_active Expired - Lifetime
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