EP0030034A2 - Digital semiconductor circuit for an electronic organ - Google Patents

Abstract

A control input of the digital circuit is assigned to each play key in the manual of the organ. In addition, 12 sound signal inputs are provided, each of which is assigned a tone of the highest octave in the manual. The levels "O" and "1" are applied to them by corresponding electrical rectangular oscillations supplied by an audio frequency generator. The number of audio frequency outputs provided in the circuit is considerably smaller than the number of control inputs of the digital circuit acting as a switching system. Each of the audio frequency outputs is provided for the application of a fixedly arranged amplitude shaper. The game buttons in the manual provide a shift register operated as a parallel series converter, which is emptied cyclically into the actual switching system via the control inputs. The shift cycles required for this are evaluated both with regard to the tone name and with regard to the octave of the respective play key played.

Description

The invention relates to a digital semiconductor circuit for an electronic organ with a number of control inputs applied via the manual corresponding to the number of play keys of the manual of the organ and with a number of sound signal inputs, each of _{which is} applied by an oscillator system with periodic electrical vibrations Control input for each game button of the manual and one audio signal input for each audio frequency is permanently assigned, in which an audio signal output is further provided for the application of an electro-acoustic transducer and in which the control signals serving for the control inputs finally correspond to the logic levels.

For example, in known digital semiconductor circuits of this type, the individual control inputs are acted upon by each of these Control inputs can be applied via a switch to a common first operating potential assigned to level "1" and when the individual game button is actuated, the switch assigned to it is closed as a result of the actuation. Control inputs, whose game keys are pressed, have the level "1", control inputs, whose game keys are not actuated, accordingly, the level "0". Furthermore, in known electronic organs, a generator is used to generate the sound frequencies, which - starting from an oscillator which supplies a square wave corresponding to the two logical levels with the highest frequency - delivers the individual tone vibrations at least to the highest octave of the organ by frequency division and to one input each provides an AND gate with two inputs, the second input of which is acted upon by the associated control input. The entirety of these AND gates is then provided to act on the audio signal outputs.

It is now possible to assign such an amplitude former to each game button and thus to each input of the digital semiconductor circuit of the electronic organ. However, the effort involved is undesirably high, especially when the semiconductor circuit is implemented monolithically. On the other hand, for musical reasons it is impossible to provide a total of only one signal output from the digital circuit of the organ and, accordingly, only a single amplitude shaper. This means that the digital semiconductor circuit of the organ is to be provided with "several, in particular expediently with ten, signal outputs, which are then each connected to the input of an amplitude shaping circuit. The entirety of the amplitude shapers is then at a common output for the application of the electro-acoustic transducer, especially a loudspeaker.

For this purpose, according to the invention it is provided that the individual control inputs are each assigned to a cell of a clock-controlled shift register operated as a parallel series converter, and that the signal output of the shift register and the clock pulses provided for its operation are used to control a switching system which, on the other hand, The totality of the provided sound signal inputs is provided that in addition the number of sound signal outputs is less than the number of control inputs and each of the sound signal outputs is assigned an amplitude shaper and that finally the outputs of the amplitude shifters are connected to an electro-acoustic transducer.

• 1. Die p Tonsignalausgänge der Vermittlungsanlage sind nummeriert, d. h., entsprechend einer Hierarchie geschaltet.
• 2. Die Gesamtheit der n Steuereingänge wird periodisch abgefragt, d. h., das Schieberegister in die Vermittlungsanlage geleert. Dabei ist angestrebt, daß zwischen zwei aufeinanderfolgenden Abfragevorgängen die jeweils zuerst gedrückte Spieltaste bzw. der ihr zugeordnete Steuereingang auf den ersten Tonsignalausgang, die als nächste gedrückte Spieltaste auf den zweiten Tonsignaleingang entsprechend der unter 1. genannten Hierarchie geschaltet wird. Wie bereits bemerkt, wird bevorzugt die Zahl p der Tonsignalausgänge auf p = 10 (entsprechend der Fingerzahl) festgelegt. Außerdem wird der zeitliche Abstand aufeinanderfolgender Abfragezyklen so kurz bemessen, daß er höchstens der zum Spielen eines Akkords durch den raschesten Spieler benötigten Zeitspanne entspricht. Demzufolge ist im allgemeinen damit zu rechnen, daß pro Abfragezyklus höchstens eine weitere Information aus dem Manual in das als Parallel-Serienwandler betriebene Schieberegister eingeht.
  Für den Fall, daß demgegenüber zwischen zwei aufeinanderfolgenden Abfragevorgängen mehr als p Steuereingänge beaufschlagt, also z. B. mehr als zehn Töne gespielt werden, sollen die überschüssigen Informationen unter Berücksichtigung der unter 1. und 2. angedeuteten Hierarchie ignoriert werden.
• 3. Ist ein Tonsignalausgang oder Kanal einmal belegt, so ist angestrebt, diesen erst dann wieder freizugeben, wenn nach Freigabe der die Belegung verursachenden Spieltaste der Ton und damit die den Ton verursachenden elektrischen Information in dem durch den Tonsignalausgang beaufschlagten Amplitudenformer abgeklungen ist.

Andererseits ist ein Nachhalleffekt vorgesehen, so daß mit dem Loslassen der Spieltaste der angespielte Ton nicht schlagartig unterdrückt wird.In a preferred embodiment, a total of 5 octaves and a key, that is 61 game keys and accordingly 61 control inputs are provided in the digital semiconductor circuit according to the invention in the manual of the organ. In the general case, a different number, eg., For the number n of the game keys and thus for the number n of the control inputs. B. 75 may be provided. The number m of the sound signal inputs is z. B. fixed to m = 12, while the number p of the sound signal outputs and thus the number of amplitude shapers provided in the circuit is preferably p = 10. The core of the invention is the switching system, the aim of further embodiments of the invention being to design it according to at least one of the following aspects:

• 1. The p sound signal outputs of the switching system are numbered, ie ge according to a hierarchy switches.
• 2. The entirety of the n control inputs is queried periodically, ie the shift register is emptied into the switching system. The aim is that between two successive interrogation processes, the game button pressed first or the control input assigned to it is switched to the first audio signal output, and the game button pressed next is switched to the second audio signal input in accordance with the hierarchy mentioned under 1. As already noted, the number p of the audio signal outputs is preferably set to p = 10 (corresponding to the number of fingers). In addition, the time interval between successive query cycles is dimensioned so short that it corresponds at most to the time required for the fastest player to play a chord. Accordingly, it is generally to be expected that at most one additional item of information from the manual will be received in the shift register operated as a parallel series converter.
  In the event that, on the other hand, between two successive interrogation processes, more than p control inputs are applied, that is, for. B. more than ten tones are played, the excess information should be ignored taking into account the hierarchy indicated under 1. and 2.
• 3. Once a sound signal output or channel is occupied, the aim is to only release it again when, after the game button causing the assignment has been released, the sound and thus the electrical information causing the sound has decayed in the amplitude shaper affected by the sound signal output.

On the other hand, a reverberation effect is provided so that the sound played is not suddenly suppressed when the play button is released.

If a game button is released when the tone signal outputs are fully occupied and another game button is struck in its place, the new tone is to be generated via the tone signal output that has been released by releasing the other game button. If several game buttons are released at the same time when the audio signal outputs are fully occupied and a new game button is pressed, the information associated with the new game button and the audio signal that it calls up should be applied to the audio signal outputs that this frees up, in which the tone that was played last and still remains in the reverberation effect faded most. If a released game button is finally struck again immediately, it is advisable to reassign the old sound signal output to the switching system.

The invention will now be described with reference to FIGS. 1 to 10. In Fig. 1, the essential parts of the invention are shown in the block diagram, while the remaining figures deal with details of the switching system or the amplitude shaping.

In the manner already indicated, the n control inputs E ₁ , E ₂ ,... E _n , or E _{v for} short, of the semiconductor digital circuit according to the invention are now acted upon by the individual game keys of the manual M. These n control inputs E _v form the information input of one register cell each of a clock-controlled shift register PSW, which is operated as a parallel series converter and by a clock generator TG during the individual sections question cycles are supplied with the shifting cycles required to push out the information provided by Manual M. The shift register PSW preferably has n register cells, so that each control input E _{v has} a register cell and each register cell has a control input E _{v of} the shift register PSW.

The data output DA of the shift register PSW is connected to the data input DE of a so-called channel selector KW, which at the same time forms an information input of the switching system VM. As a further information input, the switching system contains the count input of a sound address counter TAZ, which is designed as a digital counter on a binary basis and is described in more detail with regard to its design and control.

In addition to the channel selector KW and the sound address counter TAZ, the switching system VM p contains mutually identical output parts, ie output channels V1 to Vp, which are controlled on the one hand by the channel selector KW and on the other hand by the sound address counter TAZ. In addition, the switching system has m sound signal inputs, which are acted upon by a tone frequency generator TOS.

The tone frequency generator TOS is designed in the usual way and has a number of tone frequency outputs, each of which is assigned to a tone frequency. The tone frequency generator TOS usually has twelve tone frequency outputs, each of which provides a periodic square wave with a frequency which is assigned to a tone of the highest octave of the range of the organ. Such a tone frequency generator has a rectangular Oscillator, which provides a square wave with a sufficiently high frequency to be able to derive square waves with the help of frequency dividers with the frequencies corresponding to the tones of the highest octave. These are then made available at each of the m = 12 audio frequency outputs of the audio frequency generator TOS.

The m audio frequency outputs of the audio frequency generator TOS have m audio signal inputs TSE of the switching system VM, of which only one is shown in FIG. 1. In the case of m = 12 one has twelve such inputs TSE, each of which is assigned to a tone frequency of the highest octave.

The individual audio signal input TSE of the switching system VM is connected to an input (designated in the same way) of each of the mutually identical output channels V ₁ or Y ₂ ,... Or V _p . Each of these output channels V1 to V _p is provided with means which allow a reduction of the square waves delivered by the tone frequency generator TOS to the frequencies of the corresponding tones in the lower octaves. In addition, these output channels V ₁ to V _{p are} each provided with an audio signal output AU ₁ , AU ₂ , .. .. AU _p , from which the audio signals selected via the manual M are applied to the downstream amplitude formers AF ₁ or AF ₂ , ... or AF _p exceeded. The output of the individual amplitude shaper AF ₁ or AF ₂ , .. or. AF _p is e.g. B. provided in FIG. 4 for controlling a common electro-acoustic transducer, that is, a speaker system.

It should also be noted that each of the mutually identical output channels V ₁ , or V ₂ , ..... or Y _{D has} a further output B ₁ . or B ₂ , ..... or B _p , over which on the one hand a reaction to the channel selector KW, on the other hand there is an additional control of the associated amplitude shaper AF ₁ or AF ₂ , ..... or AFp.

The tone address counter TAZ consists of two parts. The first part consists of four flip-flop cells connected in series in a known manner, e.g. B. from toggle flip-flop cells, each representing a binary counter. The counter stages are switched in such a way that the first part of the counter counts to "1" in order to then have already switched back to the initial state "0" when the thirteenth count pulse arrives. Simultaneously with the arrival of the thirteenth count pulse (and only every thirteenth count pulse), a count pulse is given to the second part of the tone address counter TAZ. The second part of the sound address counter TAZ consists of three flip-flop cells connected in series and thus of three counting stages. They are switched so that the highest count corresponds to the number p of the total octaves provided and is therefore preferably "6" or "7".

The easiest way to achieve the above-mentioned behavior of the sound address counter TAZ is to connect those outputs of the four flip-flop cells forming the first counter portion that show a "1" at the desired highest count to one input of an AND gate with four inputs, so that a "1" also appears when the highest count is reached at the output of the AND gate. This is then fed to the reset input of the first part of the sound address counter TAZ and the counting input of the second part of the sound address counter. The individual counting states of the first part of the counter TAZ can be seen dedicated to the individual tones within the individual octaves and the individual counting states of the second part of one octave each within the scope of the organ.

The parallel-series shift register PSW can e.g. B. also consist of a common shift clock T or TM controlled master-slave flip-flop cells or better so-called quasi-static shift register cells. As already explained, the total number of register cells corresponds to the number of game keys in the manual M. Each register cell has its own information input, which is connected via a clock-controlled transfer gate to the control input E _{v of} the digital semiconductor circuit, each of which is supplied with logic information from the manual M. which is assigned to the relevant register cell by PSW. The entirety of the transfer gates mentioned is controlled by a takeover clock UE, which is likewise made available by the clock generator TG which supplies the shift clocks T and thus the counting clocks for the counter TAZ. With regard to an advantageous embodiment of the shift register PSW z. B. on the patent application P ^{29 24 526.9} (VPA 79 P 1104), with regard to an advantageous embodiment of the clock generator TG on the patent application P 27 13 319.3 (VPA 77 P 1027) or P 28 37 855.4 (VPA 78 P 1158) P 28 37 882.7 (VPA 78 P 1159) P 28 45 379.4 (VPA 78 P 1191).

If any game key of the manual M is now pressed, a "1" appears at the control input E _{v of} the digital semiconductor circuit assigned to it, which is then written into the register cell of the shift register PSW assigned to this control input due to the following transfer clock UE. The now following shift clocks T ensure that the shift register PSW is emptied until the next takeover clock pulse UE. The information stored in the individual register cells successively passes through the information output D of the shift register PSW in order to be entered in the channel selector to be described in more detail. The shift clocks T to be used for this purpose are also evaluated via the address counter TAZ in a manner to be described.

For this purpose, the structure of the individual output parts V ₁ or V ₂ ... Or V, which can be seen in FIG. 2, will now be discussed in more detail.

A read-write memory forms an essential part of each of these output parts of the switching system VM. Like the address counter TAZ, this memory also consists of two parts, namely a part S and a part S. The first part S receives its information on the basis of the part of the address counter TAZ assigned to the individual sound names, while the second storage part S is supplied with information to be stored due to the effect of the second part of the sound address counter TAZ assigned to the octaves.

The information read out from the first memory part S is sent via a first decoder D to twelve AND gates U ₁ to U ₁₂ , which are simultaneously acted upon by the entirety of the audio frequency inputs TSE, while the information obtained from the second memory part S is intended to act on a second decoder D. are. In addition, the information provided from the two memory parts is used to control a NOR gate NR, which in turn is the feedback input B ₁ already mentioned when looking at FIG. ₁ or B ₂ .... or B of the output part V ₁ or V ₂ etc. forms.

Immediately after each takeover clock UE that causes information to be input into the input shift register PSW, the serial readout of the information recorded in each case from this shift register and the structure of the information relating to the two memory parts S and S begin in a manner to be described. Each of the two memory parts is expediently constructed from discrete memory cells, in particular from discrete quasi-static register cells corresponding to the input shift register PSW, with the clock pulses TM for the input shift register PSW or the counting clocks for the sound address counter TAZ as shift clocks for the construction of the memory content of both memory parts S and S be used, as will be explained in more detail with reference to FIG. 3.

For example, the data output DA of the input shift register PSW can be connected to the one input of an AND gate, the other input of which is controlled by the shift clocks T or by secondary pulses derived therefrom. The output of this AND gate only delivers a "1" if a "1" passes the data output DA of the input shift register PSW. The bits appearing at the output of the AND gate and assigned to the individual shift clock pulses arrive at the information input of the first memory part S and at the information input of the second memory part S. The effect of clock sequences derived from the shift clocks or in some other way ensures that the "1" in the first memory part S in the memory cell assigned to the position played in each case within the octave and in the second memory part S is recorded in the memory cell associated with the octave containing the sound being played. The respective stored contents of the two memory parts are erased by a common residual pulse, which is advantageously identical to the takeover pulses UE regulating the information input into the input shift register. Further details regarding the information input into the two memory parts S and S of the individual output parts V ₁ ... V _p are brought up in connection with FIG. 3.

A decoder D and D is assigned to each of the two memory parts S and S.

The first memory part S, which is used to hold the 4-bit word forming the sound address within the individual octave, accordingly consists of four individual shift register cells which are evaluated in parallel via the decoder D - a "one-of-twelve decoder ⁰ " The 12 tone names, c, cis, d, dis, etc. twelve decoder D having twelve signal outputs are accordingly assigned one AND gate U ₁ , U ₂ , .... or U ₁₂ per signal output. Gatter has two inputs. The second input is connected to one of the twelve sound signal inputs TSE in the manner already indicated, which in turn are each acted upon by one of the twelve sound frequency outputs of the sound frequency generator TOS and thus one of the sound frequencies of the highest octave. The output of each AND gate U ₁ to U ₁₂ is connected to an output of a common OR gate 0.

With regard to the effect of the part of FIG. 2 described so far, it should be noted that due to the respective content of the first storage part S one of the 12 outputs of the decoder D receives a "1", while the others keep the "0". Accordingly, the tone frequency from the highest octave supplied by the tone generator TOS via the tone signal input TSE assigned to the relevant decoder output appears at the output of the OR gate 0 mentioned.

The second memory part S is acted upon by a 3-bit word forming the address of the octave selected in each case via the actuated play key and also controls a decoder D in parallel operation. This decoder is designed as a "1-out-of-six decoder" and accordingly has six signal outputs , of which only one receives the level "1" due to the information present in the memory section S.

In general, with regard to the configuration of the second memory part S, it can be determined with any number q of the octaves provided in the manual that the second memory part S then has q memory cells, ie shift register cells, which act as a "one-of-q decoder" D are formed, and then this decoder D q controls the AND gates U ₁ to U _o .

In the example shown in FIG. 2, a total of 6 octaves are provided in the manual M, so that the memory section S has only three information outputs leading to the decoder D and the latter is designed as a "one-of-six" decoder.

, U

,.....

zugeordnet, indem der betreffende Dekoderausgang mit dem einen der beiden Eingänge des ihm zugeordneten UND-Gatters U

bis U

verbunden ist, während der andere Eingang des betreffenden UND-Gatters über einen dem vom ersten Dekodierer D und dem Tongenerator TAZ gesteuerten ersten ODER-Gatter 0 gesteuerten Frequenzteiler TT beaufschlagt wird. Die Gesamtheit der vom zweiten Dekodierer D beaufschlagten UND-Gatter U

bis U

liegt mit ihren Signalausgängen an je einem Eingang eines zweiten ODER-Gatters 0, dessen Signalausgang den Tonsignalausgang AU₁ bzw. AU₂,.... bzw. AUp bildet, wenn der betrachtete Ausgangsteil der Vermittlungsanlage VM deren erster Ausgangsteil V₁ bzw. deren zweiter Ausgangsteil V2..... bzw. deren letzter Ausgangsteil V_p ist.Each of the q outputs of the second decoder D is one of q AND gates U

, U

, .....

assigned by the relevant decoder output to one of the two inputs of the AND gate U

to U

connected while the other input of the concern is applied to the AND gate via a frequency divider TT controlled by the first decoder D and the tone generator TAZ controlled by the first OR gate 0. The totality of the AND gates U acted upon by the second decoder D.

to U

lies with its signal outputs on each input of a second OR gate 0, the signal output of which forms the audio signal output AU ₁ or AU ₂ , .... or AUp when the output part of the switching system VM in question has its first output part V ₁ or its second output part V2 ..... or the last output part is V _p .

The frequency divider TT controlled by the first OR gate 0 is now referred to as a tone divider, since it has the task of frequency dividing the tone signals belonging to the tones of the highest octave and supplied by the tone generator TOS, for the output AU ₁ and AU ₂ . ... or to generate certain tone vibrations.

bis U

- also im Beispielsfalle U

bis U

- ist an seinem zweiten Eingang über das erste ODER-Gatter 0 gesteuert und zwar in folgender Weise: Der Ausgang des ersten ODER-Gatters 0 liegt nicht nur am Eingang des Tonteilers TT sondern auch am zweiten Eingang des ersten der genannten UND-Gatter U

. Der Signalausgang der ersten Teilerstufe des Tonteilers TT liegt am zweiten Eingang des zweiten UND-Gatters U

, der Signalausgang der zweiten Teilerstufe am zweiten Eingang des dritten UND-Gatters U

usw., so daß der (q-1)-te, also im Beispiel der Fig. 2 der fünfte Teilerausgang, am zweiten Eingang des letzten (= q-ten) dieser UND-Gatter, also im Beispielsfall am zweiten Eingang des UND-Gatters U

liegt. Hierdurch ist jedes dieser vom zweiten Dekodierer D gesteuerten UND-Gatter U

bis U

je einer der im Manual M vorgesehenen Oktaven zugeordnet.Each of the AND gates U controlled by the second decoder D

to U

- So in the example case U

to U

- Is controlled at its second input via the first OR gate 0 in the following manner: The output of the first OR gate 0 is not only at the input of the sound divider TT but also at the second input of the first of the AND gates U mentioned

. The signal output of the first divider stage of the sound divider TT is at the second input of the second AND gate U

, the signal output of the second divider stage at the second input of the third AND gate U

etc., so that the (q-1) th, that is the fifth divider output in the example of FIG. 2, at the second input of the last (= q-th) of these AND gates, that is to say in the example at the second input of the AND- Gatters U

lies. This means that each of these second decoder D controlled AND gate U

to U

each assigned to one of the octaves provided in Manual M.

und an den Tonteiler TT geliefert. Durch die im zweiten Speicherteil S gespeicherte Adressierung der über das Manual M angewählten Oktave wird dann jeweils nur eines der UND-Gatter U

- U

, also im Beispielsfalle U

- U

, aktiviert, so daß bei Aktivierung von U

der angewählte Ton der höchsten Oktave, bei Aktivierung von U

der angewählte Ton der zweithöchsten Oktave und bei Aktivierung von U

der angewählte Ton aus der niedrigsten Oktave an das zweite ODER-Gatter 0 und damit an den Signalausgang AU des betreffenden Ausgangskanals - falls dieser durch ein entsprechendes Signal über seinen Steuereingang UE₁ bzw. UE₂ bzw..... UE vom Kanalwähler KW her angewählt worden ist - gegeben wird.Accordingly, due to the respective content of the first memory section S via the decoder D, the tone selected in each case is sent to the AND gate U as the tone of the highest octave

and delivered to the sound divider TT. Through the addressing of the octave selected via the manual M stored in the second memory part S, only one of the AND gates U is then respectively

- U

, in the example case U

- U

, activated so that when U

the selected tone of the highest octave, when U is activated

the selected tone of the second highest octave and when U is activated

the selected tone from the lowest octave to the second OR gate 0 and thus to the signal output AU of the relevant output channel - if this is signaled by a corresponding signal via its control input UE ₁ or UE ₂ or ..... UE from the channel selector KW has been selected - is given.

For the feedback control on the channel selector KW and for influencing the amplitude shaper AF ₁ to AF _p which is connected downstream of the output part V ₁ - V _{p in} each case, as already indicated in FIG. 1, a control input B ₁ or B ₂ or ....,respectively. B _p adding signals required. In order to obtain this, each of the inputs of the two decoders D and D controlled by the two memory parts S and S is connected to an input of a NOR gate NR, which only then outputs a signal via the reverse control input B ₁ or B ₂ etc. , when the two memory parts S and S of the output channel V ₁ or V ₂ , etc. are empty.

Furthermore, a comparison between the signal input and the signal output of each of the memory cells of the two memory parts of the individual output channel V ₁ to V _{p is} provided. This can e.g. B. via an equivalence gate E ₁ or E2 or ..... or ..... Ep (in the example case E ₁₀ ), the outputs of which are each at an input of an AND gate UL with p inputs (ie in the example case with 10 inputs). The entirety of these equivalence gates with the AND gate forms a comparator K ₁ or K _2, etc. A "1" at the output of the AND gate UL indicates that the sound address stored in the relevant output channel V ₁ to V _p is the same is the counter reading of the sound address counter TAZ.

Instead of the configuration of the individual comparators K ₁ to K _p just described by equivalence gates, the gates E ₁ to E _{p can} all also be exclusive OR gates. However, the AND gate UL must then be replaced by a corresponding NOR gate.

The task of the comparators K ₁ to K _p is, as the further considerations will show, diverse. One of the tasks is to indicate that the relevant output channel V ₁ to V _{p is} occupied. A common task of these comparators is to control the KW channel selector. This takes place with the intermediation of an OR gate OD, as can be seen from FIG. 3.

The various functions to be performed by the switching system VM are primarily controlled via the channel selector KW. The block diagram of a preferred embodiment of the channel selector KW is shown in FIG. 3.

From the embodiment of the switching circuit shown in FIG. 2 and the overall circuit given in FIG. 1, the sound address counter TAZ and the address memory parts S, S of the individual output parts V ₁ or V ₂ or .... or. V _p (in the example case p = 10, as already indicated above) as well as the equi-; valence gate E ₁ to E ₇ and the comparators K ₁ to K _p given by this controlled OR gate OR, since on the one hand they are directly exposed to the control effect by the channel selector KW and in turn have repercussions on the channel selector.

Each of the intended output channels Y ₁ to V _p has an AND gate A ₁ or A ₂ or .... or.

Ap (assigned to A ₁ to A ₁₀ in the example). Each of these AND gates A ₁ to A _p is controlled via two inputs, one of which is connected to the data input DE of the channel selector controlled by the input shift register PSW and the other to the output of an OR gate OD ₁ or OD ₂ or ....respectively. OD _p lies. The signal output of each of these AND gates A ₁ to A _p forms the relevant control output UE ₁ or UE ₂ or UE _p , which for additional control of the respectively assigned output part Y ₁ or V ₂ or ..... or . Y _{p of} the switching system VM is associated with the respective address memories S and S, which will be discussed in more detail below.

bis A

gesteuert.The OR gates OD ₁ or OD ₂ or ..... or respectively which control the individual AND gates A ₁ to A _p just mentioned. ODp has a first input, each of which is connected to the output of a further AND gate UG ₁ or UG ₂ or... Or. UG _p is applied immediately. A second signal input of each of these OR gates OD ₁ to ODp is through the signal output of a further AND gate A

to A

controlled.

bis A

liegt unmittelbar am Ausgang dieses NOR-Gatters NO, dessen Eingänge durch je einen der insgesamt vorgesehenen Ausgangsteile V₁ bis Y_p der Vermittlungsanlage VM über dessen Steuerausgang B₁ bis B_p beaufschlagt sind.The AND gates UG ₁ to UG _p mentioned in connection with the control of the OR gates OD ₁ to ODp have three inputs, with the exception of the AND gate UG ₁ assigned to the first output part or channel V ₁ , while that to the first channel V ₁ assigned AND gate has only two inputs. One of the inputs of all of these AND gates UG ₁ to UG _p is controlled by the control output B ₁ or B ₂ or Bp of the relevant output part or channel V ₁ or V ₂ (given by NOR gate NR). V _{p is} controlled, while another input of each of these AND gates is controlled via an inverter IV by a common NOR gate NO. One input each of the other AND gates A

to A

is located directly at the output of this NOR gate NO, the inputs of which are acted upon by one of the overall provided output parts V ₁ to Y _{p of} the switching system VM via its control output B ₁ to B _p .

The first output part V ₁ associated AND gate UG ₁ is therefore fully controlled by the control output B ₁ and by the NOR gates NO. The remaining AND gates from the group of AND gates UG ₁ to UG _p have, as just stated, three inputs, two of which are controlled in an analogous manner to the two inputs of the first of these AND gates UG ₁ . Accordingly, there is one input of each of these AND gates UG ₂ to UGp at the output of NOR gate NO via inverter IV and a second input at control output B ₂ or B ₃ or .... or. B _{p of} the respectively associated output part V ₂ or V ₃ or ..... or. V _{p of} the switching system VM. The third input of these AND gates UG ₂ to UG _p is via the output of a logic cell L ₁₂ or L ₂₃ or ..... ^b controlled by L _{(p-2), (P-1)} or L _(p-1), p.

The logic cell L _12, which is provided for controlling the third input of the second AND gate UG ₂ from the series of AND gates UG ₁ to UG _p, merely consists of an inverter, the input of g by the control output _B1 of the first _{off at} g _s partly V _{1 of} the switching system VM is controlled (which is also at the one input of the AND gate UG ₁ ) and its output is connected on the one hand to the third input of the AND gate UG ₂ (assigned to the second output part V ₂ ) and on the other hand, is located at the input of the next logic cell L _{23, which} is intended to act on the following AND gate UG ₃ .

The remaining _Lo gi _{kzellen L23} to L _(p-1) are equal to each other and each consist of an inverter _23a ^and L ^L ..... _34a or resp. L _{(p-1), pa} and a NOR gate with two inputs, the output of which forms the signal output of the logic cell in question and which is designated L _{23b '} L _34b , .... L _{(p-1), pb} (cf. Fig. 4). Circuit is default, the input of the inverter a concerned _Lo g _{ikzelle L23 and L34} respectively ..... respectively. L _{(p-1), p} with the output of the respectively preceding logic cell ^L ₁₂ ^{or L} ₂₃ ^{or ....} .bzw. L _{(p-2), (p-1)} connected, while its output is at the one input of the respectively associated NOR gate b. The other input of the _N OR gate b of the relevant logic cell L ₂₃ to L _(p-1), p is from the control output B ₁ or B ₂ or ..... or. B _{p of} that output part V ₃ or V ₄ or ..... or. V _p controlled to which the relevant AND gate from the series of AND gates UG ₁ to UG _{p is} assigned. The structure and the connection of the logic cells is based on the first three of these logic cells, namely the logic cells L _{12 '} ^L ₂₃ and ^L ₃₄ in FIG ^. 4 shown.

bis A

von UND-Gattern gesteuert, die ebenfalls jeweils einem der Ausgangskanäle V₁ bis Y_p der Vermittlungsanlage VM zugeordnet sind. Jedes dieser UND-Gatter A₁ bis A_p z.B. hat zwei Eingänge, von denen der eine ohne Zwischenschaltung eines Inverters oder eines anderen Bauelementes unmittelbar am Ausgang des NOR-Gatters NO liegt, während der andere am Ausgang je eines Komparators K

bis K

liegt. Die Komparatoren K

bis K

entsprechen im Aufbau den einzelnen Komparatoren K₁bis K . Sie sind einerseits durch einen gemeinsamen Referenzzähler RZ und andererseits durch je einen sog. Alterzähler AZ₁ bzw. AZ₂ usw. beaufschlagt und sprechen bei Gleicheit des Zählstandes jedes der p vorgesehenen und jeweils je einem der p Ausgangskanäle V₁ bis V_p fest zugeordneten Alterzähler AZ₁ bis AZp mit dem jeweiligen Zählstand des Referenzzählers RZ an.In the channel selector (or output part selector) KW shown in FIG. 3, the output of the NOR gate NO not only causes the AND gates UG ₁ to UG _p just discussed, but also a further group A, which has also already been mentioned

to A

controlled by AND gates, which are also each assigned to one of the output channels V ₁ to Y _{p of} the switching system VM. Each of these AND gates A ₁ to A _p, for example, has two inputs, one of which is located directly at the output of the NOR gate NO without the interposition of an inverter or another component, while the other is at the output of a comparator K

to K

lies. The comparators K

to K

correspond in structure to the individual comparators K ₁ to K. They are loaded on the one hand by a common reference counter RZ and on the other hand by a so-called age counter AZ ₁ or AZ ₂ etc. and speak at the same time as the count of each of the p intended and each one of the p output channels V ₁ to V _p permanently assigned AZ ₁ to AZp with the respective count of the reference counter RZ.

The mode of operation of the channel selector KW shown in FIGS. 3 and 4 will now be described. It is expedient to go into the formation of the individual memory parts S and S in the individual output channels V ₁ to V _p . It is recommended that the individual memory cells of these memory parts are formed from quasi-static shift register cells. In contrast to a shift register, however, no series connection of the memory cells is provided here, but each memory cell is provided for itself both on the input side and on the output side. All that is common is the loading via the manual M and the clock supply.

bis S

zugeordnet, wobei die vier-Zellen S₁ bis S₄ durch den ersten Teil des Tonadressenzählers TAZ und die drei Zellen S

bis S

durch den zweiten Teil des Tonadressenzählers TAZ gesteuert sind. Dementsprechend sind die Speicherzellen des ersten Speicherteils S zur Aufnahme der Bezeichnung des jeweils angespielten Tons innerhalb der einzelnen Oktave und die Speicherzellen des zweiten Speicherteils zur Aufnahme der Bezeichnung der Oktave, in der der jeweils angespielte bzw. anzuspielende Ton liegt, bestimmt. Demzufolge sind weiterhin die Signalausgänge der den ersten Speicherteil S bildenden Speicherzellen S₁ bis S₄ zur Beaufschlagung des ersten Dekoders D und die Ausgänge der den zweiten Speicherteil S bildenden Speicherzellen S

bis S

zur Steuerung des zweiten Dekodierers D vorgesehen. In Fig. 5, auf die vor der weiteren Beschreibung der Wirkungsweise eines Kanalwählers KW gemäß Fig. 3 eingegangen werden soll, sind lediglich die ersten drei Speicherzellen S₁ bis S₃ des ersten Speicherteils S dargestellt. Im Aufbau und in der Anschaltung entsprechend die übrigen Speicherzellen S₄ bzw. S₁ bis S₃ den in Fig. 5 dargestellten Speicherzellen im vollen Maße.In total, each of the output parts V ₁ to V _{p are} seven memory cells S ₁ to S ₄ and S

to S

assigned, the four cells S ₁ to S ₄ by the first part of the sound address counter TAZ and the three cells S

to S

are controlled by the second part of the sound address counter TAZ. Accordingly, the memory cells of the first memory part S are intended for receiving the designation of the particular sound being played within the individual octave and the memory cells of the second memory part for recording the designation of the octave in which the respective played or to be played sound is located. Accordingly, the signal outputs of the memory cells S ₁ to S ₄ forming the first memory part S for loading the first decoder D and the outputs of the memory cells S forming the second memory part S continue to be

to S

provided for controlling the second decoder D. 5, which will be discussed before the further description of the mode of operation of a channel selector KW according to FIG. 3, only the first three memory cells S ₁ to S _{3 of} the first memory part S are shown. In structure and in connection, the remaining memory cells S ₄ or S ₁ to S ₃ correspond in full to the memory cells shown in FIG. 5.

Each of the memory cells of the two memory parts S and S in each output channel V ₁ to V _p contains four transfer transistors t ₁ , t ₂ , t ₃ and t ₄ , each of which is provided by an enhancement-type MOS transistor. It also contains an inverter I and a NOR gate N. In addition, a so-called three-phase clock generator, that is to say a clock generator TG, which is capable of delivering three periodic pulse trains TM, TS and TSS having the same frequency is required. It is essential for the three pulse sequences that the individual. Pulses TS without overlap between two pulses arrange the sequence TM so that a gap is provided between each adjacent pulse TM and TS. In addition, the falling edges of the pulses from the sequence TSS coincide with the falling edge of one pulse each from the sequence TS while the pulses TSS are slightly delayed with respect to the pulses TS with respect to the rising edge. Since the input shift register PSW is also expediently constructed using quasi-static register cells, that is to say with cells corresponding to FIG. 5, the clocks TM, TS and TSS are also required here. Finally, the individual counter stages of the sound address counter TAZ and other counters used in the circuit, in particular also the reference counter RZ and the age counter AZ ₁ to AZp, are built up by means of master-slave flip-flops (in particular by means of one toggle flip-flop each) , for which the Impulse TM and TS are also required.

bis S

liegen gemeinsam am Ausgang des dem betreffenden Ausgangskanal V₁ bis Vp zugeordneten und den diesen steuernden Kanalwähler-Ausgang UE₁ bzw. UE₂ bzw......bzw. UE_p bildenden UND-Gatters A₁ bzw. A₂ bzw......bzw. Ap. Verwendet man die in Fig. 5 dargestellen Speicherzellen, so müssen die UND-Gatter A₁ bis Ap mit drei Signaleingängen jeweils ausgestattet werden. Zwei davon sind in der aus Fig. 3 ersichtlichen Weise beaufschlagt, während der dritte durch die die Speicherzellen S₁, S₂ usw. steuernden Takte TM gesteuert ist.As can be seen from FIG. 5, the data input of each of the memory cells forming the memory parts S and S is formed by the source terminal of the transfer transistor t ₁ , which is accordingly connected to the count output Q of the counter stage of the sound address counter TAZ assigned to it. The gates of the input transfer transistors t _{1 of} all of these memory cells S ₁ to S ₄ and S

to S

are common to the output of the respective output channel V ₁ to Vp and the channel selector output UE ₁ or UE ₂ or ...... or. UE _p forming AND gate A ₁ or A ₂ or ...... or. Ap. If the memory cells shown in FIG. 5 are used, the AND gates A ₁ to Ap must be equipped with three signal inputs each. Two of these are acted on in the manner shown in FIG. 3, while the third through which the store cells S ₁ , S ₂ etc. controlling clock TM is controlled.

The drain of the transistor t _{1 of} each of these memory cells S ₁ , S ₂ etc. lies on the one hand at the input of an inverter I, on the other hand on one current-carrying electrode of two transfer transistors t3 and t4. The output of the inverter is connected via a transfer transistor t2 to the one input of a NOR gate N, the second input of which is controlled by a general reset signal Re and the output of which forms the output of the relevant memory cell. The gates of the transfer transistors t2 of the memory cells are controlled together by the clock TS.

The transfer transistors t3 bridge with their source-drain path the series circuit of inverter I, transfer transistor t2 and NOR gate N. Their gate is controlled by the clock pulses TSS. The transfer transistor t4 lies with its source-drain path between the reference potential (ground) and the input of the inverter I. Its gate is acted upon by pulses L generated in a manner to be described. The output of the NOR gates N of each of the memory cells S ₁ , S ₂ etc. is, on the one hand, connected to the input of one of the two decoders D or D assigned to it. On the other hand, each of the seven memory cells is assigned one of the comparison gates E ₁ to E _{7 of} the comparator K ₁ or K ₂ etc. For this purpose, one input of the relevant equivalence gate E ₁ or E2 or ..... or. E _{7 of} the relevant comparator K ₁ , K ₂ ..... K _p to the source terminal of the input transfer transistor t ₁ and the other input to the output of the NOR gate N of the relevant memory cell. It should be noted that the gate of the transistors t ₄ controlling delete pulses L are given by selected from the sequence TM pulses. Their generation is still being discussed.

When the input transfer transistor t ₁ assigned to the individual memory cells in the memory parts S and S of the individual output channel V ₁ to V _{p is} activated at its source, the respective clock cell TS and TSS keep it in the respective memory cell until the "1" is erased by the erase transistor t4 by an erase pulse L and the memory cell is thus again available for writing a "1". Since the erase pulse L arrives simultaneously at all erase transistors t4 of the memory cells S ₁ , S ₂ , etc. associated with the respective output channel K ₁ to K _p , the two memory parts S and S ^{* of} the respective output channel are erased simultaneously, so that the channel again for one The TAZ tone address counter is available. This is indicated by the "1" at the control output S ₁ , S ₂ etc. of the relevant channel V ₁ , Y ₂ , ....

• 1. Jedesmal wenn durch die Ausgänge der Zählstufen im Tonadressenzähler TAZ der Zählstand erreicht wird, der in den beiden.Speicherteilen S und S jedes Ausgangskanals V₁ bis V_p eingespeichert ist, so erscheint am Ausgang des dem betreffenden Ausgangskanals V₁, V₂, usw. zugeteilten Komparators K₁, K₂ usw. eine "1". Dies gilt auch, wenn der Zählstand von TAZ gleich "0" ist und die betreffenden Speicherteile S und S*leer sind. In allen anderen Fällen liegt an den Ausgängen der einzelnen Komparatoren K₁ bis K_p eine "O".

In summary it can be stated:

• 1. Each time when the outputs of the counter stages in the sound address counter TAZ reach the count that is stored in the two memory sections S and S of each output channel V ₁ to V _p , V ₁ , V ₂ appears at the output of the relevant output channel. etc. assigned comparator K ₁ , K ₂ etc. a "1". This also applies if the count of TAZ is "0" and the relevant memory parts S and S * are empty. In all other cases there is an "O" at the outputs of the individual comparators K ₁ to K _p .

bis K

eine "1" gegeben ist.If the overall order is now activated, a general reset signal ensures that all output channels V ₁ to V _p , the age counters AZ ₁ to AZ _p assigned to them and the reference counter RZ are in the initial state, so that at the output of all comparators K ₁ to K _p and K

to K

a "1" is given.

If a game key in manual M is now pressed, a "1" is entered in the register cell of the input shift register PSW assigned to it, while the register cells assigned to the game keys which are not actuated retain the state "0". The clock pulses now starting now begin to shift the "1" generated on account of the pressed play key from the input shift register, each shift clock being counted in the tone address counter TAZ. Since the arrangement of the individual register cells in the input shift register PSW corresponds exactly to the arrangement of the game keys in the manual M, the number of shift clocks required until the appearance of the "1" at the data output of the input shift register PSW and the count set up with their help is Sound address counter TAZ is the address for the sound being played.

In order to transfer the count from this tone address counter TAZ into one of the output channels V ₁ to Vp, each of the inputs on AND gates A ₁ to A _p must be assigned a "1". Since the information from the input shift register PSW is also shifted out by the clock pulses TM, TS and TSS supplied by the clock generator TG when the shift register cells are auasistatic register cells, it is automatically ensured that when a "1" arrives via the data input DE of the channel selector KW at the input of the AND gates A ₁ to A _p also a "1" is pending at the input of this AND getter dedicated to the clock TM. Finally, since the AND gate UG _{1 has} only two inputs of all these AND gates UG ₁ to UG _p and one input of all of these AND gates with empty memories via the associated control output B ₁ or B ₂ or ..... respectively. B _p resistant with a "1" is applied and also to the second input of all AND gate UG ₁ to UG _p die.von the inverter IV supplied "1" is pending and the first output channel V ₁ associated AND gate UG ₁ alone has only two inputs, a "1" is only given at the output of this AND gate UG ₁ . This means that of the OR gates OD ₁ to OD _p only the OR gate OD _{1 has} a "1" at the output. Thus, the "1" from the input shift register PSW can exit only when the the first output channel V ₁ corresponding AND gate A address ₁ and the enable its output channel.

This means that the count present at the exit of the "1" from the input shift register PSW, that is to say the address of the sound played, is adopted in the memory cells of the first output channel V ₁ . The result of this is that the "0" at the output of the comparator K ₁ disappears, that, in addition, a "0" appears at the feedback control output B _{1 of} the first output part V ₁ instead of the "1" previously present, and that the second output channel V ₂ assigned AND gate UG ₂ all three inputs are assigned a "1". Because the "O" at the reverse control output B ₁ creates a "1" at the output of the logic cell L ₁₂ (given only by an inverter), so that a "1" is now pending at the output of UG ₂ , while the "1 "now disappeared at the output of UG ₁ and likewise at the outputs of the other AND gates UG ₃ to UG _p the appearance of a "1" is temporarily excluded.

Thus, when a next "1" is shifted out of the input shift register PSW, the count of TAZ which has been built up up to that point, and thus the tone address of the newly played tone, is adopted in the memory cells of the second output part V ₂ . In this way, the "1" disappears on the reverse control output B ₂ of this channel V _2, whereby via the logic cell _L23 ensured is that the three inputs of the next output channel V ₃ corresponding AND gate UG ₃ with a "1" to the arrival of the next "1" from the output shift register PSW remain applied. The game is repeated successively on the respectively following output channel V ₄ to V _p until the addresses of the first p played tones are stored in one of the output channels and - as long as the storage state continues - ensures this in the manner already described with reference to FIG. 2 that the tone frequency oscillation corresponding to the stored tone at the tone signal output AU ₁ or AU ₂ or .... or. AUp of the relevant output channel V ₁ or V ₂ or ..... or. V _{p is} delivered to the respectively assigned amplitude shaper AF ₁ to AF _p .

Now all channels V to V _p occupied by a respective sound is played ₁ so tight closure now be taken to ensure that the memory cells of at least one of the output channels V ₁ to V _p emptied through a low pulse. The generation of these branching deletion pulses representing TM pulses and their distribution to the individual output parts V ₁ to V _{p of} the switching system VM is now based on various aspects already mentioned. After the discussion of FIGS. 6 and 7, how the implementation takes place in the individual cases will be shown.

Each of the output channels V ₁ or ..... or. V _{p of} the switching system VM controls with its output each an amplitude former AF ₁ or ...... or AFp. The structure of such an amplitude shaper is shown in FIG.

After this, the output is AU ₁ or AU ₂ or .... or. AU _{p of} the relevant output part V1 or. V ₂ or ..... or V _p at the input of a shaping circuit FS, each. is combined with a counter Z. With regard to the details of the Formerschaltung.FS and the counter Z, reference can be made to DE patent application P 29 16 765.5 (VPA 79 P 1070). This patent application relates to a semiconductor circuit for the conversion of sequences of periodic AC signals with a signal input, a circuit part which effects the conversion and a signal output. Characteristic of this semiconductor circuit is the measure that the signal input E is connected to the one current-carrying connection of n identical transistors and each of these n transistors is combined with another such transistor to form a transistor pair by the other current-carrying connection of the first transistor of each transistor pair connected to the corresponding current-carrying connection of the associated further transistor and, moreover, is connected to the signal output A of the circuit via one of n different resistor combinations, in addition that the resistor combinations respectively assigned to the individual transistor pairs form a resistor network and that the first current-carrying electrodes of the second Transistors of all these pairs of transistors are at a common operating potential which is different from the reference potential (ground) and that finally to act on the control electrodes of the transistors A digital counter Zä having n count stages and controlled by a clock generator with counting pulses is provided and the n transistor pairs are connected to the signal outputs Q, Q of the digital counter Z in different ways from case to case.

The dual counter Z assigned to the individual amplitude shaper AF ₁ to AF _p is, as already stated in the patent application P 29 16 765.5 (VPA 79 P 1070), designed as an up-down counter. In the example, it has 7 counting stages in the form of seven flip-flop cells connected in series, e.g. B. toggle flip-flop cells, which are each provided with two inputs, ie a direct and an inverted input. Each of the two inputs of the individual flip-flop cells forming the counter Z is connected to the gate of a respective MOS transistor of the enhancement type. The drains of the two MOS transistors assigned to a counting stage in this way are connected to each other and each connected via a resistor to a dividing point of a voltage divider provided by 8 resistors connected in series in the example. The source connections of the one of the two MOS transistors each assigned to a counter stage are connected to a medium operating potential and the other transistor (assigned to the inverted input) with its source at the audio signal output AU ₁ or ..... or. AUp of the relevant AF ₁ or ..... or. AF assigned output channel V ₁ or ..... or. V _{p of} the switching system VM. Said voltage divider forms the signal output SG ₁ or ..... or. SGp of the relevant amplitude shaper and is at the other end at said average operating potential and thus at the source connections of the MOS transistors assigned to the inverted inputs of the individual counter stages.

The signal outputs of the p provided amplitude formers AF ₁ to AF _p are each at an input of a mixing stage Mi, the output of which controls a loudspeaker LT, that is to say an electro-acoustic transducer, via an amplifier V. Details regarding the previously described parts of the amplitude shaping circuit shown in FIG. 6 need not be discussed further in connection with the present semiconductor circuit.

The count input of the up-down counter Z of the amplitude shaper is supplied by a system containing at least one oscillator for generating the counting clocks, the system itself being back-controlled by certain counts of the counter Z in question. In the example, two such oscillators OZ ₁ and OZ _{2 are} provided, which are designed in a manner known per se such that they deliver square-wave oscillations with an adjustable frequency. Each of these two oscillators OZ ₁ and OZ ₂ controls a frequency divider TL ₁ and TL ₂ , which in the case of the example each have three divider stages F ₁ to F ₃ and F ₄ to F _{6 connected} in series in the form of flip-flop cells. In the example, master-slave flip-flops (toggle flip-flops) are used for the individual divider stages, so that the oscillations supplied by the respective oscillator OZ ₁ or OZ ₂ directly to one input of the first flip-flop cell and the other input is fed via an inverter (not specifically designated). These two oscillators OZ ₁ and OZ ₂ are all of those provided p amplitude formers together. They therefore control a total of p frequency dividers TL ₁ and p frequency dividers TL ₂ .

As a further component of the system for the generation of the counter clocks are at least two flip-flops and a back-controlled by certain counts of the binary counter Z via the flip-flops and the supply of the vibrations supplied by the divider stages as counter clocks for the counter Z, the logic is combined from AND gates and OR gates provided.

Here, in the in Fig. Exemplary case depicted 6 AND gates A ₁ to A with three signal inputs to mention first six _6, of which the three first the controlled from the oscillator OZ ₁ first divider TL ₁ and the last three which from the oscillator OZ ₂ controlled second divider TL _{2 are} assigned by an output, z. B. the non-inverted output, each divider stage F ₁ to F _{6 is} connected to an input of one of the AND gates a ₁ to a ₆ . Accordingly, e.g. B. the AND gates a ₁ to a _{3 to} the first divider TL ₁ and the AND gates a _{2 to} the second divider TL ₂ . The outputs of all these AND gates a ₁ to a ₆ each go to an input of a common OR gate od. The output of this OR gate od is connected to a further AND gate ug which has two inputs, one of which is through said OR gate od and the other being controlled by one output of a flip-flop cell FF. The flip-flop LFF is acted upon at both inputs by an output of the logic circuit Lo. This logic circuit Lo is in turn controlled by the up-down counter Z and by a start signal St, which is also provided for starting the RS flip-flop formed by the two NOR gates n and n ₂ .

, a

und a

( es können natürlich auch noch mehrere solcher UND-Gatter vorgesehen sein), die jeweils sieben Eingänge aufweisen und die zwecks Kodierung jeweils eines bestimmten Zählstandes des Zählers Z durch je einen der beiden Ausgänge Q und Q jeder Zählstufe von Z beaufschlagt sind. Dabei ist das UND-Gatter a

einem von "O" verschiedenen ersten Zählstand, das UND-Gatter a

einem zweiten - höheren-Zählstand und das UND-Gatter a

einem noch höheren dritten Zählstand von Z zugeordnet, der insbesondere dem höchsten Zählstand dieses Zählers Z entspricht. Dem dritten UND-Gatter a

ist ausgangsseitig eine Differenzierstufe DS₂ zugeordnet, während die Steuerung durch die beiden anderen UND-Gatter a

und a

ohne eine solche Differenzierstufe arbeitet.The up-down counter Z has seven counting stages in the example. It controls both with the counter reading "0" and with its highest count - the logic circuit Lo and with the highest count as well as with two further counts one of the three AND gates a

, a

and a

(Of course, several such AND gates can also be provided), which each have seven inputs and which each have one of the two outputs Q and for the purpose of coding a specific count of the counter Z. Q Z are applied to each counter stage. The AND gate is a

a first count other than "O", the AND gate a

a second - higher count and the AND gate a

assigned an even higher third count of Z, which corresponds in particular to the highest count of this counter Z. The third AND gate a

a differentiation stage DS _{2 is} assigned on the output side, while control by the other two AND gates a

and a

works without such a differentiation stage.

liegt an einem Eingang des bereits genannten NOR-Gatters n₁, das zusammen mit dem NOR-Gatter n₂ ein RS-Flip-Flop bildet. Hierzu ist sein Ausgang an einem Eingang des NOR-Gatters n₂ und der Ausgang des NOR-Gatters n₂ an einen Eingang des NOR-Gatters n₁ gelegt. Das erste NCR-Gatter n₁ hat noch einen dritten Eingang, der an einem durch Rücksetzsignale gesteuerten Reseteingang der Schaltung gemäß Fig. 6 liegt. Durch diesen Reseteingang Re ist außerdem ggf. der Rücksetzeingang des Zählers Z beaufschlagt, so daß dieser beim Auftreten eines Rücksetzimpulses auf den Zählstand "O" umschaltet (falls der Zähler Z nicht bereits vorher durch die Rückzählphase auf "O" geschaltet ist). Ein-durch ein Startsignal gesteuerter Eingang St liegt über eine Differenzierstufe DS₁ einerseits an der Logik Lo und andererseits an einem zweiten Eingang des mit dem NOR-Gatter n₁ kreuzgekoppelten NOR-Gatters n₂. Der Ausgang des durch die NOR-Gatter n₁ und n₂ gebildeten RS-Flip-Flops ist mit dem Ausgang des NOR-Gatters n₁ identisch. Er liegt an je einem Eingang der durch die beiden letzten Teilerstufen F₃ und F₆ der beiden Teiler TL₁ und TL₂ beaufschlagten UND-Gatter a₃ und a₆.The AND gate a

is located at an input of the aforementioned NOR gate n ₁ , which forms an RS flip-flop together with the NOR gate n ₂ . For this purpose, its output is connected to an input of the NOR gate n ₂ and the output of the NOR gate n ₂ to an input of the NOR gate n ₁ . The first NCR gate n _{1 also} has a third input which is connected to a reset input of the circuit according to FIG. 6 which is controlled by reset signals. Through this reset input Re, the reset input of the counter Z is also possibly acted on, so that it switches to the count "O" when a reset pulse occurs (if the counter Z has not previously been switched to "O" by the countdown phase). On-by a start signal Controlled input St is connected via a differentiating stage DS ₁ to logic Lo on the one hand and to a second input of NOR gate n ₂ cross-coupled to NOR gate n ₁ on the other. The output of the RS flip-flop formed by the NOR gates n ₁ and n ₂ is identical to the output of the NOR gate n ₁ . It is connected to one input of each of the AND gates a ₃ and a ₆ acted upon by the last two divider stages F ₃ and F _{6 of} the two dividers TL ₁ and TL ₂ .

, ein zweiter Eingang des anderen NOR-Gatters n₄ am Ausgang des UND-Gatters a

und ein dritter Eingang des NOR-Gatters n₄ am Reset- eingang Re der Schaltung. Der Ausgang des zweiten RS-Flip-Flops n₃, n₄ ist durch den Ausgang des zweiten dieser NOR-Gatter, also durch den Ausgang des Gatters n₄ gegeben. Er liegt an je einem Eingang der durch die beiden vorletzten Stufen F₂ bzw. F₄ der beiden Teiler TL₁ und TL₂ beaufschlagten UND-Gatter a₂ bzw. a₅.A second RS flip-flop is connected through the two NOR gates n ₃ to the output of the other NOR gate. A second input of the NOR gate n ₃ is at the output of the AND gate a

, a second input of the other NOR gate n ₄ at the output of the AND gate a

and a third input of the NOR gate n ₄ at the reset input Re of the circuit. The output of the second RS flip-flop n ₃ , n ₄ is given by the output of the second of these NOR gates, that is to say by the output of the gate n ₄ . It is connected to an input of the AND gates a ₂ and a _5, respectively, which are acted upon by the two penultimate stages F ₂ and F _{4 of} the two dividers TL ₁ and TL ₂ .

und ein weiterer Eingang des anderen NOR-Gatters n₆ durch den Ausgang des UND-Gatters a

über eine Differenzierstufe DS₂ gesteuert. Ein dritter Eingang des NOR-Gatters n₆ liegt am Reseteingang Re. Sein Ausgang bildet den Ausgang des dritten RS-Flip-Flops n₅, n₆. Er liegt an je einem Eingang der durch die ersten Teilerstufen F₁ bzw. F₄ beaufschlagten UND-Gatter a₁ bzw. a₄.A third RS flip-flop is provided by the two NOR gates n ₅ and n ₆ , of which in turn one input is fed back to the output of the other gate. Another input of gate n ₅ is through the output of second AND gate a

and another input of the other NOR gate n ₆ through the output of the AND gate a

controlled by a differentiation stage DS ₂ . A third input of the NOR gate n ₆ is at the reset input Re. Its output forms the output of the third RS flip-flop n ₅ , n ₆ . It is located at an entrance through the first Divider stages F ₁ and F _{4 act on} AND gates a ₁ and a ₄ .

gesteuerten Differenzierstufe DS₂ liegt ferner am einen Eingang einer weiteren Flip-Flopzelle AFF, deren zweiter Eingang am Reseteingang Re angeschaltet ist. Der beim Auftreten eines Signals am Ausgang der Differenzierstufe DS₂ den Pegel "1" erhaltende Ausgang des Flip-Flops AFF liegt an je einem letzten Eingang der durch den ersten Teiler TL₁ gesteuerten UND-Gatter a₁ bis a₃ und über einen Inverter IR an je einem letzten Eingang der durch den zweiten Teiler TL₂ gesteuerten UND-Gatter a₄.bis a₆.The output of the through the AND gate a

The controlled differentiating stage DS ₂ is also connected to one input of a further flip-flop cell AFF, the second input of which is connected to the reset input Re. The output of the flip-flop AFF, which receives the level "1" when a signal occurs at the output of the differentiating stage DS _2, is connected to a last input of the AND gates a ₁ to a ₃ controlled by the first divider TL ₁ and via an inverter IR at a last input of the AND gates a _4. to a ₆ controlled by the second divider TL ₂ .

The same output of the flip-flop cell AFF is also connected to the input of the counter Z which effects the conversion of the counter Z from the up to the down-counting operation. The other output of the flip-flop cell AFF can be used instead of the inverter IR to switch the third inputs of the To control AND gates a ₄ to a ₆ . The inverter IR is then not required.

dem höchsten, das UND-Gatter u

dem niedrigsten Zählstand, also dem Zählstand "0" zugeordnet ist. Das UND-Gatter u

kann mit dem UND-Gatter a

identisch sein, wobei.allerdings im Falle der Logik Lo die Differenzierstufe DZ₂ nicht mit einbezogen ist. Da im Beispielsfall der Zähler Z sieben Zählstufen, also sieben hintereinandergeschaltete Toggle-Flip-Flopzellen, aufweist, haben die UND-Gatter u₁ und u2 jeweils sieben Eingänge, die im Falle des UND-Gatters u₁ mit den den Zählstand anzeigenden Ausgängen Q und im Falle des UND-Gatters u₂ mit den die hierzu invertierten Signale führenden Ausgängen Q des Zählers Z jeweils verbunden sind.The embodiment of the logic circuit Lo shown in FIG. 7 has two AND gates controlled by the two extreme states of the up-down counter Z, the AND gate u

the highest, the AND gate u

is assigned to the lowest count, ie the count "0". The AND gate u

can with the AND gate a

be identical, although in the case of logic Lo the differentiation stage DZ _{2 is} not included. Since in the example the counter Z has seven counting stages, that is to say seven toggle flip-flop cells connected in series, the AND gates have u ₁ and u2 each have seven inputs, which in the case of the AND gate u ₁ with the outputs Q indicating the count and in the case of the AND gate u ₂ with the outputs carrying the signals inverted for this purpose Q of the counter Z are each connected.

The output of the counting state "O" AND gate u ₂ is connected via a differentiating stage DS3 to the one input of an OR gate org ₂ , the other input of which is controlled by a further AND gate ud ₃ , and the output of which is thus to the Flip-flop LFF is created so that this blocks the AND gate ug controlling the supply of counting pulses to counter Z. The first-mentioned AND gate ud ₃ is acted upon on the one hand by the AND gate u1 dedicated to the highest count of the counter Z (which is preferably identical to the AND gate a ₃ ) and on the other hand by a signal supplied via a control input P / S. In the presence of such a signal (or its absence) it is achieved that the sound amplitude maintains its constant amplitude as long as the signal continues even when the play key is released.

The other input of the flip-flop cell LFF is controlled by a further OR gate org ₁ , which, in contrast to the OR gate org _1, ensures the supply of counting pulses to the counter Z via the AND gate ug. The OR gate org ₁ is also controlled by two AND gates ud ₁ and ud ₂ . One input of the AND gate ud _{2 is located} at the control input P / S already mentioned, while the other input is acted upon by an input TLO. A signal is given to the input TLO when the AF ₁ for the current loading of the amplitude shaper under consideration until AF _p responsible game button in manual M is released. The generation of this signal, which controls the input TLO, will be discussed after the pending further consideration of the channel selector KW.

The other AND gate ud ₁ is connected with one input to the AND gate u2 assigned to the count "0" of the counter Z and with the other input to the input St carrying the start signal, through which the NOR gate n _{2 is also} controlled . Since when switching on the channel V ₁ or V ₂ or ..... or. V _p and the AF or AF ₂ or ..... or. AFp the up-down counter Z is at the count "O", the OR gate org _{1 is} activated by the start signal supplied via the start input St and thus the flip-flop LFF is brought into an operating state in which the downstream AND Gate ug is permeable for the count clocks supplied by the output of the OR gate od. The state is evidently ended when, due to the downward counting process in the counter Z, the count "O" is reached - and thus by the AND gate u ₂ by means of it. switched differentiating stage DS _3, a signal is given to the OR gate org ₂ , through which the flip-flop LFF tilts into the other position and blocks the AND gate ug.

In the same sense, when the AND gate u ₁ and the signal input P / S are coupled to the AND gate u ₁ coupled to the highest count of the counter Z, the AND gate ud3, since this then also throttles the AND gate ug via the OR gate org ₂ . In the same way as the AND gate ud _1, the AND gate ud ₂ acts on it OR gate org ₁ and thus on the flip-flop LFF as soon as it is present at its one input at the same time as a play signal in the manual M which is released when the respective play button is released and is fed through the input TLO and at the other input by a signal P / S (e.g. generated by a pedal ').

The differentiating stages DS ₁ , DS ₂ and DS ₃ can advantageously be designed in accordance with German patent application P 28 45 379.4 (VPA 78 P 1191), since these trigger the immediate creation of a short defined pulse R due to a controlling pulse RZ. The task of these differentiation stages DS ₁ to DS ₃ is to be seen in the present case in that an extremely short pulse of defined length is triggered when a control pulse of any length occurs.

The start signals St are advantageously the takeover signals UE ₁ to UE _p which are used to start the output part V ₁ to V _{p of} the switching system VM which is assigned to the relevant amplitude shaper AF ₁ to AF _p and which are generated by the associated AND gate A ₁ to A _{p of} the channel selector KW used, so that the output of the relevant output part V _{1 or} ..... _{b or} V _p associated with AND gate A ₁ or ..... or A _p for controlling the logic Lo in the downstream Amplitude former AF ₁ or ..... or. AF _{p is used} for the delivery of the start signal St. As already stated, they are brought to the NOR gate n ₁ as well as to the AND gate ud ₁ in the logic circuit Lo via the differentiating stage DS ₁ .

zugeordneten Zählstand hoch. Währenddessen wird aufgrund der Steuerung der Formerschaltung FS durch den Zähler Z die von der Formerschaltung an die Mischstufe MI weitergegebenen und . von dem jeweils zugeordneten Ausgangsteil V bis V gelieferten tonfrequenten Signale sukzessive gesteigert, wobei infolge der verhältnismäßig langsamen Aufzählung des Zählers Z die Amplitude nur verhältnismäßig langsam gesteigert wird.Due to the start signal St, a "1" appears at the output of the NOR gate n ₁ due to the specified conditions, which reaches the one of the three inputs of the AND gate a ₃ controlled by the third divider stage F _{3 of} the divider TL ₁ . Furthermore, the flip-flop AFF is in a state in which the AND gate a. Is due to the initial state of the counter Z (be it due to a previous countdown to the count "0" or be it due to a reset signal given via the reset input Re) ₁ to a ₃ can be subjected to a "1" by this flip-flop AFF. Finally, the two oscillators OZ ₁ and OZ _{2 are in} continuous operation (they can be switched on, for example, by the start signal St). Thus pass through the AND gate a ₃ , the OR gate od and the AND gate ug counting pulses, which appear at a relatively low frequency because they come from the last stage F _{3 of} the divider TL ₁ . These counts gradually count the counter Z up to that of the AND gate a

assigned count high. Meanwhile, due to the control of the shaping circuit FS by the counter Z, the shaping circuit FS passes on the mixing stage MI and. sound frequency signals supplied from the respectively assigned output part V to V are successively increased, the amplitude being increased only relatively slowly due to the relatively slow enumeration of the counter Z.

mit dem Erreichen des ihm zugeordneten Zählstandes, des Zählers Z an, so verschwindet die "1" am Ausgang des NOR-Gatters n₁. Dagegen erscheint nun am Ausgang des NOR-Gatters n₄ eine "1". Dies hat zur Folge, daß die Zufuhr der von der Teilerstufe F₃ gelieferten Zählimpulse gestoppt und stattdessen die Zufuhr von aus der Teilerstufe F₂ stammenden Zählimpulsen über das UND-Gatter a₂ ermöglicht wird, da sich an dem Betriebszustand der beiden Flip-Flops LFF und AFF nichts geändert hat und auch die Eingänge St und Re nicht mehr beaufschlagt wurden. Aufgrund der nunmehr mit höherer Frequenz als bisher erscheinenden Zählimpulse werden die Amplituden der von der Formerschaltung FS gelieferten Tonsignale rascher als bisher größer, und zwar solange, bis das durch den höheren Zählstand des Zählers Z gesteuerte UND-Gatter a₂ anspricht.Now speaks the AND gate a

when the counter Z assigned to it is reached, the "1" at the output of the NOR gate n ₁ disappears. In contrast, a "1" now appears at the output of NOR gate n ₄ . As a result, the supply of the of the divider stage F ₃ stopped counting pulses and instead the supply of count pulses originating from divider stage F _{2 is} enabled via the AND gate a ₂ , since nothing has changed in the operating state of the two flip-flops LFF and AFF and also the inputs St and Re were no longer charged. Due to the counting pulses now appearing at a higher frequency than before, the amplitudes of the sound signals supplied by the shaping circuit FS become larger faster than before, until the AND gate a ₂ controlled by the higher count of the counter Z responds.

When the AND gate a ₂ responds, the "1" at the output of the NOR gate n ₄ disappears and instead appears at the output of the NOR gate n ₆ . The supply of counting clocks from divider stage T _{2 is} thus ended and the AND gate a _{1 is} made continuous for the counting clocks originating from first divider stage F ₁ . As a result, the increase in amplitude of the tone-frequency signals supplied at the output of the shaping circuit FS progresses even more rapidly than hitherto. When the count assigned to the AND gate a _{3 is reached} , the "1" at the output of the NOR gate n ₆ disappears. The flip-flop AFF is also flipped. This changes the counting direction in the counter Z. In addition, the effects of the AND gates a ₁ to a ₃ acted upon by the oscillator OZ _{1 become} effective for the delivery of the counting cycles by the AND gates a ₄ to a ₆ acted upon by the oscillator OZ ₂ replaced.

, a

und a3 durch den Zähler Z in entsprechender Weise abgeändert werden muß, bzw. diese UND-Gatter durch entsprechend anders gesteuerte UND-Gatter ersetzt werden müssen. Die Darstellung.der hierzu erforderlichen Schaltmittel in Wort und Bild verlangt im grundegenommen nichts anderes als die Verwendung von durch UND-und ODER-Kombinationen realisierte Steuermittel, die aufgrund eines Umschalt- bzw. zweiten Startsignals die entsprechende Umstellung der durch die NOR-Gatter n₁ bis n₆ gebildeten drei RS-Flip-Flops und/oder der diese beaufschlagenden UND-Gatter bewirken. Bei der in Fig. 6 dargestellten Anschaltung dieser drei RS-Flip-Flops müßte dann wieder das NOR-Gatter n₁ zur Einleitung der Abklingphase derart geschaltet werden, daß an seinem Ausgang eine "1" erscheint, die mit dem Erreichen des dem UND-Gatter a

entsprechenden Zählstandes von Z wieder verschwindet, während zur gleichen Zeit die "1" am Ausgang von n₄ erscheint. Beim Erreichen des dem UND-Gatter a

zugeordneten nächst niedrigeren Zählstandes von Z verschwindet die "1" am Ausgang des NOR-Gatters n₄. Stattdessen tritt die "1" am Ausgang des NOR-Gatters n₆ auf und verschwindet wieder, sobald im Zähler Z der nunmehr dem UND-Gatter a

zugeordnete Zählstand "O" erreicht ist. Es ist klar, daß auch bei der Erzielung dieses "Nachhalleffekts" oder auch Soustaineffekts das UND-Gatter ug für die vom ODER-Gatter od gelieferten Zähltakte durchlässig sein muß und somit an dem ODER-Gatter org₂ keine "1" anliegen darf. Die hierzu erforderlichen Bedingungen lassen sich unmittelbar aus Fig. 7 ablesen. Zu erwähnen ist noch, daß man die an dem nicht mit dem UND-Gatter ug verbundenen Ausgang erscheinenden Signale als Zeichen dafür verwenden kann, daß der Zähler den Zählstand "O" hat und somit aufnahmebereit ist.'First, however, only the state "0" is present at the outputs of the NOR gates n ₁ , n ₄ and n _6, which also control these AND gates a ₄ to a ₆ , so that for the time being none Counting cycles arrive at the counter Z and the amplitude of the audio frequency signals reaching the mixing stage Mi via the shaping circuit FS maintain their highest value. In order to end this state, the RS flip-flops formed by the NOR gates n ₁ to n _{6 must come} into action again, the flip-flop n ₁ , n ₂ now having a higher counter reading than the flip -Flop n ₃ , n ₄ and the flip-flop n ₅ , n ₆ must end its action at the count "0". This means that the control of the AND gates a

, a

and a3 must be modified in a corresponding manner by the counter Z, or these AND gates must be replaced by correspondingly differently controlled AND gates. The representation of the switching means required for this in word and image basically requires nothing other than the use of control means implemented by AND and OR combinations, which, on the basis of a changeover or second start signal, the corresponding changeover by the NOR gates n ₁ to n ₆ formed three RS flip-flops and / or the AND gate acting on them. In the connection of these three RS flip-flops shown in FIG. 6, the NOR gate n ₁ would then have to be switched again to initiate the decay phase in such a way that a "1" appears at its output which, when the AND and Gate a

corresponding count of Z disappears again, while at the same time the "1" appears at the output of n ₄ . Upon reaching the AND gate a

assigned the next lower count of Z, the "1" at the output of the NOR gate n ₄ disappears. Instead, the "1" occurs at the output of NOR gate n ₆ and disappears again as soon as in counter Z the AND gate a

assigned count "O" is reached. It is clear that even when this "reverberation effect" or sous-effect is achieved, the AND gate must be permeable for the counting cycles supplied by the OR gate od and therefore no "1" may be applied to the OR gate org ₂ . The conditions required for this can be read directly from FIG. 7. It should also be mentioned that the signals appearing at the output not connected to the AND gate below can be used as a sign that the counter has the count "O" and is therefore ready for recording. '

At the end of the description of the channel selector KW according to FIG. 3, reference should be made to FIG. 8, in which the connection of the reference counter RZ already shown in FIG. 3 and the age counter AZ ₁ to AZ _p (in the example p is again equal to 10) is shown is. The control AST of the age counters AZ ₁ to AZ _p , which is only indicated in FIG. 3, that is to say in the example case AZ ₁ to AZ _10, is shown in FIG. 8.

Each age counter AZ ₁ to AZ is assigned to one of the intended output channels V ₁ to V _{p of} the switching system VM. Its counting input is in the embodiment shown in FIG. 8 by the output of an AND gate UL ₁ or UL ₂ or ..... or. UL _p applied. Furthermore, each of the age counters AZ ₁ to AZ _p can be reset to the count "0" by an erase signal L ₁ to L _p supplied by the respectively assigned amplitude shaper AF ₁ to AF _p when it returns to the initial state and by a general (not shown) reset signal "be reset.

bis K

vorgesehen, der bereits erwähnt wurde und der bei Gleichheit des Zählerstandes des Referenzzählers RZ mit dem einzelnen Alterszähler AZ₁ bzw. AZ₂ usw. anspricht, d. h. also eine "1" abgibt.All age counters have the same number of count levels, which is also common for the age counters AZ ₁ to AZ _p sam assigned reference counter RZ applies. There is a comparator K between the reference counter RZ and each of the intended age counters AZ ₁ to AZ _p

to K

provided, which has already been mentioned and which, if the counter reading of the reference counter RZ is identical with the individual age counter AZ ₁ or AZ ₂ etc., responds, that is to say outputs a "1".

The AND gates UL ₁ to UL allocated to the individual age counters AZ ₁ to AZ _p provide the counting clock for the respective age counter. In the example, these AND gates UL ₁ to UL _p each have three inputs. One of these is acted upon by the OR gate OD shown in FIG. 3 and controlled by the comparators K ₁ to K _{p of} the individual output channels V ₁ to V _p , which always supplies a "1" when at least one of the output channels V ₁ to V _{p is} occupied.
(If you want to have the age counters or their clock supply only activated when all channels V ₁ to V _{p are} occupied, you have to replace the OR gate OD with a corresponding AND gate.)

A circuit arrangement TLO ₁ to TLO _{p is also} assigned to each of the output channels V ₁ to V _p and thus to each of the age counters AZ ₁ to AZ _p . B. can be configured according to FIG. 9 and which responds when the game button causing the application of the individual channel V ₁ to V _p and thus the respectively assigned age counter AZ ₁ to AZ _{p is} released again. It supplies a signal which is used to control the second input of the AND gate UL ₁ or UL ₂ etc. of the individual age counters AZ ₁ , AZ ₂ etc. is provided so that the relevant age counter AZ ₁ or AZ ₂ etc. receives counting pulses only when the key is released or the effect of the circuit parts mentioned is blocked by a (common signal) P / S. The third inputs of the individual AND gates UL ₁ to UL are acted upon together by counter clocks. These counting cycles can e.g. B. can be supplied by the input shift register PSW controlling clock TG.

As a result of the connection of the AND gates UL ₁ to ULp just described, it is understandable that that counter has the highest count - at which the continuous signal supplied by the switching element TLO is the longest effective.

The outputs of the AND gates UL ₁ to ULp assigned to the individual age counters AZ ₁ to AZ _{p are} each connected to an input of a common OR gate oe, the output of which supplies the counting clocks for the reference counter RZ. Thus, each of the counting cycles supplied to one of the age counters AZ ₁ to AZp also serves as a counting cycle for the reference counter RZ.

bis K

vorgesehen. Der Ausgang dieser Komparatoren K

bis K

dient einerseits zur Steuerung je eines UND-Gatters A

bis A

. Er dient andererseits mittels eines Inverters IR₁ bzw. IR₂ bzw. .... IR_p zur Steuerung des Reseteinganges des Alterszählers AZ₁ bzw. AZ₂ usw., der zu diesem Zweck vom Ausgang des zugehörigen Inverters IR₁ bis IR_p über eine Differenzierstufe ds₁ bzw. ds₂ bzw.....bzw. dsp mit einem kurzen Res etimpuls beaufschlagt wird wenn die "1" am zugehörigen Komparator K

bzw. K

usw. verschwindet. Der Ausgang der einzelnen von den Komparatoren K

bis K

beaufschlagten Inverter IR₁ bis IR_p liegt außerdem an je einem Eingang eines allen Komparatoren K

bis K

gemeinsam zugeteilten UND-Gatters an₁.As already mentioned above, there is a comparator K between the reference counter RZ and each of the age counters AZ ₁ to AZ _p

to K

intended. The output of these comparators K

to K

serves to control one AND gate A each

to A

. On the other hand, it is used by means of an inverter IR ₁ or IR ₂ or .... IR _p to control the reset input of the age counter AZ ₁ or AZ ₂ etc., which for this purpose from the output of the associated inverter IR ₁ to IR _p a differentiation level ds ₁ or ds ₂ or ..... or. dsp a short reset pulse is applied when the "1" on the associated comparator K

or K

etc. disappears. The output of each of the comparators K

to K

acted on inverter IR ₁ to IR _p is also at one input of each of the comparators K

to K

shared AND gate to ₁ .

The reference counter RZ is designed as an up-down counter, which is switched on the basis of a signal supplied by the AND gate at ₁ in the opposite counting direction and which in the absence of such a signal immediately tilts back into the up-counting direction. The output of the AND gate at ₁ is also at an input of a further AND gate at ₂ , the output of which is at a further input of the OR gate OR oe controlled by the AND gates UL to ULp and the other input of which is by clock pulses, e.g. B. is controlled by the clocks TM.

Thus, if a reversal of the counting direction of the reference counter RZ occurs as a result of a "1" at the output of the AND gate at ₁ , then this receives via the AND gate at ₂ as long as counting cycles until one of the comparators again, namely the comparator that corresponds to the age counter with the highest count is assigned a "1" at its input. so that the equality of the count of the reference counter with the count of one of the age counters AZ ₁ to AZ _{p is} restored.

bis K

, also das Erscheinen einer "1" an ihrem Ausgang besagt, wie wiederholt betont, daß Gleichheit zwischen dem Zählstand des Referenzzählers RZ und dem Zählstand eines Alterszählers herrscht. Eine Ausnahme bildet der Ausgangszustand, da dann nicht nur ein Komparator, sondern alle eine "1" liefern, so daß schon aus diesem Grunde der Referenzzähler RZ zunächst auf den Zählstand "0" gehalten ist. Nach der Beaufschlagung des ersten Ausgangskanals V1 spricht das ODER-Gatter OD* an. Der erste Zähltakt für einen Alterszähler AZ₁ bis AZp ist aber erst dann fällig, wenn einer der Schaltungsteile TLO₁ bis TLO_p anspricht. Wegen der Anhängigkeit der Zähltakte an den dritten Eingängen der UND-Gatter UL₁ bis UL_p, die von einem gemeinsamen Taktgeber stammen und daher synchron zueinander sind, erscheinen dann am Ausgang desjenigen UND-Gatters UL₁ bzw. UL₂ bzw.....bzw. ULp die Zähltakte, das durch das Signal TLO, also durch den jeweils zugeordneten Indikator TLO₁ bis TLO_p, beaufschlagt ist. Diese Zähltakte gelangen dann sowohl an den Zähleingang des zu dem UND-Gatter UL₁ bis UL_p, das nunmehr für die Zähltakte durchlässig ist, gehörenden Alterszähler als auch über das ODER-Gatter oe an den Zähleingang des Referenzzählers RZ, so daß sich in beiden Zählern derselbe Zählstand aufbaut.The response of the individual comparators K

to K

, ie the appearance of a "1" at its output means, as repeatedly emphasized, that there is equality between the count of the reference counter RZ and the count of an age counter. An exception is the initial state, since then not only one comparator, but all deliver a "1", so that for this reason alone the reference counter RZ is initially kept at the count "0". After the first output channel V1 has been applied, the OR gate OD * responds. However, the first counting cycle for an age counter AZ ₁ to AZp is only due when one of the circuit parts TLO ₁ to TLO _p responds. Because of the dependency of the counting clocks on the third inputs of the AND gates UL ₁ to UL _p , which originate from a common clock generator and are therefore synchronous to one another, UL ₁ or UL ₂ or .... then appear at the output of that AND gate. .respectively. ULp is the counting clock which is acted upon by the signal TLO, that is to say by the respectively assigned indicator TLO ₁ to TLO _p . These counting cycles then arrive both at the counting input of the age counter belonging to the AND gate UL ₁ to UL _p , which is now permeable to the counting clocks, and also via the OR gate oe at the counting input of the reference counter RZ, so that in both Counters builds up the same count.

Is now loaded a second channel and the loading of this channel, for. B. the channel V ₂ causing game button released, the assigned to this channel age counter, so in the example of the Alterzähj he AZ ₂ , now also the synchronous counting pulses, so that there are AZ ₂ in this age counter and in all others to a busy output channel belongs to and counts by one of the signals TLO age counter builds an individual count, which is lower, the later the age counter in question was acted upon by the TLO signal assigned to it.

usw., so daß der Referenzzähler RZ auf den Zählstand des jeweils den nächsthöchsten Zählstand aufweisenden Alterszählers, z. B. des Alterszählers AZ₂ zurückgesetzt wird. Dann spricht der diesem Alterszähler, z. B. dem Alterszähler AZ₂ zugeordnete Komparator, also der Komparator K₂, mit einer "1" an seinem Ausgang an, so daß die Rückzählung des Referenzzählers RZ abrupt beendet wird. Die folgenden Zählimpulse werden dann in positivem Sinne sowohl auf den nunmehr den höchsten Zählstand aufweisenden Alterzähler, z. B. AZ₂, und den Referenzzähler RZ gegeben, bis auch AZ₂ durch ein vom zugehörigen Kanal V₂ bzw. dem Amplitudenformer AF₂ gelieferte Löschsignal L₂ auf den Zählstand "O" zurückgesetzt wird. Ist beispielsweise der Alterszähler AZ₅ der Alterszähler mit dem nächsthöchsten Zählstand,-so wiederholt sich der beschriebene Vorgang mit diesem, indem der Referenzzähler auf den Zählstand dieses Alterszählers AZ₅ zurückgesetzt, dann durch positive Beaufschlagung mit den gemeinsamen Zähltakten synchron mit dem neuen Alterszähler AZ₅ solange hoch gezählt wird, bis durch einen vom Amplitudenformer AF₅ stammendes Löschsignal L₅ auch der Zählstand dieses Zählers gelöscht und der Referenzzähler RZ auf einen neuen Zählstand, nämlich den nächsthöchsten Zählstand eingestellt wird.An erase pulse generated by the first responding output channel V ₁ or by its amplitude shaper and applied to the reset input of the age counter AZ ₁ ensures that the count of the age counter with the highest count is deleted. The "1" at the output of the associated comparator K thus disappears

etc., so that the reference counter RZ to the count of the next highest counting age counter, z. B. the age counter AZ _{2 is} reset. Then he speaks this age counter, e.g. B. the age counter AZ ₂ associated comparator, that is, the comparator K ₂ , with a "1" at its output, so that the countdown of the reference counter RZ is ended abruptly. The following counts are then in a positive sense both on the age counter which now has the highest count, e.g. B. AZ ₂ , and the reference counter RZ, until AZ ₂ is reset to the count "O" by a delete signal L ₂ supplied by the associated channel V ₂ or the amplitude shaper AF ₂ . If, for example, the age counter AZ _{5 is} the age counter with the next highest count, the process described is repeated with this, by resetting the reference counter to the count of this age counter AZ ₅ , then by positive action with the common counting cycles synchronously with the new age counter AZ ₅ as long is counted up by a ₅ derived from the amplitude former AF clear signal L ₅ also clears the count of this counter and the reference counter RZ to a new count, namely, the next highest count is set.

bis A

inkraft,Since the deletion of the age counter synchronized with the deletion of the in the memory parts S and S of the assigned output channel V ₁ , V _p is the stored sound address, the channel that has become free can be re-acted on, as has already been described above. If this tone address has been deleted due to the age-related decay of the played tone without a newly played button and a "takeover" signal being the moment triggering the delete signal, this means that NO (FIG. 3 ) no "1" is pending and therefore the newly assigned output channel can be reassigned in the manner already described with the intermediary of the respectively assigned AND gate from the series of AND gates UG ₁ to UG _p . If, on the other hand, all channels V ₁ to Vp are occupied and at least one game button has already been released, the AND gates A ₁ to A _p or the OR gates OD ₁ to OD _p assigned to them are controlled by the AND gates A.

to A

in force,

bzw. K₂ usw. hat eine "1" an seinem Ausgang, während alle übrigen dieser Komparatoren am Ausgang eine "0" haben. Wenn man nun die in Fig. 3 mit zwei Eingängen versehenen UND-Gatter A

bis A

jeweils mit einem dritten Eingang versieht, diesen dritten Eingang durch ein gemeinsames Überschreibungssignal ÜS steuert und das am Ausgang des einzelnen UND-Gatters A

bis A

gelieferte Signal nicht nur zur Steuerung des zugehörigen ODER-Gatters aus der Reihe der ODER-Gatter OD₁ bis ODp verwendet, sondern-dieses Signal zugleich als zweites Löschsignal für den Inhalt . der Speicherteile S und S des jeweils zugehörigen Ausgangskanals verwendet. Hierdurch ist automatisch erreicht, daß bei Anlegen eines Überschreibungssignals ÜS an die Gesamtheit der UND-Gatter A

bis A

bei vollbesetzten Ausgangskanälen V₁ bis V_p der Kanal mit dem am weitesten abgeklungenen Tonsignal in dem zugeordneten Amplitudenformer sofort freigemacht und durch das neu angespielte Tonsignal besetzt wird.The age counter controlled comparator K which has the highest count

or K ₂ etc. has a "1" at its output, while all other of these comparators have a "0" at the output. If you now look at the AND gates A

to A

each provides a third input, controls this third input by a common overwrite signal US and that at the output of the individual AND gate A

to A

supplied signal not only used to control the associated OR gate from the series of OR gates OD ₁ to ODp, but also this signal as a second delete signal for the content. the memory parts S and S of the respective output channel used. This automatically ensures that when an overwrite signal ÜS is applied to the entirety of the AND gates A

to A

at fully occupied output channels V ₁ to V _p the channel with the most decayed audio signal is immediately cleared in the assigned amplitude shaper and is occupied by the newly played audio signal.

A circuit for generating the TLO signal is shown in FIG. 9. Here, the data input DE of the channel selector KW and the comparator K _{1 are} each connected to one input of an AND gate 1 and one input of a NOR gate 2. The output of the AND gate 1 controls the reset input R of an RS flip-flop 3, the output of the NOR gate controls the set input S of this flip-flop 3. The Q -Output is at an input of a further AND gate TLO ₁ , the output of which supplies the signal TLO. The second input of the AND gate TL0 ₁ is controlled via an inverter by the input P / S.

Since there is exactly one coincidence of a "1" at the output of the comparator K _{1 in question} and a "1" at the data input DE during each counting period of the sound address counter TAZ, provided that the game key acting on channel V _{1 is} still pressed, the output is Q of the RS flip-flop 3 is given a permanent "1" only when the "1" at the data input DE no longer appears at the time when the comparator K ₁ etc. responds, that is, in other words, the game button in question is released.

10 shows a possibility for supplying the individual output channel (V ₁ ,... V _p ) with the sound address stored in the age-related deletion in the respective output channel on the basis of an amplitude modifier (AF ₁ ,... AF _p ) Deletion pulse delivered or a deletion pulse to be supplied when the stored information is prematurely replaced by new information.

liegt mit seinem Ausgang an dem einen Eingang eines weiteren UND-Gatters u

, dessen anderer Eingang gemeinsam mit dem für die Dauer des Betriebszustandes der Rückwärtszählung durch das Flip-Flop AFF (Fig. 6) gesteuerten Steuereingang.des Vorwärts-Rückwärtszählers Z beaufschlagt ist. Demzufolge spricht das UND-Gatter u

nur dann an, wenn bei Rückwärtszählung der Zählstand "0" in dem Zähler Z erreicht wird.The AND-gates assigned to the up-down counter (Z) in the individual amplitude shaper (AF ₁ , .... AF _p ) and each responding at the count "0 _"

lies with its output at one input of a further AND gate u

whose other input is acted upon together with the control input of the up-down counter Z controlled by the flip-flop AFF (FIG. 6) for the duration of the operating state of the down-count. As a result, the AND gate speaks u

only on when the count "0" in counter Z is reached during countdown.

entstehende "1" kann z. B. über ein ODER-Gatter OT an den gemeinsamen Rücksetzeingang der beiden Speicherteile S und S (z. B. an das Gate der Transfertransistoren t₄ bei einer Ausgestaltung gemäß Fig. 5) gelegt werden. Andererseits ist das ODER-Gatter OT auch von dem Ausgang des dem betreffenden Ausgangskanal (V₁.....V_p) jeweils zugeordneten und von dem zugeordneten Alterszähler (AZ₁,....AZ_p) bzw. von dem diesem zugeordneten Kompa- rator (K

,....K

) hergesteuerten UND-Gatters A

,....A

her beaufschlagt, welches, wie bereits dargelegt, bei vollbelegten Ausgangskanälen V₁,....V_p und aufgrund eines Überschreibungssignals ÜS anspricht.The u at the output of the AND gate

resulting "1" can z. B. via an OR gate OT to the common reset input of the two memory parts S and S (z. B. to the gate of the transfer transistors t ₄ in an embodiment according to FIG. 5). On the other hand, the OR gate OT is also from the output of the respectively assigned output channel (V ₁ ..... V _p ) and from the assigned age counter (AZ ₁ , .... AZ _p ) or from the one assigned to it Comparator (K

, .... K

) controlled AND gate A

, .... A

forth, which, as already explained, responds to fully occupied output channels V ₁ ,... V _p and due to an overwrite signal ÜS.

It should also be noted that even in the case of the present digital circuit, a system designed in a known manner for generating a general reset pulse can be provided. It is also still related 10 that the delete signal L output at the output of the OR gate OT in any case - for. B. by tilting the flip-flop AFF in the other operating state and by resetting the RS flip-flops n ₁ - n ₆ in the initial state (the signal L then represents the reset signal Re indicated in FIG. 6) - is used for this purpose that the amplitude shaper F ₁ , .... AF _p assigned to the respective output channel V ₁ , .... V _p is spontaneously reset to the initial state.

It will be understood that modifications of the described embodiment of a digital semiconductor circuit according to the invention are now possible for the person skilled in the art reading the above information.

Claims (42)

1.Digital semiconductor circuit for an electronic organ with a number of control inputs applied via the manual corresponding to the number of play buttons in the manual of the organ and with a number of sound signal inputs applied by an oscillator system with periodic electrical oscillations, in which one control input each has a play button of the Manuals and one audio signal input each is permanently assigned to an audio frequency, in which an audio signal output is also provided for the application of an electro-acoustic transducer and in which the control signals serving for the control inputs correspond to the logical levels, characterized in that the individual control inputs (E _i ) are assigned to each cell of a clock-controlled shift register (PSW) operated as a parallel series converter, that the signal output (D) of the shift register (PSW) and the clock pulses provided for its operation are also used for control purposes serve a switching system (VM), which on the other hand is provided with the entirety of the intended sound signal inputs (TSE), that the number (p) of the sound signal outputs (AU ₁ .... AUp) lower than the number (n) of the control inputs (E.) and each of the sound signal outputs (AU ₁ , .... AU _p ) is assigned an amplitude former (AF ₁ , .... AF _p ) and that the outputs (AG ₁ , .... AG _p ) the amplitude formers are connected to an electroacoustic transducer (L). 2. Digital semiconductor circuit according to claim 1, characterized in that the Signal output (D) of the shift register (PSW) is connected to the data input (DE) of a channel selector (KW) and the channel selector (KW) with one of its outputs (UE ₁ or UE ₂ , .... or UE) for control One output part each (V ₁ , V ₂ , .... V _p ) of the switching system (VM) serves as a further information input of the switching system (VM) in addition to the channel selector (KW) through the shift clocks for the shift register ( PSW) is provided as a counting clock controlled tone address counter (TAZ), which is provided on the p output. parts (V ₁ to V) of the switching system (VM) acts in the same way. 3. Digital semiconductor circuit according to claim 2, characterized in that each of the same output parts (= output channels) (V ₁ to V _p ) with each of the oscillator (TOS) acted upon sound signal inputs (TSE ₁ ..... TSE ₁₂ ) is connected in the same way. 4. Digital semiconductor circuit according to claim 2 or 3, characterized in that the oscillator (TOS) is designed such that it the tone frequencies assigned to the tones of the highest octave in the form of square waves with the levels logic "1" and "0" each an audio signal input (TSE ₁ .... TSE ₁₂ ) of the switching system (VM) and that each of these twelve audio signal inputs is connected to each of the p provided output parts (V ₁ to V _p ) of the switching system (VM). 5. Digital semiconductor circuit according to claims 2 to 4, characterized in that each of the output parts (V ₁ , .... V _p ) of the mediator tion system (VM) is provided with a feedback control output (B ₁ , .... B), by means of which a reaction of the relevant output part (V ₁ , ... V _p ) of the switching system (VM) on the channel selector (KW) and possibly an additional control effect on the amplitude former (AF ₁ , .... AF _p ) assigned to the relevant output part is possible. 6. Digital semiconductor circuit according to claims 2 to 5, characterized in that the sound address counter (TAZ) acted upon by the shift clocks (TM) of the input shift register (PSW) consists of two parts, that each of the provided p output parts (V ₁ , .. ..V _p ) the switching system (VM) as an information input part contains a read / write memory controlled both by the channel selector (KW) and by the sound address counter (TAZ), that this read / write memory consists of two parts (S, S), that also the first Part (S) of all of these memories is loaded by the first part of the sound address counter (TAZ) and the second part (S) by the second part (S) of the sound address counter (TAZ) and that finally the first part of the sound address counter and the memory (S , S) for controlling the switching system (VM) on the basis of the sound name and the second part for controlling the switching system (VM) on the basis of the octave containing the respectively played sound of the manual (M) are provided. 7. Digital semiconductor circuit according to claim 6, characterized in that the first part of the sound address counter consists of four series-connected counter stages and the second part of the sound address counter (TAZ) consists of at least three series-connected counter stages, that it the counting input of the first counter stage of the first part of the sound address counter (TAZ) is acted upon by the shift clocks intended for the operation of the input shift register (PSW) in the same way as the clock input of the shift register (PSW), so that the counting input of the second part of the sound address counter (TAZ ) is applied to the outputs of the counter stages of this sound address counter part, which outputs the count of the first part of the sound address counter, in such a way that the second part of the sound address counter (TAZ) receives a counting pulse only when the count of the first counter part which is initially at "0" has increased by the amount "12". 8. Digital semiconductor circuit according to claim 7, characterized in that the first part (S) in the individual output parts (V ₁ , .... V _p ) of the switching system (VM) provided read-write memory z. B. from four memory cells and the second part (S) z. B. consists of three memory cells that the information input of the memory cells of the first memory part (S) for receiving the count of the first part and the information input of the memory cell of the second memory part (S) is provided for receiving the count of the second part of the sound address counter (TAZ) that the content of the first memory part (S) for controlling the recording of the information present at the audio signal inputs (TSE ₁ , .... TSE ₁₂ ) of the switching system (VM) through the individual output channel (V ₁ , .... V _p ) the switching system (VM) and the content of the second memory part (S) for controlling the transfer of this information to the audio signal output (AU ₁ , .... AU _p ) of the relevant output channel (V ₁ , .... V _p ) of the switching system (VM) is provided. 9. Digital semiconductor circuit according to claim 8, characterized in that a by the memory cells of the first memory part (S) controlled first decoder (D) and a by the memory cells of the second memory part (S) controlled second decoder (D) in each output part (V ₁ , .... V _p ) of the switching system (VM), it is provided that each of the outputs of the first decoder (D) is provided with one input each of an AND gate (U1, U ₂ , .... U ₁₂ ) is whose second input is controlled by one of the sound signal inputs (TSE) of the switching system (VM) acted upon by the oscillator (TOS) and the output of which is connected to one of the inputs of a first OR gate (Q), further that each of the Outputs of the second decoder (D) to one input each of an AND gate (U

, U

, .... U

.. specified) whose second input is through the intermediary of the output of the first OR gate (0) is controlled in a different manner and its signal output to a respective one of the inputs of a second, the tone signal output of the respective circuit portion and one of the p _{sound interruptions} g _än g _{e (AU1} , _AU2 , _.. .. _AU p) of the switching system (VM) forming second OR gate (0 ^* ) is placed. 10. Digital semiconductor circuit according to claim 9, characterized in that the signal output of the first OR gate (0) of each output part (V ₁ , .... V _p ) of the switching system (VM) on the one hand to one input of one of the second Decoder (D *) controlled AND gate (U

), on the other hand to the signal input of a frequency divider (TT), that the number of divider stages of the frequency divider (TT) is at least equal to the number of signal outputs of the second one reduced Is decoder and that the signal outputs of at least the first divider stages each to a further one of the AND gates controlled by the second decoder (D) (U

, .... U

....) is laid. 11. Digital semiconductor circuit according to claims 8 to 10, characterized in that the two memory parts (S, S *) in each of the output channels (V ₁ .... V _p ) of the switching system (VM) through the channel selector (KW) one control input assigned to the respective output channel (UE ₁ , UE ₂ , .... UEp) is controlled. 12. Digital semiconductor circuit according to claims 8 to 11, characterized in that each of the memory cells of the two memory parts (S, S) in the individual output channels (V ₁ , .... V _p ) with respect to the signal input from the sound address counter (TAZ) and with regard to the information output to the decoder (D, D) is monitored by means of a comparator (K ₁ , .... K _p ) assigned to the respective output channel (V ₁ .... V _p ) and that the individual comparators (K ₁ , K ₂ , .... K _p ) are such that - if the count on the sound address counter (TAZ) matches that in the two memory parts (S, S) of the respective output channel (V ₁ , V ₂ , .. ..Vp) each stored and the sound address of the game key acting on the relevant output channel outputting the signal "1", while in the other case a "0" is pending at the output of these comparators. 13. Digital semiconductor circuit according to claims 8 to 12, characterized in that the two memory parts (S, S *) in the output channels (V ₁ , .... V _p ) consist of memory cells (S ₁ , S ₂ , ....) which are not connected to one another, the data input of each of which is connected to an output of the sound address counter (TAZ) which conveys the count and the data output of which is on an input of the decoder (D or D) to be loaded by the relevant memory cell. 14. Digital semiconductor circuit according to claim 13, characterized in that the individual memory cells (S ₁ , S ₂ , ....) of the two memory parts (S, S) of the individual output channels (V ₁ , .... V _p ) clock-controlled quasi-static shift register cells exist (Fig. 7). 15. Digital semiconductor circuit according to claim 4 and 9, characterized in that the outputs of the first decoder (D) each with a tone assigned to the highest octave and from which the corresponding square wave tone generator (TOS) acted on tone signal input (TSE ₁ ,. ... TSE ₁₂ ) is combined by an AND gate (U ₁ , .... U ₁₂ ) with two inputs each, so that the outputs of these AND gates (U ₁ , .... U ₁₂ ) are also connected One input each of an OR gate (0) and its input is connected to the clock input of a frequency divider (TT) with a number of divider stages appropriate to the number of the intended octaves and that the output of the OR gate (0) is direct as well as via the Divider stages of the frequency divider (TT) delivered tone-frequency vibrations to one input of an OR gate (0) forming the output (AU ₁ , .... AU _p ) of the relevant output channel (V ₁ , .... V _p ) in one controlled by the second decoder (D) are switched on. 16. Digital semiconductor circuit according to claim 15, characterized in that the output of the by the first decoder (D) controlled OR gate (0) and the signal output of each divider stage of the frequency divider (TT) via an AND gate (U

, .... U

) each with an output of the second decoder (D) and the output of these AND gates (U

, .... U

) are each connected to an output of the OR gate (0 *) forming the audio signal output (AD ₁ , ... AU _p ) of the relevant output channel (V ₁ , .... V _p ). 17. Digital semiconductor circuit according to claims 1 to 16, characterized in that in the individual audio signal outputs (AU ₁ , ... AU) of the switching system (VM) assigned to amplitude formers one acted upon by the audio signal output concerned and each by an up-down counter ( Z) controlled shaper circuit (FS) is provided and its output is connected to a common (mixing stage) with the individual sound signal outputs with subsequent electro-acoustic transducer (L). 18. Digital semiconductor circuit according to claim 17, characterized in that for the generation of the up-down counter (Z) required for the application of the shaping circuit (FS) in the individual amplitude formers (AF ₁ , .... AF _p ) controlling up-down counter for all amplitude formers of the common oscillator circuit (OS ₁ or OS ₂ ) it is provided that the oscillator is controlled by a logic circuit individually controlled in the individual amplitude orients (AF ₁ , .... AF _p ) and at least one frequency divider (TL ₁ or TL ₂ ) provides the counting cycles required for the relevant up / down counter (Z). 19. Digital semiconductor circuit according to claim 18, characterized in that by the count outputs of the up-down counter (Z) in the individual amplitude formers z. B. three RS flip-flops (n ₁ , ⁿ ₂ ; ⁿ ₃ , ⁿ ₄ ; n ₅ , n ₆ ) are controlled, each of which responds at a certain count and with one output the permeability of one AND gate (a ₁ .... a ₆ ) for each of a sequence of counting pulses delivered by the oscillator (OZ ₁ or OZ ₂ ) via the divider stages of at least one frequency divider (TL ₁ or TL ₂ ) to one input of the other input by a is controlled via various signals (St, P / S, u ₁ , u2) which are used to operate the overall circuit, logic circuit (Lo). 20. Digital semiconductor circuit according to claim 19, characterized in that with reaching the highest count in the up-down counters (Z) of the individual amplitude formers (AF ₁ to AFp) via the RS flip-flops (n ₁ , ... .n ₆ ) controlled further flip-flop (AFF) switched from its previous operating state and the up-counting direction of the up-down counter (Z) to the other operating state assigned to the down-counting direction of this counter (Z) and this due to this switchover its output signal is used to switch the counter in the countdown direction. 21. Digital semiconductor circuit according to claims 18 to 20, characterized in that upon reaching the count "0" in the process of counting down by the up-down Counter (Z) in the individual amplitude shapers the output of an output channel (V ₁ , .... V _p ) of the switching system (VM) assigned to the respective amplitude shaper (AF ₁ , .... AF _p ) in the initial state displacing erase pulse (L ₁ , .... L _p ) is connected. 22. Digital semiconductor circuit according to claim 21, characterized in that the outputs indicating the inverted count ( Q ) of the up / down counter (Z) in the individual amplitude formers (AF ₁ , .... AF _p ) at the count "0" and only at this responsive AND gate (u ₂ ) act on that the output of this AND Gate ( _U2 ) for controlling the one input of a second AND gate (u ₃ ) is provided, the other input of which together with the control input controlling the down counting direction, in particular by the RS flip-flops (Z) controlled by the counter (Z). n ₁ , .... n ₆ ) controlled flip-flop (AFF) controlled and its output provided for the delivery of an erase signal (L) for the sound address stored in the respectively assigned output channel (V ₁ , .... V _p ) is (Fig. 10). 23. Digital semiconductor circuit according to claims 5 to 22, characterized in that to form a channel selector (KW) from the signal output (DA) of the input shift register (PSW) acted upon data input (DE) to one of the number (p) of the output channels ( V ₁ , .... V _p ) corresponding number of AND gates (A ₁ , .... A _p ), each with two inputs, the second input of which is connected by an when the output channel (V ₁ , .... V _p ) the signal "0" unoccupied output channel, the signal "1" carrying the feedback control output (B ₁ , .... B _p ) of the assigned output channel (V ₁ , .... V _p ) is controlled and the output of which is the transfer of one of the sound addresses to the next "1" . at the data input (DE) of the channel selector (KW) causing game button corresponding count from the sound address counter (TAZ) into the memory (S, S *) of the relevant output channel (V ₁ , .... V _p ). 24. Digital semiconductor circuit according to claim 23, characterized in that in the memory parts (S, S *) of the individual output channel (V ₁ , .... V _p ) the outputs of the two memory parts indicating the respectively stored information content to a common NOR Gates (NR) are placed, the output of which forms the feedback control output (B ₁ , .... Bp) of the relevant output channel (V ₁ , ... V _p ). 25. Digital semiconductor circuit according to claims 23 and 24, characterized in that the second input of the information transfer from the sound address counter (TAZ) not connected to the data input (DE) into the respectively assigned output channel (V ₁ , .... V _p ) inducing AND gates (a _1, a ..... _p), each by one another the output channel in question (V ₁ .... _Vp) is also associated AND gate (UG _1, .... UG _p) It is controlled that each of these further AND gates (UG ₁ , .... UG _p ) has a first signal input controlled by the feedback control output (B ₁ , .... B _p ) of the respectively assigned output channel and a second one by the total of provided output channels (V ₁ , .... V _p ) via a common AND gate (N0, IV) controlled signal input and that with the exception of the first output channel (V ₁ ) arranged AND gates (UG ₁ ) the remaining of these AND gates (UG ₂ , .... UGp) also have a third input, via which a logic (L ₁₂ , ... L _(p-1) , p is an order in which the individual output channels (V ₁ , .... V _p ) are controlled. 26. Digital semiconductor circuit according to claim 23, characterized in that the feedback control output (B ₁ ) of the first output channel (V ₁ ) via an inverter (L ₁₂ ) with the third (free) input of the assigned to the second output channel and through the feedback control output (B ₂ ) of the second output channel (V ₂ ) directly applied AND gate (UG ₂ ) is placed that further between the respectively adjacent through the feedback input (B ₂ , .... B _p ) of the respectively assigned output channel (V ₂ , .... V _p ) controlled AND gate (UG ₂ , .... UGp) via their free third input at the input of an inverter (L _23a , .... L _(p-1) , pa, that in addition the output of this inverter and the feedback control output (B ₂ , .... B _p ) of the AND gate (UG ₂ , .... directly acted upon by the relevant feedback control output (R ₂ , .... R _p ) UG _p ) an - j _e an input of a NOR gate (L _23b , ... L _(p-1) pb), the output of which is connected to the free third input of the next channel (V _3, .... V _p) respectively associated and from that directly acted upon by its back control output (B _3, .... Bp) AND gate (UG _3, .... UG _p ) is connected. 27. Digital semiconductor circuit according to claims 23 and 26, characterized in that between the loading of the respectively assigned output channel (V ₁ , .... V _p ) by the common sound address counter TAZ and the AND gate (A _1, .... A _p) and the same channel (V ₁ .... _Vp) assigned to the second AND gate (UG _1, .... UG _p) in each case an OR gate (OD ₁ , ... OD _p ) is provided, the output of which is at the input which is not acted upon by the data input (DE) and which initiates the information input into the respectively assigned output channel (V ₁ , .... V _p ) and at the same time by emitting a start signal ( St) to the respectively assigned amplitude shaper (AF ₁ , .... AF _p ) whose AND gate (A ₁ , .... A _p ) is brought into operation and whose one input is through the output of the control output (B ₁ , .... B _p ) of the assigned output channel (V ₁ , .... V) controlled AND gate (UG ₁ , .... UG _p ) is applied. 28. Digital semiconductor circuit according to claims 23 to 27, characterized in that the outputs of the output channels (V ₁ , .... V _p ) assigned comparators (K ₁ , .... K _p ) either to control a common OR -Gatters (OD *) or a common AND gate are provided. 29. Digital semiconductor circuit according to claims 23 to 28, characterized in that each of the intended output channels (V ₁ , .... V _p ) is assigned an age counter (AZ ₁ , .... AZ _p ), that also a with regard to the number of counting levels with the age counters (AZ ₁ , .... AZ _p ) matching, common and designed as a forward-backward counter reference counter (RZ) is provided that between each of the age counters (AZ ₁ , .... AZ _p ) and the common reference counter (RZ) each have an effect on the equality of the counter readings in the reference counter (RZ) with the respectively assigned one Age counter (AZ) responsive comparator (K *, .... K

) is provided, via the output of which a triggering of the assigned output channel (V ₁ , .... V _p ), which can be triggered by a signal (ÜS), via the one between the two assigned to the relevant output channel (V ₁ , .... V _p ) AND gates (A ₁ , U _G1 ; A ₂ UG ₂ ; .... Ap, UG _p ) provided OR gates (OD ₁ , OD ₂ , ... OD _p ) is possible. 30. Digital semiconductor circuit according to claim 29, characterized in that the output of the individual age counters (AZ ₁ , .... AZ _p ) assigned comparators (K

, .... K

) with the mediation of an AND gate (A *, .... A

) to a second input of the OR gate (OD ₁ ,...) which controls the AND gate (A ₁ , ..... A _p ) which effects the information input into the respectively assigned output channel (V ₁ , .... V _p ). ... OD _p ) is placed. 31. Digital semiconductor circuit according to claim 30, characterized in that the individual comparator (K

, .... K

) each downstream AND gate (A

, .... A

) with a second input through the feedback control inputs (B ₁ , .... B _p ) of the entirety of the output channels (V ₁ .... V _p ) is also controlled via a common NOR gate (NO). 32. Digital semiconductor circuit according to claims 30 and 31, characterized in that the individual comparator (K

, .... K

) Respectively downstream and the connection at which the stress of a respectively associated output channel (V ₁ .... _Vp) causing AND gate (A _1, .... A _p) bilden- de AND gate (A

, .... A

) together with the other of these AND gates (A

, .... A

) at a third input by means of an overwrite signal (ÜS) is controlled and that this is then at the output of this AND gate (A

, .... A

) appearing signal is used to delete the TON address stored in the respective assigned output channel. 33. Digital semiconductor circuit according to claim 32, characterized in that the output of the individual age counters (AZ1 .... AZp) respectively assigned comparator (K

, .... K

) downstream AND gate (A

, .... A

) is connected via an OR gate (OT) to the erase input of the memory parts (S, S) provided in the associated output channel (V ₁ , .... V _p ) and that another input of said OR gate (OT) is acted upon by the cancellation signal (L) delivered from the respective amplitude channel (V ₁ , .... V _p ) assigned to the respective amplitude shaper (AF ₁ , .... AF _p ). 34. Digital semiconductor circuit according to claims 29 to 31, characterized in that the sound address used for deleting the sound address stored in one of the output channels (V ₁ , .... V _p ) and by the associated amplitude shaper (AF ₁ , ... .AF _p ) delivered delete signal (L) or a delete signal generated due to an overwrite signal (ÜS) is used simultaneously to delete a possibly existing count in the associated age counter (AZ ₁ , .... AZ _p ). 35. Digital semiconductor circuit according to claims 29 to 33, characterized in that the count input of each age counter (AZ ₁ , .... AZ _p ) via the output of one AND gate (UL ₁ , .... UL _p ) with Counting clocks is supplied that the counting input of the reference counter (RZ) is supplied with counting clocks via the output of an OR gate (oe), The fact that the output of the individual age counters (AZ ₁ .... AZ _p) associated AND gate (UL _1, UL .... _p) to a respective input of the reference counter (RZ) with counting clock pulses supplied OR gate (oe) is connected to the fact that the AND gates (UL ₁ , .... UL _p ) each supplying the counting cycles for the individual age counters (AZ ₁ , .... AZ _p ) and thus for the reference counter (RZ) have three inputs, one of which is controlled by an OR gate (OD) (or one) which is controlled jointly by the feedback control outputs (B ₁ , .... B _p ) of the intended output channels (V ₁ , .... V _p ) accordingly switched AND gate) is acted upon, the second by clock pulses appearing synchronously in all these AND gates (UL ₁ , .... UL _p ) and the last by one each for the relevant age counter (AZ ₁ , .... AZ _p ) in the manual (M) which responds to the game button assigned to the output channel assigned to the age counter concerned (V ₁ , .... V _p ) ends circuit part (TLO ₁ , ..... TLO _p ) is applied. 36. Digital semiconductor circuit according to claims 29 to 35, characterized in that the comparators assigned to the individual age counters (AZ ₁ , .... AZ _p ) (K

, .... K

) are provided in each case for generating an erase signal for the counter reading of the age counter when the "1" disappears at its output and a further one for resetting the counter reading of the reference counter RZ to the counter reading of the signal with the next higher counter reading. 37. Digital semiconductor circuit according to claim 36, characterized in that the output of the individual comparators (K

, .... K

) is connected via an inverter (IR ₁ , .... IRp) and a differentiation stage (ds ₁ , .... ds _p ) to the delete input of the assigned age counter (AZ ₁ , .... AZ _p ), that in addition the output of these inverters (IR ₁ , .... IR _p ) is in each case connected to an input of an AND gate (at ₁ ) with p inputs and that finally the output of this AND gate (at ₁ ) for switching over the Counting direction in the reference counter (RZ) from the upward counting direction in the opposite counting direction for the duration of a "1" pending at the output of the AND gate (at ₁ ) and for controlling countdown pulses supplied to the counting input of the reference counter (RZ) during the countdown phase is provided. 38. Digital semiconductor circuit according to claims 35 and 36, characterized in that the individual age counter (AZ ₁ , .... AZ _p ) or its supply with counting clocks respectively assigned circuit part (TLO ₁ , .... TLO _p ) An AND gate with two inputs contains that one of these inputs through the comparator (K ₁ , .... Kp) in the respective output channel (V ₁ ,... _p ) assigned to the relevant age counter (AZ ₁ ,... _p ). ... V _p ) and the other is acted upon by the data input (DE) of the channel selector (KW). 39. Digital semiconductor circuit according to claim 35, characterized in that when releasing the assigned output channel (V ₁ , .... V _p ) with assigned age counter game key temporarily assigned in the manual (M) responsive circuit part (TLO ₁ , ... .TLO _p ) an AND gate (1) and a NOR gate (2) - each with two inputs - contains that one input of each of these two gates (1, 2) through the data input (DE) of the channel selector (KW ) and the other is controlled by the output of the respective assigned output channel (V ₁ , .... V _p ) and by it and by the sound address counter (TAZ) comparator (K ₁ , .... Kp) that the outputs of the two gates (1, 2) are each connected to an input of an RS flip-flop and that, finally, at the output having the state "1" when a "0" is present at the output of the AND gate (1) Q ) of the RS flip-flop (3), a signal (TLO) which also controls the counting pulses for the associated age counter and AND gate (UL ₁ , .... UL) can be removed. 40. Digital semiconductor circuit according to claim 5, characterized in that the play key in the manual (in the manual (when releasing the assigned output channel (V ₁ , .... V _p ) with assigned age counter (AZ ₁ , .... AZ _p )) M) responsive circuit part (TLO ₁ , ..... TLO _p ) an AND gate (4) with an input through the data input (DE) of the channel selector (KW) and one through the comparator (K ₁ , ... .K _p ) in the associated output channel (V ₁ , .... V _p ) controlled input and a monostable multivibrator (5) connected downstream of this AND gate (4), the relaxation time of which is somewhat longer than the duration of a full counting period of the sound address counter ( TAZ) and that at the output in the idle state of the monostable multivibrator (5) having the state "1", the AND gate (UL ₁ ,...) Which conveys the counting cycles for the associated age counter (AZ ₁ , .... AZp). ... UL _p ) co-controlling signal (TLO) is removable. 41. Digital semiconductor circuit according to claims 39 or 40, characterized in that the pressed when releasing the Game button-delivering output of the RS flip-flop (3) or the monostable multivibrator (5) the control signal (TLO) delivering output of the circuit parts mentioned is connected to the input of a further two-input AND gate (TLO) while the second input of this AND gate is controlled by a signal (P / S) via an inverter (7). 42. Digital semiconductor circuit according to claim 35, characterized in that the counting clocks used for loading the reference counter (RZ) and all age counters (AZ ₁ , .... AZ _p ) are used synchronously by a common clock generator, e.g. B. from the clock generator (TG) for the input shift register (PSW).

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