EP0092211A1 - Electronic time-programme commutating device - Google Patents

Abstract

PCT No. PCT/EP83/00107 Sec. 371 Date Dec. 20, 1983 Sec. 102(e) Date Dec. 20, 1983 PCT Filed Apr. 18, 1983 PCT Pub. No. WO83/03688 PCT Pub. Date Oct. 27, 1983.A time-programming apparatus comprises a central processor which includes at least one recording/readout working memory having addressable registers, computing means with at least one logic circuit connected to the working memory for processing output signals therefrom, and at least one program memory with associated program counter connected to the logic circuit for the generation and distribution of function signals for the central processor. The apparatus further comprises a luminous digital display connected to the processor and divided into subregions with respective display fields for alphanumeric display, input means including manually actuatable keys and switches assigned to the display fields, and output means for selective actuation of a load to be operated, the input and output means being connected to the central processor and all including the luminous display, with a wall provided therefor, being contained in a common housing. Power means in the housing supplies electric power to the central processor, the input means being so connected to the processor as to define hierarchical functioning and including first and second function-selection means and a further selection means.

Description

The present invention relates to an electronic time or time program switching device, comprising an electronic clock with a clock generator and several divider stages, a central unit with read / write work memories and / or read-only memories, computer, ie. arithmetic-logic unit for the processing of data, as well as program memory with associated program counter and decoding devices, and a luminous digit on direction, an input unit with controls, such as buttons and switches, an output unit for the excitation or de-excitation of switch devices for consumer circuits, and finally control and power supply modules, as well as a housing in the front wall of control and setting fields and at least one luminous digit device is arranged, with further special features according to the preamble of claim 1.

The requirements for a time or time program switching device, previously mainly time switches with electromechanical drive and mechanical switching devices, such as radially displaceable switching segments, plug-in switching fingers, or the like, have recently become increasingly high. So now and in the future it will probably be required even more that at least several time switch programs, ie. with differences in different days of the week and also for several switching channels with partially different time switching programs should be as easy and error-free to set.

Electronic time switches with more complicated and multi-time and channel programs have recently come onto the market; in these it has been shown that incorrect entries are possible in several ways and then problems in correcting them occur, for example because. Entire sections of the switching program must be deleted and the relevant switching data must be re-entered from the beginning. So it is possible with the well-known electronic time switch "GRÄSSLIN digi 127", because a numeric keypad is provided for the input of the switching time data, also impermissible time data, eg. Enter 26.84 with weekday "9"; this error is indicated by flashing, but it requires deleting the entire time entry and re-entering it in fe most prescribed order, ie. starting from the beginning.

In addition, in the known time switch, the switching data record cannot be completely entered, but only a partial section thereof, for example. with a single day of the week, either an ON switching time or an OFF switching time; Combinations e.g. of several days of the week with the same ON and OFF switching times are neither possible in the display nor can they be checked at the same time. A pattern for a programming sheet is therefore included in the operating instructions.

The invention is therefore based on the object of improving a time or time program switching device and its modules according to the preamble of claim 1, ie. the display device for the ON and OFF switching times with any number of days of the week and possibly different switching channels - optionally adjustable in any change of the sections of the complete data set - combined with the operating elements and intermediate memories so that they can be controlled and designed so that the individual switching times and secondary data can be configured can be entered in any order and the entry of inadmissible switching time data is excluded from the outset, incorrect or no longer required input data for switching times in individual sections can be corrected as desired and complete data sets with ON and OFF switching times, weekday (s) and secondary data, e.g. selected switching channels or choice between ON or OFF switching time, can be clearly read and adjusted or corrected during the entire setting process.

This object is achieved according to the invention in a time switch with the features according to the preamble of claim 1 by connection with the sub-features according to the characterizing part of claim 1. This conveys the technical progress that in the entire handling, ie. the creation, supplementation, partial deletion and correction of an ON and OFF switching time pair, the overview of the entire associated data set including the weekdays and switching channels belonging to this pair, a permanent monitoring of all setting measures to a high degree and thus the operation without any special Training and

Requirements on the skill of the operator is possible. The advantages that can be achieved in this way are further promoted by configurations in connection with further special features, since the functional reliability, which is otherwise only achievable to a limited extent, is even better guaranteed with such a highly developed and versatile time switch.

• • Fig.l: a) die Draufsicht auf den Zeitschalter mit geschlossenem Gehäuse,
  • b) einen Teilschnitt in Längsrichtung,
  • c) die Draufsicht auf das nichtbestückte Gehäuse bzw. dessen Oberteil mit beschrifteter Abdeckmaske auf dem Bedienfeld;
• • Fig.2: a) die Draufsicht auf das nichtbestückte Oberteil ohne Abdeckmaske mit Schnitt-Angaben,
  • b) einen abgesetzten Längsschnitt C-D zur Wiedergabe von Einzelheiten der Schalterhalterung bzw. Tastenführung,
  • c) einen Teilschnitt mit Leiterplatte (vgl. Fig. lb),
  • d) einen abgesetzten Teilschnitt A-B vor allem zur Darstellung der Führungsrippen für die Tastenstife,
  • e) die Unteransicht des GehäuseOberteils mit den innen einstückig angeformten Führungsrippen für die Tastenstife;
• Fig.3: einen Längsschnitt des aus Gehäuse-Unterteil und darauf aufgesetztem Oberteil zusammengebauten eigentlichen Gehäuses mit dazwischen eingeklemmter Leiterplatte mit angedeuteter Bestückung derselben und Abdeckung des Gehäuse-Unterteils durch ein topfförmiges Abdeckgehäuse mit ausbrechbaren Wandteilen für die Durchführung von Anschlußleitungen;
• Fig.4: eine Variante der Frontansicht bei anderer Gehäuseform pzw. anderer Taster-/ /Schaller-Bestuckung
  • a) mit übereinander benachbarten und in der Breite aneinander angepaßten Anzeige- und Bedienungsfeldern, sonst jedoch gleicher elektronischer Ausstattung wie im Ausführungsbeispiel der Fig.la (Stunden, Minuten, Sekunden, vier Kanäle)
  • b) mit ähnlicher Frontplatten-Gestaltung wie in Fig.la, jedoch mit dieser gegnüber abgerüsteter elektronischer Ausstattung, dh. für Zeitanzeige von Stunden und Minuten und im zB. Sekundentakt blinkenden Doppelpunkten, sowie für maximal zwei Kanäle; bei einkanaliger Ausführung fehlen die gestrichelt markierten Teile;
• • Fig.5: a) einen Querschnitt G-H (vgl. Fig.2a) durch das Gehäuse-Oberteil,
  • b) einen Querschnitt E-F (vgl. Fig.2c) do., mit aufgesetztem topfförmigem Abdeckgehäuse und angedeuteter Bestückung mit der Leiterplatte,
  • c) einen Querschnitt I-K (vgl. Fig.2e) do;
• • Fig.6: a) die Unteransicht des Gehäuse-Unterteils,
  • b) einen Längsschnitt E-F (vgl. Fig.6c),
  • c) die Draufsicht auf das Gehäuse-Unterteil;
• • Fig.7: a) einen Längsschnitt A-B durch das Gehäuse-Unterteil (vgl.Fig.6c)
  • b) eine Seitenansicht desselben in Pfeilrichtung N,
  • c) einen Querschnitt I-K,
  • d) do. G-H,
  • e) einen Längsschnitt C-D,
  • f) eine Seitenansicht in Pfeilrichtung O;
• • Fig.8: a) einen Querschnitt J-K durch das topfförmige Abdeckgehäuse (vgl. Fig.8d),
  • b) einen Längsschnitt A-H (vgl. Fig.8d),
  • c) einen Querschnitt L-O do.
  • d) eine Draufsicht auf das Innere des Abdeckgehäuses;
• • Fig.9: a) eine Unteransicht des Abdeckgehäuses,
  • b) eine Vorderansicht davon;
• Fig.lo: ein stark vereinfachtes Blockschaltbild mit den wichtigsten elektronischen Baugruppen;
• Fig.11: eine schematische Übersicht über die Aufteilung des Gesamt-Blockschaltbildes mit logischen Parallel-Verknüpfungsstufen und die Zusammengehörigkeit der Teil-Blockschaltbilder a) bis d):
  • a) die Untergruppe mit den Funktionswahl-Tasten,
  • b) die Untergruppe mit den Stelltasten und dem Programmierspeicher,
  • c) die Untergruppe mit der UND-Verknüpfungs-Gruppe für die Ein-und Ausgänge von Eingangsspeicher der Anzeigeeinrichtung und
  • d) die Untergruppe mit elektronischer Uhr und Logischen Einheiten (LE) mit zugehörigen UND-Verknüpfungsgliedern;
• Fig.12: einen Prinzip-Blockschalt Ausschnitt aus einem Beispiel für logische Seriell-Verknüpfungsstufen mit Schiebe- registern bei dem Vergleich von Da-tensatz--Abschnitten;
• Fig.13: einen Prinzip-Blockschaltbild-Ausschnitt aus einem dem Beispiel von Fig.12 entsprechenden Beispiel bei Auswertung der Stelltasten-Codes;
• Fig.14: ein Prinzip-Blockschaltbild für ein Ausführungsbeispiel mit Bedienfeld-Matrix für Funktionswahl-Schalter und -Tasten, sowie Stelltasten und Mikroprozessor mit arithmetisch-logischer Einheit, Pufferspeichern, Eingangs- und Ausgangs-Registern, Arbeits- und Programmspeichern usw.
• Fig.15: auszugsweise ein Flußuragramm des Ausführungsberspiels der Schaltuhr gemäß Fig.4b mit eingefügten Leuchtziffer-Einrichtungs-Display-Anzeigen für einzelne Betriebszustände mit Anzeige der Schaltzeiten für EIN- und AUS-Schaltung und der laufenden Uhrzeit, der gewählten Wochentage und Schaltkanäle, sowie der Symbole "I" und "0" für die EIN- und AUS- Schaltzeiten;
• Fig.16: Beispiele für Anzeige der Wochentage:
  • a) Einstellung von zwei Tagen
  • b) Ergänzung einer bereits vorliegenden Einstellung und Reihenfolge der Betätigung der Taster hierfür
  • c) fehlenden Einstellung der EIN-Schalttage
  • d) do. der EIN- und AUS-Schalttage
  • e) Zahl der eingestellten EIN-Schalttage größer als diejenige der AUS-Schalttage
  • f₁) Positionieren und Quittieren der Schaltkanäle
  • f₂) fehlende Einstellung des zweiten Schaltkanals (nur bei Zeitkanal-Schaltuhr)
• Fig.17: Blockschaltbild für ein Ausführungsbeispiel der Kompatibilitäts- (Plausibilitäts-)Prüfung der eingegebenen Daten eines kompletten SOLL-Schaltzeiten-Datensatzes vor der Übernahme aus dem Programmierspeicher in den Schreib-/Lese-Arbeitsspeicher.

The embodiments of the invention are the subject of the dependent claims. Exemplary embodiments are described below with reference to the drawing; it represents:

• • Fig.l: a) the top view of the timer with the housing closed,
  • b) a partial section in the longitudinal direction,
  • c) the top view of the unequipped housing or its upper part with a labeled mask on the control panel;
• • Fig. 2: a) the top view of the non-equipped upper part without a mask with cut information,
  • b) a stepped longitudinal section CD for reproducing details of the switch holder or button guide,
  • c) a partial section with a printed circuit board (see FIG. 1b),
  • d) a stepped partial section AB, above all to show the guide ribs for the key pins,
  • e) the bottom view of the upper housing part with the integral guide ribs for the key pins;
• 3 shows a longitudinal section of the actual housing assembled from the lower part of the housing and the upper part placed thereon, with a printed circuit board clamped in between with indicated mounting thereof and covering the lower part of the housing by a pot-shaped cover housing with break-out wall parts for the implementation of connecting lines;
• Fig.4: a variant of the front view with a different housing shape pzw. other push buttons / / Schaller equipment
  • a) with display and control fields adjacent to one another and the width of which is matched to one another, but otherwise the same electronic equipment as in the embodiment of Fig.la (hours, minutes, seconds, four channels)
  • b) with a similar front panel design as in Fig.la, but with this compared to disarmed electronic equipment, ie. for time display of hours and minutes and in e.g. Flashing colons every second, and for a maximum of two channels; in the single-channel version, the parts marked with dashed lines are missing;
• • 5: a) a cross section GH (see FIG. 2a) through the upper housing part,
  • b) a cross section EF (see FIG. 2c) do., with a pot-shaped cover housing and indicated mounting of the printed circuit board,
  • c) a cross section IK (see FIG. 2e) do;
• • 6: a) the bottom view of the lower housing part,
  • b) a longitudinal section EF (see FIG. 6c),
  • c) the top view of the lower housing part;
• • Fig. 7: a) a longitudinal section AB through the lower housing part (see Fig. 6c)
  • b) a side view of the same in the direction of arrow N,
  • c) a cross section IK,
  • d) do. GH,
  • e) a longitudinal section CD,
  • f) a side view in the direction of arrow O;
• • 8: a) a cross section JK through the cup-shaped cover housing (see FIG. 8d),
  • b) a longitudinal section AH (see FIG. 8d),
  • c) a cross section LO do.
  • d) a top view of the interior of the cover housing;
• • Fig. 9: a) a bottom view of the cover housing,
  • b) a front view thereof;
• Fig.lo: a very simplified block diagram with the most important electronic components;
• Fig. 11: a schematic overview of the division of the overall block diagram with logical parallel logic levels and the belonging together of the partial block diagrams a) to d):
  • a) the subgroup with the function selection buttons,
  • b) the sub-group with the setting buttons and the programming memory,
  • c) the subgroup with the AND logic group for the inputs and outputs of the input memory of the display device and
  • d) the subgroup with electronic clock and logic units (LE) with associated AND logic elements;
• Fig. 12: a basic block circuit section from an example of logical serial logic stages with shift registers when comparing data record sections;
• Fig. 13: a basic block diagram section from an example corresponding to the example in Fig. 12 when evaluating the setting key codes;
• Fig. 14: a basic block diagram for an exemplary embodiment with a control panel matrix for function selection switches and keys, as well as setting keys and microprocessor with arithmetic-logic unit, buffer memories, input and output registers, working and program memories etc.
• Fig. 15: Excerpt of a flow chart of the execution example of the time switch according to Fig. 4b with inserted luminous digit device display displays for individual operating states with display of the switching times for ON and OFF switching and the current time, the selected days of the week and switching channels, and the symbols "I" and "0" for the ON and OFF switching times;
• Fig. 16: Examples of weekdays:
  • a) Setting two days
  • b) Supplementing an existing setting and sequence of pressing the buttons for this
  • c) Missing setting of the ON switching days
  • d) do. the ON and OFF switching days
  • e) Number of ON switching days set greater than that of OFF switching days
  • f ₁ ) Positioning and acknowledging the switching channels
  • f ₂ ) missing setting of the second switching channel (only with time channel timer)
• Fig. 17: Block diagram for an embodiment of the compatibility (plausibility) check of the entered data of a complete SET switching times data record before the transfer from the programming memory into the read / write main memory.

In Fig.la the top view - from the front as a front view - is shown on the timer with closed housing 1, from which one can see the division of the front panel 2 into the control panel 3 and the display panel 4. The control panel ³ itself is also divided into subfields 5 to 8 in accordance with the outline of the control elements, the bottom 5 being the function selection main switch 9 "STEL / AUT" and the group of switching channel selector switches 1o to 13 ("Sl to S4"), the upper strip 14 of the keypad 6 "SET" the function selection keys 15 (CLOCK), 16 (ON switching time) and 17 (OFF switching time), the middle strip 18 and the lower strip 19 the setting keys "h" 2o (hours ), "m" 21 (minutes), "s" 22 (seconds), "d1-7" 23 (weekdays), "Sl-4" 24 (switching channels) and "Q" 25 (acknowledgment); the last one The key mentioned belongs to the variant of the single-digit input that is possible in the two cases "dl-7" and "Sl-4", in which the weekdays and the switching channels are repeated when the control keys are pressed

the associated data is shifted by one digit, ie the previously entered value is deleted and the character concerned is only added to the associated buffer memory to the data that may already be stored there by actuating the "Q" key.

With the function selection key "Sl-4" 26 in the control subfield ⁷ "Test" (ABFR) - also referred to as "AS1" - the query is initiated, with the control key "Check" (ABFR) 27 the actual query of the Time provided complete data set started and the key section 28 "Clear" (CLE) deleted the queried section of the data set. When the function selection key 29 "PROGR" or "AUT" is pressed, automatic operation is restored after an interruption by one of the function selection keys 15, 16, 17 and 26.

Display field 4 shows the ¢ complete data record for a switching time pair - in the case of a query - or part of it when it is first entered after complete deletion - with the switching time image in an upper half 3o for the ON switching time with the symbol "I" 31 and a lower half 32, mirrored from top to bottom, is divided with the symbol "0" 33 and each half except for the times "h", "m" and "s" with a colon between the data for "h "and" m "below and above the same bar marks 35, 36 in seven adjacent positions corresponding to the days of the week and in the right part 37 of the display field 4 arrows one above the other. 38 for the display of the selected switching channels.

The special division of the operating (3) and display fields (4) gives the user a particularly easy and fail-safe setting of the timer data. With the routine selected with the function selector key "CLOCK", he can set the built-in electronic clock by pressing the setting keys 2o to 22 "h", "m" and "s", as well as for the valid weekday "dl-7" - Press as often or as long (for automatic pulse train) until the relevant section value matches the current time, after which he presses the function selection key 29 "AUT" to transfer the set half data record to the buffer for the current time and release the continuation the automatic operation of the electronic timer and thus the ongoing automatic adjustment of the built-in electronic clock.

For the purpose of setting the ON and OFF switching times, the user has only one of the function selection buttons "I" 16 and "O" 17 and then again in succession - in any order - the setting buttons 2o to 25 for the associated switching times, days of the week and Actuate switching channels, also as long or as often until the desired values are displayed in the individual sections; if this is the case, he in turn only has to press the function selection key 29 "AUT" or "PROGR", whereupon the complete data record shown in the display field 4 as associated digits, identifiers and symbols is transferred to the working memory or the associated register and also "AUT" operation is restored.

Here, however, the condition must be met that all sections of the complete data record, possibly also, for example. are entered as "zero" (00) - without actuating the setting keys 2o to 25 belonging to a section, there is no display at all - ie. that the record is "complete". In a simplified version of the electronic time switch, this condition can also be limited to a "half data record", in which case such a time is displayed alternately for the current time, for ON switching time and for OFF switching time - in a less simplified version, however, then Completeness condition is checked for the entire data set.

In addition to the current overview described, the geometric arrangement of the setting keys 2o to 25 and the function selection keys 15 to 17 and 29 in accordance with the order also makes operation easier, because the function selection keys 15 to 17 and 29 are in a common line 39, the group of keys 26 to 28 for the interrogation, correction and deletion in sections, which also includes the total reset by means of the pushbutton 41 "Reset", in a line 4o perpendicular thereto and the actual setting keys are accommodated in the subfield lying between them.

With the function selection main switch 9 in its "AUT" position, the entirety of all stored complete data records are secured against unauthorized or accidental changes by the function selection keys 15 to 17 and 26 and the setting keys 2o to 25 being blocked as ineffective. The peculiarities of the electronic circuit are the subject of a separate and independent description of the same.

In FIGURE 1b, a partial section in the longitudinal direction, the arrangement of the circuit board 51, double-sided self-aligning manner by clamping attachment between ribs 52 which are of the _housing top part is integrally formed on the side wall 53, and the end surfaces of the side wall 54 of the housing lower section supported. The function selection and the setting buttons 55 to 58 are each from a neck, for example. 53, of rectangular cross-section and a head plate 6o composed of a rubber-like material with additives made conductive and in its entirety by an elastic support surface 61 and connected to it integrally and integrally. When one of these buttons is pressed, the contact surface 61 is pressed onto the circuit board below the neck in question and the ends of conductor tracks applied at this point are thus conductively connected, ie. the switch effect. The necks 55 to 59 are formed by the webs integrally formed below the front plate 2, for example. 62, 63, and the support surface 61 through the intermediate webs also integrally formed there, for example. 64 held at a precisely uniform distance from the front plate 2 self-adjusting.

In addition to the control panel 65, the semiconductor compact brick 67 with the display device and associated electronic assemblies is installed directly under the window 68 in the front panel 2 in the display panel 66 and is electrically connected to the circuit board 51 of the circuit board 51 by the associated connecting lugs. On the inside of the printed circuit board 51 are printed circuit boards 69, 7o at right angles to it, as indicated, for mechanical stiffening and for mounting larger components, such as capacitors of the power supply part, a battery for the power reserve, and the relays appropriate.

In Fig.lc is the top view of the bare upper housing part 1 with holes 81, 82 for screwing it to the lower housing part, with openings for the window 83 belonging to the display device, for function selection and setting keys, for example. 84, 85, 86, function selector switch, e.g. 87, 88, and the masks 89, 9 ₀ , 91 for the subfields 7, 7, 8 (in Fig.la).

2a shows in the bottom view of the upper housing part 101 the integrally molded frame lo2 of the window lo3 for the display device (not shown) and the holding frame lo4 for this, as well as the openings, for example. 1 ₀ 5, for the necks not shown here, 106 for example. of the finger lo7 belonging to an actuating key (in FIG. 2c) and the guide ribs combined to form a lattice work lo8, namely integrally molded on the underside of the front plate lo9, for example. llo to 113, on all four sides of the rectangular openings, e.g. 1 ₀ 5, and with each other and with these integrally molded stiffening ribs, eg. 114, 115. You can also see on the inside of the walls, eg. 116, 117, molded support ribs, e.g. 118, 119, for the printed circuit board 12o in Fig. 2a, b, c and d. Fig.2e shows the top view of the completely unpopulated front panel lo9 with the openings, for example. lo5 for a key neck, e.g. lo6) un for a channel switch 121, as well as for the function selection main switch 122 ("STEL / AUT).

3 shows a longitudinal section AB through the housing upper part, which is supplemented by a longitudinal section through the lower housing part 151 and a phantom longitudinal view of the cover housing 152, and which is provided with a compact semiconductor module 153 for the display device and a group 154 of setting buttons. You can see again the clamp fastening of the circuit board 155 between ribs, eg. 156, which are integrally formed on the longitudinal side wall 157, and the lower housing part 151, namely its upper edge. Larger components, such as (again in phantom), relays 159 to 162, electrolytic capacitors 163, 164 and the other parts are arranged on the inside of the circuit boards 158, 159 which are attached at right angles to the underside of the circuit board on the longitudinal edges of the circuit board 155 of the power supply part 165. In this way, even with the new construction with digital electronics, a sufficiently dimensionally stable and space-saving design of the electronic timing device is possible despite its components, which are partially sensitive to changes in geometric dimensions. The phantom view also shows how the pot-shaped cover housing 152 is fastened with the aid of clamping claws in the grooves with internal teeth 166 being put over the housing lower part.

4 a shows a variant of the front view with a different housing shape, in which the display 181 and control panels 182 are arranged one above the other with longitudinal edges abutting one another (to be understood only conceptually). For the rest, the comments on Fig.la apply with regard to the ease of operation due to the geometrical assignment of display area areas and switches or buttons according to their ranking, especially the increase in the displayed values per button or with a long press of a sequence, and for the days of the week and the channels of the ongoing switchover after pressing the button and the transfer to the programming memory only after Actuation of the acknowledgment button in the same way, so that further explanations are unnecessary. The electronic equipment and consequently the equipment of the front panel - apart from the local arrangement - corresponds to that of Fig.la.

The front view for an embodiment electronically disassembled with respect to Fig.la or Fig.4a is shown in Fig.4b. The digits of the display 184, 185 of the ON switching time and corresponding to the OFF switching time indicate the hours or minutes, while the colons 186 arranged between them indicate the seconds or other sections of the minutes. The bars 187, 188 above and below the number line "1 ... 7" show, when the lamp is constantly lit, the one selected by button "dl-7" (189) and permanently saved by pressing the acknowledgment button "Q" (19 ₀ ) Day of the week, whereupon the subsequent bar flashes when the "dl-7" button is pressed and jumps one step at a time until the day in question is saved when acknowledged by the "Q" button (19o) and indicated by a constant light. The symbols "S", "L", "1" and "2" (191) belong to the switching channels, the symbols "I" and "O" (192, 193) show the selected partial data record for setting the ON or of the OFF switching times.

The saved switching times are queried with the "Check" button (194), the queried switching times are deleted with the "Clear" button (195), and the (complete) data record is saved in accordance with the switching time image in the "Program" (196) button Display in memory; the button ("clock picture") (197) is used to set the continuously running time in the background, the button "I / O" (198) to choose between "ON" and "OFF" switching times, and to start the Operation of the timer for setting and automatic operation, switches 199 and 2oo of the operating or channel circuit can be set to "Set / Program" or "Automatic / independent of this". The parts with a dashed line are missing in the single-channel version of the time or time program switching device.

The cross sections GH, EF and LO in Fig.5a, b and c, through the housing upper part 2 ₀ 1, the one in Fig.5b by the cover housing 2o2 in close to the usual graphic representation and supplemented by the lower part 203, 203 inserted in the phantom, let in particular the various types of supporting, holding and clamping aids in the form of integrally molded ribs 206, 2o4 or side walls 2o5, Recognize supports 207, 2o8, etc., as well as the lattice work of reinforcement 21o and guide ribs 211, 212, which is integrally formed on the underside of the front plate 2o9, and the receptacle 213 for the screw sleeve 214, which is also integrally formed on the cover housing 2o2. The printed circuit board 215 is together with their side circuit boards 216, 217 between the upper housing part 201 and the lower housing part 2o3 with the aid of the ribs, for example. 2o6 and 21o clamped correctly in accordance with distance and shape. One side printed circuit board has a connector plug 219 on the part protruding from the floor.

The lower housing part (151 in FIG. 3) is shown with a bottom view, a longitudinal section EF and a top view in FIGS. 6a, b, and c. To be emphasized here is the height-offset form, which on the one hand offers a larger space for power supply in the room part 221, while the elongated room part 222 offers space for connector strips, means for connecting the installation and the lower room part 225 for the larger components , such as electrolytic capacitors, batteries and relays is sufficient, on the other hand, the circuit board with the connector strip extends through the slot 223 in the intermediate floor 224. The grooves 226, 227 with offset toothed inner surfaces 228 and the integrally molded sleeves 229, 23o for screwing to the upper housing part are arranged on the side walls. On the underside of the intermediate floor 224, the spacer bars 231, 232 for the self-adjustment of the distance and the position of the cover housing are also in one piece forms.

In Fig.7a for a longitudinal section AB, Fig.7c a cross section IK, Fig.7d for a cross section GH and Fig.7e for a longitudinal section CD through the lower housing part and Fig.7b for a side view in the direction of arrow N and Fig.7f for a side view in the direction of arrow O on the lower housing part, the special features are given the same designations as in FIG. 6, so that further explanations on this are not necessary.

8 and 9 show the cover housing (202 in FIG. 5b) in cross sections JK (FIG. 8a), L-0 (FIG. 8c), in longitudinal section AH (FIG. 8b), in a top view of the interior (FIG .8d), repeatedly shown in bottom view (Fig.9a) and front view (Fig. 9b). The screwing sleeves (214 in Fig. 5b) are designated 241, 242, on the side walls are integrally molded ribs, for example. 243, 244, for supporting the side walls of the lower housing part (FIGS. 6 and 7) on the lugs (233, 234) of the upper edge. Break-out opening areas 247 and 248, 249, 25o are provided in the floor 245 and in the front wall 246 for connecting lines and assembly. Other integral parts are, for example. the fitting parts 251 for the lower housing part.

The circuit-specific features are explained below with reference to FIGS. 10 to 14. First, Fig.lo shows a simplified block diagram with the most important electronic components. In it, the buffer 301 for the sections 3o2 to 3o5 of the current time, which are connected as consecutive counters with the levels 6 ₀ (s), 6 ₀ (m), 24 (h) and 7 (d) and both at non-drawn position of the switch 3o6 from the buffer 3o7 with a data record read in there, set the current time, and the electronic clock (buffer 3 ₀ 1) can be continuously fed from the frequency divider pulse source controlled by an oscillator 3o8, as well as the sections of the buffer 3o7 the programming memory 31o sections invite, its portions ^g by actuation of the setting keys 311 and with switch to oN or oFF switching times e-set switch 311 by means of clock pulses from the clock generator 309 are set. Depending on the position of the changeover switches 311a, the positions “I” and “O” can be used to store two half-data records in succession from the programming memory and vice versa, depending on the position of the changeover switches 311a. The buffer memory 3o7 can be connected to the input memory 312 of a display device and to the main memory 313 via the line group 314.

In automatic mode, a complete data record is shoveled from the main memory into the intermediate memory 3o7, while the current time is displayed by the display device. The latter and one of the two half data records for ON and OFF switching times are located in sections at the inputs of the logic comparator units 314, which, in the case of equality, have a signal at their outputs via the AND logic elements 315 (not shown in detail) for all Sections switch the switching devices together with the signal of the channel selection section 316 to the ON or OFF operating state.

11 shows a schematic overview of the division of the overall block diagram with logical parallel logic levels and the association of the block diagrams 11a to 11d:

The subgroup of Fig.lla with the function selection buttons 321 (CLOCK) for the current time, 322 (ON), 323 (OFF) for the ON and OFF switching times, 324 (AS1 ...) for the query channel Preselection and 325 (AUT) for taking over the automatic operation of the electronic time switch are on one side at the clock pulse source T ₁ , T ₂ - which still has to be explained - and are on the output side via the AND elements with the complementary outputs Q of the FLIP-FLOP - Links 331 to 335 of the other function selection keys linked. This has the consequence that the FLIP-FLOP element (eg. 332) controlled by pressing a key (eg. 322) does not have the inputs of all other FLIP-FLOP elements 331, 333, 334 and 335 through its Q output enabled AND gates 326, 328, 329 and 330 blocks.

H signals are on the output lines 336 (CLOCK), 337 (AUT), 338 ("I") and 339 ("O") and 34o (AS1, ..) as long as no other function selection key than that of the set FLIP-FLOP element has been actuated. The function selection main switch "AUT / STEL" 341 is located at some point in the circuit, as a result of which the same output effect as with the "AUT" function selection button 325 is achieved - but blocked. The switching channel actuating switches 342 serve to block the control circuit of the switching devices in one of the operating states: remain ON, remain OFF or remain inactive.

The subgroup of Fig.llb with the control buttons 351 (weekday "d"), 352 (hour "h"), 353 (minute "m"), 354 (second "s"), 355 (switching channel "Sl ... "), 356 (query" ABF "), 357 (acknowledgment, ie taking over the weekday or shift channel shift setting" QUI ") and 358 (deletion" CLE ") is on one side of the clock pulse source via line 359 and is connected to T ₁ and T ₂ - for which an explanation follows - and is on the output side of an input of AND gates 36o to 367, while the other input is connected to that Q -Output (343 in Fig.lla) of the FLIP-FLOP element 335 assigned to the function selection key 325 "AUT". As a result, all setting keys of this group 351 to 358 are blocked as ineffective in automatic operation, the outputs of the AND elements 36o to 365 drive the monostable FLOP elements 368 to 373, of which those 368 to 373 provide signals for further links.

The set outputs of the monistable FLOP ^t elements 332 and 333 (Fig.11a), as by circles, e.g. 374, indicated, are linked by OR gates 375, 376 so that they indicate output signals via FLIP-FLOP gates 379, 38o as to whether all of the relevant setting keys are actuated; only then is an H signal given both for the control routine "ON" and for that "OFF" and passed on via the AND gate 377 on line 378 for a positive result of the completeness check. These output signals also control, via an OR gate 381, a time-delayed monostable FLOP gate, the complementary Q output signal 382 of which is on the reset line 383 for the reset inputs. The "ABF" key 356 thus only causes the reloading of a data record stored in the working memory into the input memory of the display device and thus an interruption of the "AUT" routine if the "AS1 ..." function selection key has been actuated beforehand, ie . a signal is present on line 384 and enables the forwarding of the "ABF" signal to line 386 via AND gate 385.

The actual set signals go from the relevant output of one of the AND gates 36o to 364 to the individually assigned sections of the intermediate memory 387 to 391 and set them to the corresponding values of the programming memory depending on the number of clock pulses entered; the buffer sections 387 and 391 are designed as shift memories, so that after each input which is to be stored, these are entered into the actual register by a signal at the output of the AND gate 366 belonging to the acknowledgment actuating key "QUI" 357 387 ^: or 391 ^{t -} possibly in addition to the positions already occupied - must be saved. The data contents of the "switching time" and "switching channel" sections are taken from the outputs 393 and 394 of the programming memory 392.

11c shows the function selection signals "I", "O", "AS1 ..", 4 ₀ 1 to 4 ₀ 3, and the control signal "ABF" 404 with the outputs "SZ" (switching times) 4 ₀ 5 and "SK" (switching channels) 4o6 the inputs and outputs for ON switching time - 407, 4o8 and OFF switching time 4 ₀ 9, 41o of the buffer for the complete data set, and switching channel 411, as well as the input of the electronic clock 413 and the input 414, as well as the outputs 415 (ON switching time), 416 (OFF switching time) and 417 (switching channel) of the working memory 418 through a chain 419 of AND gates and the AND gate 430 of the latter together with the completeness signal logically linked on line 421 (378 in Fig. 11b). The data transports in connection with the working memory 418 are controlled by the central unit 422 including decoder in connection with a program memory 423 and possibly with an external additional read / write memory 424.

In Fig.lld are the assemblies of the electronic Clock 441 with the time segment stages 442 (day of the week "d"), 443 (hours "h"), 444 (minutes "m" and 445 (seconds "s") with the clock generator 446, consisting of an oscillator 447 and various divider stages, e.g. for 1 ms, 1/2 s, 1/8 s and 1 s clock output, e.g. T ₁ and T ₂ , as well as (1 s) for the ongoing advancement of the electronic clock 441 The time segment stages 442 to 445 can also be set from the programming memory (392 in Fig.llb) via line 448 and the AND gate 449. The presence of the function signal "CLOCK" on line 45o.

From the clock generators 446, two different clock signals are released alternately via the AND gates 466, 467 by controlling the second inputs from a time-delayed monostable FLOP gate controlled via the line 468 to the outputs T ₁ and T ₂ after a period of time. With this arrangement, the time-delayed switching of the clock signal input takes place with the setting keys from individual pulses to a sequence of faster clock pulses.

The basic block diagram of FIG. 12 as a section shows an example with logical serial logic stages for the comparison of data record sections using shift registers when processing the time comparison of time and programmed ON or OFF switching time. The associated data and half data sets are in registers 471 and 472 for the days of the week, 473 and 474 for "h", "m" and "s" for the current time and the stored switching time, and registers 475 and 476 for the switching channels of an intermediate memory loaded from the working memory 477 via the lines 479, 48o and 481 chers 478 filed. Shift registers 482 to 485 and 486, 487 are assigned to registers 472, 473 of the switching times on the input side and output side and the registers for the switching channels only on the output side. When a clock pulse is applied, the shift registers each switch the input and / or the output of the relevant time segment register to the next one.

The clock pulses are generated by multiple linking by means of AND gates between clock signal line 488 via a first AND gate 489 with the AND gates controlled by CARRY and STATUS output signals of the comparator stage 49o with a 491 negated on one side and a 492 negated on both sides ' Approved. If, at the next clock pulse, the comparator element 49o determines equality and the CARRY and STATUS outputs are high, the AND element 493 is released and a clock pulse is transmitted to the further shift registers 484, 485 and via the counter 494 and the AND element 495 487 is given so that the comparison for the next section is released. If the comparator stage 49o outputs the STATUS and CARRY signal = 1 (H) in this case as well, then the memory sections for the identically identified switching channels from the registers 475, 476 are switched through to the output 496 via the enabled AND gate further control processes are triggered. In this example, the individual data record sections are not queried in parallel, but in series.

The excerpt from a principle block diagram of FIG. 13 works according to the same principle as in FIG. 12 for an example of the evaluation of the setting key codes. For example, are stored in register 5ol. the constants corresponding to the key codes for the subordinate Be Reichs, namely "QUI" (3), "CLE" (4), "Sl-4" (5), "TAG" (6), "SEK" (7), "ABF" (6), "STU" (9) and "MIN" (A), in register 502 for an "ABF" subroutine for the "QUI" key, which in turn corresponds to the key codes constants for "TAG" (6) and "Sl..4" (5), in a register 5o3 for the "ABF" subroutine for the CLE key the constants "TAG" (6), "TAGIO" (1), "STU" (9), "MIN" ( lo = A - hexadecimal code!), "SEK" (7) and "Sl..4" (5) saved. By means of the shift registers 5o4 to 5o8, these constants are sequentially read out from the key switch (or switch contacts) matrix (563 in FIG. 14) and in intermediate storage locations "STELF" 5 ₀ 9, "TASMRK ₁ " (51o or " TASMRK ₂ "511 stored key codes compared and depending on the result of the logic comparator 512, the CARRY and STATUS signals through AND gates 513, 514 and 515 unchanged, with one and with two negated inputs, linked to the clock signal and, accordingly, the register positions switched from level to level until equality is determined and then the procedure is switched on in a subordinate register, e.g. 5 ₀ 2, 5o3 etc. The output signals then control via further AND gates 516 and another shift register closes the signal circuits for the following circuit groups.

14 shows the exemplary embodiment with a microprocessor in which the modules arithmetic-logic unit (ALE) 551, buffer group 552, input and output register R 553, output register D 554, working memory 555 including programming memory, Buffer for complete data sets, program memory 556 including program counter, return address memory and table memory, operation part decoder 557 and display device including auxiliary modules and clock 558 are integrated. There are reads on the input and output register Lines 559 and address lines 56o, 561 of the function selection switches, keys and setting keys combined to form a matrix 563 are connected in such a way that the codes of the lines result in the switch and key codes being divisible into constant ranges, for example. the higher-level function keys "CLOCK", "ON", "OFF", "AS1 ..", in the constant range greater than 10 (A), the lower-level control keys "h", "m", "s", "d1-7 "," S1..4 "," QUI "," ABF "and" AS1 .. "in the area less than / equal to lo (A) and greater than" 2 "and the" AUT "key in the area less / are equal to 2. In this way, a clear query with fairly few work steps is possible in all three cases. The output signal of the logic combination or comparator stage 551 controls the relays 562 via intermediate modules 561 and further logic elements.

When the program is being processed, the operational parts of the command words of the program memory are processed in accordance with the steps of the command counter, as it corresponds exactly to the serial, logical operation of the exemplary embodiments in FIGS. 12 and 13, which operates purely in hardware.

15, the simple and clear handling of a time or time program switching device according to the exemplary embodiment in FIG. 4b can be explained. After pressing the "Check" button (194) for the first time, an empty display (6 ₀ 1) with the number line "1 ... 7" for the days of the week and the symbols "-S", "L ₁ " and "L" for the previously set or not set channels, when the button is pressed again, the first switching time image - starting with Monday, but still without its on show - 00:00 (602) visible. After a further query of switching times, the picture "FULL" (6o3 "comes at some point, namely when the memory capacity reserved for SL ₁ has been used up. Then the channel" S-L2 "is selected when the" Check "button is pressed again Repeated actuation until "FULL" appears, the channel "SL ₁ " is automatically switched back to and the empty display (6 ₀ 1) is shown again After pressing the "I / O" button (198), the ON circuit diagram (6o4) for the first setting, shown here at 00:00 for "I".

After the "I / O" button has been _{pressed for} the ^{first time} and the "Check" button has continued, if the "h", "m", "dl-7" and "Sl-2" buttons have already been pressed, the switching times 6o5, if necessary consecutively. If this operation had not yet taken place, the ON ("I") and OFF ("O") switching times can be selected according to the preselection using the "I / O" button using the "h", "m", "dl-7" and "Sl-2" can be entered (6 ₀ 6 or 6o7). In the following, the entered switching time data, ie. delete the displayed and the last pressed key by pressing the "Clear" button (6 ₀ 8) and / or use the "CLOCK" button to display or set the current time (609) or by pressing the "Check" button instead "call up the relevant switching time image (61 ₀ ) without transferring it to the main memory; if "FULL" is displayed (611), the current time (612) appears on the display.

Fig. 16 shows that the display, change and deletion of the data of the displayed, set days of the week and switching channels takes place in the same simple way. The days of the week for the ON switching time are there in each case in the upper line and for the OFF switching time in the lower - in accordance with the picture 6 ₀ 5 on the display - shown as a series of bars that may light up next to each other, with "flashing" hatched and "constant", ie. are drawn in solid black. In Fig. 16a ^, 1) the sequence of the bar images according to the actuation of the pushbuttons "dl-7", if necessary or in part several times, "Q" acknowledgment and 2) the switching time data record corresponding to the setting of the days of the week. Excerpt reproduced. In Fig.l6b is shown how the setting according to 1) by pressing the button "dl-7", again sometimes several times without acknowledgment, and the button "Q" the setting of Tuesday and Wednesday is expanded by the additional days of the week Thursday and Saturday , 3).

In Fig.l6c, top 1), the absence of a setting of ON switching days is indicated, which is eliminated by pressing the "dl-7" button 2) and pressing the "Q" button twice. In Fig.l6d, line 1) the flashing of all bars shows that no day of the week is set at all, which is why according to 2) by pressing the "I / O" setting to ON, ie. "I" - and pressing the "dl-7" and "Q" buttons and then 3) resetting the "I / O" button - setting to OFF, ie. "O" - and also pressing the buttons "dl-7" and "Q" the data record section for the days of the week must be corrected. It is just as easy to correct an incorrect setting according to Fig.l6e - here more ON switching days than OFF switching days in line 1) - by preselecting the OFF switching times "O" using the "I / O" button and pressing the "dl" button -7 "and" Q "for setting the weekdays Monday, Tuesday, Wednesday and Friday and acknowledging them for storage.

Fig.16f ₁ , line 1) indicates an incomplete entry of the switching channels (only ⁿ SL ₁ "), which is supplemented by pressing the button" Sl-2 "and" Q "to that according to line 2), as the sequence of In the event of an incorrect setting according to line 1 of FIG. 16f ₂ to the second switching channel, the button "Sl-2" is used to switch to the first switching channel, the symbol flashing, and then by pressing the button "Q" this correction can be saved.

17 shows a block diagram for an example of the compatibility check (plausibility) of the individual data of the complete switching time data record found complete by the completeness check in the programming memory 621 with the partial areas for the symbol "I" 622, the weekdays "d" 623 , the switching time of day in hours "h", minutes "m" and seconds "s" 624, of the ON switching time partial data record, and correspondingly the symbol "O" 625, the days of the week "d" 626, the switching time of day 627 of the OFF switching time partial data record with the switching channel or the switching channels "SK" 628 associated entered data for possible contradiction (s). These include, for example. the setting ON switching time equal to OFF switching time for the same weekdays and the same switching channels. Under the condition d _I (number) = d ₀ (number), SK _{I is} equal to SK _O the condition must be met: ^T p _{/ I} less than T _{P / O} ^T _{p / I} switch-on time T _{P / O} switch-off time all in all Programming memory 621.

There are further possibilities of contradictions between the data records in the programming memory 621 and one or more switching time data records in the working memory (418) with the associated address counter 629, from which, for the purpose of checking for compatibility, in each case a complete, complete switching time data record (63o) together with at least the following half data record 631 for the same day of the week (e) and the same switching channels are read into the buffer memory 63 ₀ , 631. These switching time data records necessarily have the same structure or the same composition from partial areas, as described in connection with the programming memory.

Folgende Voraussetzungen müssen auf jeden Fall erfüllt sein:

Dann müssen folgende Fälle von der Weiterleitung der im Programmierspeicher enthaltenen, eingestellten Daten in den Arbeitsspeicher ausgeschlossen sein: T_P/I größer als T_A/O ; T_p/O größer als ^T _A/I/AZ+1 unabhängig davon muß aber auch T_P/i kleiner als T_A/I des gerade aus dem Arbeitsspeicher ausgelesenen Datensatzes sein. Bei der Prüfung auf diese Bedingungen, die als besondere Beispiele ausgewählt wurden und wobei noch weitere zu berücksichtigen sind, ist zwischen folgenden Fällen zu unterscheiden:

Diese Bedingungen sind - zum überwiegenden Teil - in dem Blockschaltbild der Fig.17, das als Ausführungsbeispiel überdies nur eine Auswahl der möglichen Lösungen für die Realisierung wiedergibt, dadurch als Logikplan nachgebildet, daß zunächst in zwei Vergleicherstufen 632, 633 die Anzahl der Wochentage als Wort⁶³⁴bis drei bit für den Einschalt-Teildatensatz-Abschnitt d_I mit demjenigen Wort 635 für d_O einerseits und die durch die Schieberegister 636 und 637 jeweils ausgewählte höchstwertige Stelle der Schalt-Tageszeiten - Teilabschnitte 624, 627 - in Zwischenregister 638, 639 umgespeicherten Werte andererseits verglichen werden und folglich an den Ausgängen der NAND-Glieder 64o, 641 nur dann ein H-Signal, dh. am Ausgang des UND-Gliedes 642 nur dann ein Freigabesignal (H) an den ersten Eingang des UND-Gliedes 643 weitergegeben wird. Dann sind überhaupt erst die oben geschilderten Voraussetzungen zum ersten Teil erfüllt.The following sub-areas (index "I" means belonging to the switch-on times, index "O" to the switch-off times, index P to the programming memory and index A to the main memory, "T" means switching time of day) must be compared and related to each other put:

The following requirements must be met in any case:

The following cases must then be excluded from forwarding the set data contained in the programming memory to the working memory: T _{P / I} greater than T _{A / O} ; T _{p / O} greater than ^T _{A / I / AZ + 1} independently of this, however, T _{P / i} must also be less than T _{A / I} of the data record just read from the main memory. When examining these conditions, which have been selected as special examples and which still have to be considered, a distinction must be made between the following cases:

These conditions are - for the most part - reproduced as a logic diagram in the block diagram of FIG. 17, which, as an exemplary embodiment, also only shows a selection of the possible solutions for the implementation, in that the number of the first in two comparator stages 632, 633 Days of the week as word ⁶³⁴ to three bits for the switch-on partial data record section d _I with that word 635 for d _O on the one hand and the most significant digit of the switching times of the day selected by shift registers 636 and 637 - sections 624, 627 - in intermediate register 638, 639 values stored on the other hand are compared and consequently only an H signal at the outputs of the NAND gates 64o, 641, ie. at the output of the AND gate 642 only then an enable signal (H) is passed on to the first input of the AND gate 643. Then the above-mentioned requirements for the first part are only fulfilled.

In a corresponding manner, the requirements regarding the switching channels Kp and K _{A are} determined by the comparator stage 644, for the number of days of the week d _{A / I} b ^between . d _{A / I / AZ + 1} (in buffers 645 and 646) and the number of days of the week d _{p / O} or d _{A / O} (buffers 635, 647), as well as dp _{/ I} or d _{A / I} in the Comparator stages 648, 649, the data of the symbols O _{/ P} and O _{/ A} in the partial areas 625, 65o and finally the data of the symbols I _/ p and I _A b ^z w. I _{/ A / AZ + 1} (the latter in the subareas 651, 652) checked or compared in the comparator stages 653, 654; the result signals of these comparator stages must be H without exception, so that the AND gate 655 also supplies an H signal at its output, which is present at the second input of the AND gate 643 and at the first input of the AND gate 643a, the output signal of which addresses counter 629 increased by one. This completes the second part of the prerequisites.

The actual plausibility check consists of the further linking steps: First, the selected registers and the intermediate registers are located at the inputs of comparator stage 656 via shift registers 636 and 657 638 or 658 re-stored data of the most significant digits of the ON switching times Tp _{/ I of} the programming memory 621 or T _{A / I of} the working memory 418, ie. the buffer memory 63o - that is to say the addressed switching time data record; At the inputs of the comparator stage 659, the selected data of the most significant digits of the OFF switching times T _{P / O of} the programming memory 621 and TA / 0 of the buffer memory 63o are located via shift registers 637 and 66o and stored in the intermediate registers 639 and 661, respectively of the working memory 418 - with the same addressing as with the ON switching time of day - on; Finally, at the inputs of the comparator stage 662, together with the output signals of the intermediate registers 638 and 663 - the latter via the shift register 664 - the data of the most significant digits of the OFF switching times T _{p / O of} the programming memory 621 or T _{A / I / AZ + 1 of} the next higher address of the working memory 418 for the same days of the week and switching channels.

The outputs of the comparison stages 656, 659 and 662 are through the OR gate 665, the AND gate 666 and partly via the AND gate 643a, the output signal of which increases the address counter 629 by one, and finally the AND gate 667 is linked in such a way that that on the output line 668 - if conditions are met - an enable signal for the transfer of the complete switching time data record in the programming memory 621 to the addressed subarea between AZ and AZ + 1 of the main memory 418 occurs via the line 669 and the AND gates 670, 671; the AND gate 671 is also only conductive if the enable signals of the completeness check are applied to its inputs 672, 673 (outputs of the AND gates 375, 376 in FIG. 11b). The outputs 415 to 417 and the inputs, 418 entspre including for W / R and C / S switching of the working memory _- Chen those of Fig.11; An enable signal for deleting the data record or its partial areas in the programming memory or — depending on the actuation of the pushbuttons — the working memory is issued via line 674.

Additions to this exemplary embodiment of the compatibility check are readily possible for any person skilled in the art on the basis of the above description in connection with FIG. the use of further tests is only a question of the maximum allowable effort. However, this is usually not so important if the data links are carried out by means of serial processing according to a program, to which the example of parallel processing can easily be transferred, as has already been explained in connection with the completeness check.

Claims (32)

1. Electronic time or time program switching device, containing an electronic clock with clock generator and several divider stages for time segment data signals, for example. Day of the week "d", hour "h", minute "m", possibly second "s", or the like, and clock signals for larger periods of time, a central unit with read / write work memories with addressable cells or registers as groups of these and / or read-only memories, computer, ie. arithmetic-logic unit or comparator stage (s) for processing the data output signals of these modules, as well as program memory with associated program counter and decoding devices for the generation and distribution of function signals for the control of electronic modules of the central unit, a luminous digit device divided into partial areas (3o, 32) with display fields (4) for groups of numbers, letters, identifiers and / or symbols, an input unit with the display fields (4) assigned to operating elements, such as buttons and switches, grouped into sub-areas, an output unit for the excitation or de-excitation of switch devices, eg. electromagnetic relays, electronic switch devices, or the like, for consumer circuits, possibly with several channels and / or switching amplifiers, Control and power supply modules and a housing, in the front wall of which operating and setting fields and at least one luminous digit device are arranged,
characterized in that (a) the controls for (a _l ) a first function selection, e.g. for "AUTOMATIC / / SET" (9) and / or switching the switching channels (lo to 13) on and off as an on / off switch or changeover switch (341), (a ₂ ) a second function selection, e.g. for current time (CLOCK) (15), on (ON) (16), off switching times (OFF) (17), switching channel (AS1, ...) (27) and / or automatic (AUT) (26 ) as the function selection button (321 to 325), and (a ₃ ) the setting of the switching time data "h" (2 ₀ ), "m" (21), possibly "s", the choice between ON and OFF switching time input, the choice of days of the week (23) or switching channels (24) and their temporary storage as a setting button for the input of divider stage impulses se or selection and acknowledgment button (25)
trained and connected to control inputs or outputs of the central unit, (b) the sub-areas (3o, 32) with display elements for time data of ON (3o) and / or OFF switching times (32) and output switching channels (37) associated signals together with those of indicators, eg. "I" (31) and "O" (33) for the assignment to the on and off times, and / or symbols, for example. Colon (s) (34) between "h" and "m" display elements, e.g. for the continuous display of the second cycle by flashing, display elements for seven bars (35, 36) which can be arranged next to one another, for example. Arrows (38), for the days of the week etc. by means of one of the function selection switches or pushbuttons with mutual exclusion or mutual release of a single one in any order in assigned buffers at least partially with adapted limit value overflow, for example. for seven days of the week, ten tens and six ones at the times, and / or with two inputs for opposite polarity ("+/-") of the pulses to be entered, (c) wherein the data set signal group for ON and OFF switching times and the associated switching channels can only be adopted in its entirety from buffer cell groups into the central unit and processed there by:
the signal groups of the partial areas of the data records to the corresponding inputs or outputs of a programming (392) or a read / write work memory (412 to 418) can be connected via logical parallel and / or serial linkage or comparator stages. 2. Time or time program switching device according to claim 1, characterized in that the separately addressable cells or registers as groups of them the programming and the read / write working memory (a) a partial programming memory (in 392) for a half data record with time data or data of the ON or OFF switching times and, if appropriate, the switching channels and, if appropriate, spatially separated therefrom, at least in part by an external additional read / write - memory expandable working memory (418), (b) at least one auxiliary register (412) for a complete data set with ON and OFF switching time data including data for days of the week and, if appropriate, for switching channels (c) separately addressable buffers in the main memory (418) for data of the time (441 to 445), or the ON and OFF switching times, for data of the days of the week, for data of the switching channels, for data of the actual states of the switch devices, for setting indicators and / or flags for switch and / or button codes, constants, addresses, and time counter data, or the like.,.
are assigned, whose write inputs (4o7, 4o9, 411, 414) to outputs (321 to 325, 351 to 358) of the input unit and / or the other registers (393, 394) and their read outputs (415 to 417) to inputs of an input memory (412) of the luminous digit display device or an associated one Buffer can be connected. 3. Time or time program switching device according to one of claims 1 and 2,
characterized in that the outputs (393, 394) of all the cells of the programming memory (392) assigned to the locations of the complete data record for the purpose of checking for completeness at the inputs of a logical assembly group linking with AND and / or NAND elements and / or counters , Shift registers and / or a comparator stage (375 to 377, 379, 38o) or any such serial multiple functions, the output signal of which is at an input of an AND gate, the other input of which is connected to the output of the programming memory and the outputs of which if the link condition is fulfilled Corresponding inputs (414) of an auxiliary register in the main memory (418) are connected, whereas if the display element is not fulfilled, it flashes a signal to the areas of the memory cells that are not used. 4. Time or time program switching device according to one of claims 1 to 3, characterized in that the outputs (378) of all Providing the cells of the programming memory (392) assigned to the complete data record for the purpose of checking the compatibility or plausibility of the input data at the inputs of a logic combination module with AND- (642, 643, 643a, 666, 667), NAND- (64o, 641 ), OR (665) or EXOR gates and / or counters ((634, 635, 645, 646, 647), shift registers (636, 637, 657, 66o, 664) and / or comparator stages (632, 633 , 644, 649, 648, 653, 654, 656, 659, 662) or any such serial multiple functions whose output signal is at an input of an AND gate (67o, 671), the other inputs of which are connected to the outputs of the programming memory ( 392) or its other input are connected to the output of the AND element (67o, 671) belonging to the logic module for the completeness check, this connection (s) only being established if the compatibility condition is met or if the condition is not met the non-compatible memory cell len belonging display elements with a flashing signal. 5. time or time program switching device according to claim 4, characterized in that the outputs of a first, ie. of the ON circuit partial data record of the programming memory (621) and the read outputs of a second, ie. of an ON circuit partial data record (from 651) of the read / write work memory (418), by means of an increasing sequence from an ON circuit partial data record if the following associated OFF circuit partial data record is present to the next ON circuit partial data record which can be connected continuously by an increased address counter (629) addressed by the result of a comparison stage with AND gates (655, 643a) to data records of the same channel data, wherein the address counter (629) is incremented until a third, ie. an ON circuit partial data record (from 652) of the read / write random access memory (418) is just larger than the OFF circuit partial data record of the programming memory (392), but the ON circuit partial data record of the latter is still larger as the read / write RAM (418) row off line record, the result signal of the comparator stage if the first ON and the fourth OFF partial data record of the programming memory (392) or the first ON and the second ON circuit partial data record on the one hand and the fourth OFF and the third OFF circuit are identical Partial data record on the other hand of the programming memory (392) or of the read / write working memory (418), and if finally a fifth, ie. on the third, ie. the OFF circuit partial data record following the ON circuit partial data record of the read / write random access memory (418) is smaller than the fourth, ie. the OFF circuit partial data record of the programming memory (392), the transfer into the read / write working memory (418) by the AND gates (67 ₀ , 671) and on the other hand with a positive difference between the first ON and the second ON circuit partial data record and / or between the fourth OFF and the third OFF circuit partial data record while deleting the stored complete ON / OFF circuit data record in the read / write work memory, the takeover of the relevant complete ON / OFF Circuit record in the programming memory (392) in the read / write main memory (418) releases. 6. Time or time program switching device according to one of the An Proverbs 1 to 5, characterized in that the content (s) of one, several or all cell (s) or partial areas of a register belonging to the displayed data record for at least one preselectable channel and / or day of the week by actuating the or . the associated button (s) can be replaced or deleted independently of the other sub-areas. 7. Time or time program switching device according to one of claims 1 to 6, characterized in that the content of at least one line of a portion of the register belonging to a data record by individual actuation of a control button by one value level or, if appropriate, according to the Expiry of a predetermined waiting period of continuous actuation by which several value levels can be set or changed, and / or selectable in an increasing or decreasing sense by means of a "-" or "+/-" additional switch. 8. Time or time program switching device according to one of claims 1 to 7, characterized in that in each of the signal circuits for the actuating buttons (351 to 358) a logical AND or OR parallel and / or serial Linkage level (36o to 367; 326 to 335) for canceling the electrical effect of the previously activated radio tion selection button (321 to 325), ie. for CLOCK, ON, OFF, AS1 ..., AUT, and vice versa. 9. Time or time program switching device according to one of claims 1 to 8, characterized in that in each of the signal circuits for the control buttons (351 to 358), for example. "d", "h", "m", "s", "Sl ...", ABF or CHECK, QUI, CLE, a logical AND or OR parallel and / or serial link level (36o to 367) for blocking the electrical effect of the former using the function selection button (325). 1 ₀ . Time or time program switching device according to one of claims 1 to 9, characterized in that the input memory for DAY (day of the week) and / _or the KAN is designed as a sliding memory (387, 391) and between it and the corresponding register (387 ' , 391 ^r ) there is a logical parallel or serial link stage (for example AND gate 366) for the acknowledgment in the case of multiple storage of TAG or KAN data or associated flags. 11. Time or time program switching device according to one of claims 1 to lo, characterized in that between the input circuit the function selection button (321 to 325) and the actuating button (36o to 367) a logical parallel and / or serial link stage (326 to 335) for blocking their electrical effect by the function main selector switch "STEL / AUT "in one position. 12. Time or time program switching device according to one of claims 1 to 11, characterized in that the switching channels are assigned channel selector switches (342), by means of which the channels can be set independently of the function and control buttons and these can be set at a higher level. 13. Time or time program switching device according to one of claims 1 to 12, characterized in that in the signal circuit of the control button for "h", "m", optionally "s", a logical parallel and / or serial linkage stage ( 375, 376, 379, 38o) for enabling the signal circuit of the ABF (or CHECK) button when the AND condition is fulfilled with the signals of the function selection button AS1 ..., then the ON or OFF and if necessary the DAY (weekday) button is located. 14. Time or time program switching device according to one of claims 1 to 13, characterized in that in the signal circuit of the function selection (321 to 325) and the actuating buttons (351 to 358) a logical parallel and / or serial linkage stage with the signal circuit of the CLE button (358) for canceling the electrical effect immediately before pressing the button or deleting the associated section of the displayed data record. 15. Time or time program switching device according to one of claims 1 to 14, characterized in that in the signal circuit of the function selection button a shift register device for switching it from the control circuit of a respective one of the associated function selection circuits to a next one, for example. in the order "CLOCK - ON - OFF - AS1 ... - AUT - CLOCK .... etc." if the function selection button is pressed in succession. 16. Time or time program switching device according to one of claims 1 to 15, characterized in that in the signal circuit of the control button, for example. "h", "m", possibly "s", a shift register device for switching the former in the order given to the next, in the case of the actuating buttons "d" and "Sl ..." with the interposition of a Logical parallel and / or serial link level for the previous actuation of the "QUI" button after one or more actuation of the relevant actuating button when the AND- Condition. 17. Time or time program switching device according to one of claims 1 to 16, characterized in that the signal circuit of the function selection button a timer for its resetting after a preset period of time, for example. Contains 40 seconds if none of the control buttons are pressed within this period. 18. Time or time program switching device according to one of claims 1 to 17, characterized in that the controls arranged in groups in priority levels, namely as a function selection switch (9 to 13), function selection button (15 to 17; 26 to 29 ) and control buttons (2o to 25) in a matrix with addressing lines in one and reading lines in the other coordinate, the controls being arranged at their crossing points, and so combined that when the address assigned to the respective control is connected to the assigned A CODE occurs at the output of the reading lines, which is clearly defined for the groups of operating elements in characteristically limited number ranges, e.g. for buttons within the hexadecimal range 0 to F, eg in its lower part. "2" for the "AUT" button, in its upper area, eg. larger than "lo" for the function buttons (hexadecimal size ser than "A"), and in its middle range between "3" to "lo" or "A", both included, for control buttons except "AUT". 19. Time or time program switching device according to one of claims 1 to 19, characterized in that between each of the function selection buttons connected to a clock pulse source and the inputs of the logical AND or OR parallel logic stages for the data inputs of the modules for current time, also for ON and OFF switching times, switching channel of the programming memory, as well as the input memory of the luminous digit display device, as well as the auxiliary register for a complete data set (e.g. 621, 63o, 631), as well as the buffer for data of the current time (442 to 445), or the ON and OFF switching times, the days of the week, the switching channels (2o7 and 412), an AND gate and a FLIP-FLOP element (36o to 373), with the other inputs the former the Q -Outputs of all the other latter are connected so that the FLIP-FLOP modules of all others are reset when one of the function buttons is pressed. 2 ₀ . Time or time program switching device according to claim 19, characterized in that between each of the control buttons connected to a clock pulse source derived from the clock module and the inputs of time Section divider stages and the switching channel stage, an AND logic element, to the other input of which the Q output signal of the FLIP-FLOP element assigned to the "AUT" key is connected, and a monostable FLOP element with a time-limited duration of the Q. -Output signal and automatic reset after a predetermined time, whose Q output in combination with the output signals of the FLIP-FLOP elements of the function signal buttons "ON" and "OFF" each control a FLIP-FLOP element, whose Q output signals bring together in an AND gate an enable signal for the takeover of the output signals of the sections of the input memories of the luminous digit display device. 21. Time or time program switching device according to one of claims 1 to 2 ₀ , characterized in that a pair of AND gates connected on the output side is used as the clock pulse source, the first input of which is connected to the "1-s" divider stage and its first input of the other to the "1/8-s" divider stage of the clock module (446) and its other inputs to the Q output or the Q output of a time-delayed controlled monostable FLOP element and whose input is above a time delay element is acted upon by the Q output of the monostable elements of the actuating button signal circuits via a common OR element (375, 376). 22. Time or time program switching device according to one of the An Claims 1 to 21, characterized in that at the inputs of the logic unit (LE) the output signal of the electronic clock via an AND gate each and the output signals of the buffer for the sections of the data of the current time, the ON and the OFF. Switching times including the days of the week and the switching channels are connected, the other inputs of the AND elements being controlled by the output signal of the FLIP-FLOP element of the circuit group belonging to the "AUT" button. 23. Time or time program switching device according to one of claims 1 to 22, characterized in that switches with at least two positions in the control circuit of each of the circuit groups for the release or blocking of their actual state are in one of their operating states. 24. Time or time program switching device according to one of claims 1 to 23, characterized in that in the control circuit each of the function selection buttons with the exception of the "AUT" button, a switch with two positions "STEL" and "AUT" for blocking the input with the control buttons when the "AUT" button is pressed. 25. Time or time program switching device according to one of claims 1 to 24, characterized in that in the reset circuit of the monostable FLOP elements in the signal circuit of the actuating button, the output signal of the OR gate (381) in the signal circuit of the "CLE" - Pushbutton (358) and in the reset circuit of the FLIP-FLOP elements (331 to 335) in the signal circuit of function selection keys (321 to 325) the Q output signal of a time-delayed controlled monostable FLOP element (T ₁ ) is connected, the input of an OR gate (381) controlled by the Q output signals of the FLIP-FLOP gates in the signal circuits of function selection pushbuttons on the input side. 26. Time or time program switching device according to one of claims 1 to 15, characterized in that the electronic assemblies at least partially structurally integrated components of a commercially available microprocessor with an arithmetic-logic unit, read / write RAM, input and output. Registers for addressing, data reading and data transfer from or from the group of switches and / / or from function selection and setting buttons combined in a Matriex, as well as from or into the data and address buffer (s), among others . Accumulator (A), B register, etc., constant memories, counters for time intervals, shift registers for logical linking and comparison routines of memory contents and their decision evaluation with the help of groups of AND and OR gates. 27. Time or time program switching device according to one of claims 1 to 26, characterized in that the AND or OR, FLIP-FLOP and MONO-FLOP modules, counters for time intervals and / or memory data words, Shift registers, constant memory locations of the serial logic combination and comparator stages are at least partially replaced by locations of a program memory containing decoder words with decoders for deriving function signals from the operational parts of the stored instruction words. 28. Time or time program switching device according to one of claims 1 to 27, characterized in that the technologically combined as a semiconductor compact module (67) together with microprocessor modules, preferably in C'MOS technology and with LED Liquid crystal display element designed luminous digit display device on a printed circuit board (12o, 215) with electroplated conductor tracks mounted and connected by means of the connecting lugs, and the printed circuit board (215) between an upper housing part (2 ₀ 1) with a window opening (83) for the luminous digit display device and an adjacent control and setting field (3) adjacent to it with the function selection buttons (15 to 17 and 27) and setting buttons (21 to 24), as well as function selection switches on the one hand and a housing Lower part (2o3) through their matching wall edges by screwing to an actual one Self-adjusting housing are held on both sides by spacers and ribs (e.g. 2 ₀ 6), partitions (e.g. 114) and pins (e.g. 118) to secure the distance. 29. Time or time program switching device according to claim 28, characterized in that the circuit board (215) is stiffened by further circuit boards (216, 217) attached to it on both longitudinal sides at right angles, on which the components of the power supply, rectifier , a galvanic battery and / or capacitors (159 to 163) etc., the relay or the like. and connector strips, the latter as galvanically attached contact strips, are arranged. 3 ₀ . Time or time program switching device according to one of claims 28 and 29, characterized in that the lower housing part (213) with preferably internally toothed grooves (228) on two opposite side walls for its clamping holder by claws on the counterpart both in the cutout of a front The mounting plate of an electronic device frame can be plugged in as well as can be plugged into a body-mounting design for protecting the rear parts and connections of the lower part of the housing against improper contact. 31. Time or time program switching device according to one of claims 28 to 3 ₀ , characterized in that the function selection and control buttons as fingers made by means of additives made of rubber-like material (55 to 59 ') with a neck (59) of rectangular cross-section, and guided through matching rectangular openings (1 ₀ 5) with ribs (llo to 112) integrally formed on the edge on the underside of the front plate (lo9), and with a head plate lying opposite the printed circuit board (51) (6 ₀ ) formed as a current connector between the conductor tracks touched when the button is pressed and are integrally and integrally united with a common elastic support surface (61) with molded fitting parts. 32. time or time program switching device according to one of claims 28 to 31, characterized in that the display panel and the adjoining control and setting panel of at least approximately the same adjacent side length to an elongated rectangle in the aspect ratio two to one in the Front plate of the upper housing part is combined and can be covered in a dust and damage-proof manner by a transparent cover hood which can be plugged onto the upper housing part between its side walls.

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