EP0626084A1 - Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means - Google Patents
Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution meansInfo
- Publication number
- EP0626084A1 EP0626084A1 EP94903547A EP94903547A EP0626084A1 EP 0626084 A1 EP0626084 A1 EP 0626084A1 EP 94903547 A EP94903547 A EP 94903547A EP 94903547 A EP94903547 A EP 94903547A EP 0626084 A1 EP0626084 A1 EP 0626084A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- programming
- blocks
- gate array
- logic blocks
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
Definitions
- This invention generally relates to integrated circuit computing devices, and, more specifically, relates to an integrated circuit computing device comprising a dynamically configurable gate array which has a microprocessor coupled to a reconfigurable instruction execution unit.
- This device can implement complex, time-consuming operations by reconfiguring the instruction execution unit to perform a specific function very quickly in hardware rather than implementing complex operations in time- consuming software routines.
- microprocessor Most modern computers are based on a conventional Von Neumann architecture which executes software instructions in sequential fashion. Many modern computers are based on the microprocessor, which follows the traditional, sequential Von Neumann approach. In recent years the use of the microprocessor has become more widespread and varied, from special purpose microprocessors with special features suited to automotive and control applications (commonly known as microcontrollers) to the more highly-integrated general purpose microprocessors such as the Intel 80386 and 80486, which are used in IBM-compatible personal computers, and the Motorola 68020 and 68030, which are used in Apple Mclntosh- compatible personal computers.
- MULTIPLY instruction within a typical microprocessor causes the microprocessor to generate a sequence of ADD and SHIFT instructions to accomplish the desired MULTIPLY function. If this MULTIPLY function could be carried out in hardware, the execution time for the MULTIPLY function could be reduced by orders of , magnitude.
- the microprocessor evolved over many years to become a very complex and powerful general purpose processor, capable of high levels of performance due to the large amount of circuitry and firmware dedicated to complex, high level functions.
- These high power, complex, general purpose microprocessors are known as Complex Instruction Set Computers (CISC) , due to the features that would allow the execution of complex instructions.
- CISC Complex Instruction Set Computers
- RISC Reduced Instruction Set Computer
- the RISC architecture concentrated on implementing each instruction within a simple instruction set in a single clock cycle.
- the underlying philosophy of the RISC architecture is to do fewer functions than the CISC architecture, but to do them very fast.
- the amount of circuitry in a RISC is substantially less than that used in a CISC. So for a typical RISC machine, there is no MULTIPLY instruction.
- the MULTIPLY operation would be accomplished in a RISC machine by a software routing performing a series of ADD and SHIFT instructions.
- a RISC-based computer can outperform a CISC-based computer even though it must implement many of the CISC functions in software routines. This is due to the highly efficient instruction set where each instruction can be executed much faster than even the simplest instructions in a CISC- based computer. This improvement in speed usually more than makes up for the overhead in additional software.
- Certain applications such as digital signal processing, video image generation, and complex mathematical calculations require functions that are not implemented within the complex hardware and firmware of the general purpose CISC.
- Some microprocessors have circuitry dedicated to perform certain of these complex functions in hardware, such as digital signal processors, video processors, or math processors. However, each of these is limited to its specific realm, is not suited to general-purpose use, and cannot be modified to perform a different type of high level function.
- For a general purpose CISC or RISC to perform these types of special, complex functions they must be implemented in long, complex, software routines that take a relatively long time to execute.
- a computer system that uses a CISC or RISC type microprocessor to perform these complex operations will spend a relatively large amount of time executing these complex operations when compared to the time spent performing other simpler functions.
- a well-known rule with regards to problem solving is known as the Amdahl Rule, which states that 10% of the problem generally takes 90% of the time to solve the problem.
- This rule also applies to computers: 10% of the computer's operations generally take 90% of the computer's time. Assuming this is true, it is obvious that an improvement in the execution time of the 10% of the computer's functions that take 90% of the computer's time will directly and drastically improve the performance of the computer.
- FPGAs Field Programmable Gate Arrays
- I/O input/output
- programmable logic blocks programmable routing resources to interconnect the logic blocks to each other and to the I/O blocks.
- I/O input/output
- Many uses for these FPGAs have been found, with most being used to implement a high number of combinatorial logic functions, which results in lower part count, lower power dissipation, higher speed and greater system flexibility than if discrete components were used.
- Some FPGAs have been used to implement sequencers and other various forms of state machines which are essentially combinatorial in nature.
- the routing resources are used to interconnect the logic blocks to each other and to the I/O blocks, and to connect the I/O blocks through the I/O pads to the pins of the FPGA.
- the programming of the FPGA is accomplished by loading configuration data into the Configuration Memory Array of the FPGA. Since the XILINX FPGA is RAM-based, when power is first applied to the FPGA it has not yet been configured. Once the configuration data has been loaded into the Configuration Memory Array, the FPGA is ready for operation.
- XILINX specifically acknowledges this potential use for the FPGA.
- the FPGA is reconfigured only to provide a different combinatorial logic function, and has not been used to implement a general purpose computing device. If a general computing device could be constructed within an FPGA, greater system flexibility would be achieved.
- Two computers have been built with this architecture, the SPLASH 1 which is discussed in Maya Gokhale et al., Building and Using a Highly Parallel Programmable Logic Array (Supercomputing Research Center, Jan. 1991) and the SPLASH 2 which is discussed in Jeffrey M. Arnold et al., SPLASH 2 (Supercomputing Research Center, 1992) .
- the XILINX FPGAs are placed in a systolic array which distributes the computing among the FPGAs to accomplish a high level of parallel processing.
- This systolic array configuration results in greatly increased computing speed due to the shared parallel execution of functions, but requires the use of many XILINX FPGAs and a great deal of software overhead to distribute the processing to accomplish this high level of performance.
- general-purpose CISC and RISC machines are not well-suited to fast execution of complex operations.
- Special- purpose processors execute a limited number of complex operations very quickly, but cannot be configured for operations outside their limited specialty, and are not well-suited as general purpose computing devices.
- an integrated circuit computing device is provided. This computing device is implemented in an FPGA such as the RAM-based XC3020 FPGA by XILINX.
- the number of logic blocks and routing resources available in the XILINX FPGA makes it well suited for implementing a simple microprocessor such as a RISC Processor.
- This RISC Processor is coupled to a unique instruction execution unit that can be reconfigured to implement a variety of very complex operations in hardware.
- One specific example of the degree of performance enhancement available from this type of computing device is a digital audio post-processor which is used to digitally sample and filter an audio signal.
- a digital audio post-processor which is used to digitally sample and filter an audio signal.
- Figure 1 is a block diagram of the computing device of the present invention when used as a component in a high-speed computer system.
- FIG. 2 is a block diagram of the FPGA shown in Figure 1.
- Figure 3 is a block diagram of a computer system using the computing device of Figure 1 to digitally sample and filter up to 8 audio input channels.
- Figure 4 is a block diagram of a computer system that uses two of the computing devices of the present invention in pseudo- parallel fashion which further increases the speed of the system.
- FIG. 1 shows a block diagram of the computing device 10 of the present invention when used in a high-speed computing system 48.
- the computing device 10 is implemented within a Field Programmable Gate Array (FPGA) 12, and has a RISC Processor 14, a Reconfigurable Instruction Execution Unit 16, a Host Interface (I/F) 18, and a Configuration Memory Array 20.
- the Host Interface 18 is coupled to an external Host 40 via System Bus 44.
- the Host 40 controls the configuration of FPGA 12 by loading new configuration data through Host Interface 18 into the Configuration Memory Array 20 of FPGA 12 as required by the specific operation.
- RISC Processor 14 is coupled to Program Memory 42 which contains the code (instructions) for RISC Processor 14.
- the FPGA 12 of Figure 1 is shown in more detail in Figure 2.
- This FPGA is typically a RAM-based FPGA similar to the XILINX XC3000 series of FPGAs.
- the specific configuration of each of the XC3000 series of XILINX FPGAs is given in detail in The Programmable Gate Array Data Book. (XILINX 1992) .
- the FPGA represented in Figure 2 is comprised of I/O Pads 30, I/O Blocks 32, Logic Blocks 34, and Routing Resources (not shown).
- the I/O Pads 30 are contacts on the FPGA 12 that are bonded to metal pins or contacts (not shown) which connect the FPGA 12 to circuitry external to FPGA 12.
- the I/O Blocks 32 are programmable blocks that can be configured to provide input or output signals to the I/O Pads 30 of FPGA 12, and can also be programmed with such features as signal feedback into FPGA 12 or registered inputs and outputs.
- the Logic Blocks 34 contain circuitry that be programmed to perform a myriad of different functions. The specific configuration of the Logic Blocks 34 is not critical, provided the Logic Blocks 34 provide the required minimum level of functionality to implement the desired circuitry.
- the Routing Resources are a large number of conductors that cross at numerous points within FPGA 12 controlled by programmable pass transistors, and, once properly programmed, the pass transistors and Routing Resources provide the majority of the signal paths between the I/O Pads 30, the I/O Blocks 32, and the Logic Blocks 34. These programmable pass transistors are programmed by the Host 40 writing configuration data through Host Interface 18 to Configuration Memory Array 20.
- the FPGA 12 is a general purpose, programmable device.
- the I/O Blocks 32 and the Logic Blocks 34 can each be programmed to perform specific functions, and the Routing Resources can be programmed to interconnect the I/O Blocks 32 with the I/O Pads 30 and the Logic Blocks 34 to achieve the desired overall function of the computing device 10.
- Note that many other circuits may be implemented in FPGA 12 simultaneously with the components shown in Figure 1 to add flexibility and power according to the specific application.
- the result of this flexible architecture is a user- configurable integrated circuit capable of a very high level of performance.
- the FPGA 12 Since the FPGA 12 is RAM-based, it is programmed by writing configuration data into the Configuration Memory Array 20. This configuration data controls pass transistors within the FPGA 12 to appropriately configure the I/O Blocks 32, the Logic Blocks 34, and the Routing Resources so the desired circuitry is implemented within the FPGA 12.
- the XILINX XC3020 FPGA can be programmed in either parallel or serial modes. In either case, the Configuration Memory Array is filled with configuration data from an external source, which programs the FPGA 12 to perform the desired functions.
- the configuration of Figure 1 uses serial mode to serially shift all the bits of the configuration data into Configuration Memory Array 20.
- the computing device 10 of the present invention is not a typical RISC processor. Included within FPGA 12 is a Reconfigurable Instruction Execution Unit 16. A typical RISC processor has a fixed instruction execution unit where all data manipulations are performed. The Reconfigurable Execution Unit 16 of the present invention allows the FPGA 12 to execute extremely complex instructions in a very short time, which greatly boosts the speed and performance of the computer system using the computing device 10.
- the operation of the computing device 10 of the present invention is best understood by referring to Figure 1.
- the FPGA 12 Once the FPGA 12 is powered up, it must be initially configured or programmed by the Host 40.
- the Host 40 thus writes the appropriate configuration data into the Configuration Memory Array 20, which programs the FPGA 12 to the appropriate initial state.
- the RISC processor 14 then begins executing its program from Program Memory 42.
- Program Memory 42 For illustrative purposes with the system shown in Figure 1, it is assumed that the Host 40 is the "master" and the computing device 10 within FPGA 12 is a "slave" to Host 40. In this configuration the Host 40 is a computer capable of general-purpose functions. As the Host 40 executes its program, it may encounter a complex, time-consuming operation.
- Host 40 reconfigures the FPGA 12 for that particular operation by initiating the programming sequence for the FPGA 12 which causes new configuration data to be written into the Configuration Memory Array 20.
- the effect of this new configuration data is to leave the programming of the I/O Blocks 32 unchanged, to leave the programming of the Logic Blocks 34 that comprise the RISC processor 14 unchanged, but to change the programming of the Logic Blocks 34 that comprise the Reconfigurable Instruction Execution Unit 16 such that the desired complex operation can be accomplished by the newly configured hardware on data that already exists within the Reconfigurable Instruction Execution Unit 16.
- the FPGA 12 can signal the Host 40 and transfer the data to Host 40, if required.
- This operation allows the computing device 10 of the present invention to execute many different and complex operations in hardware rather than in long, time-consuming software routines. Since the Reconfigurable Instruction Execution Unit 16 within computing device 10 can be dynamically reconfigured to accomplish each of these complex operations in programmable hardware rather than employing fixed, special-purpose circuitry for each operation, the computing device 10 provides great flexibility and power with a minimum of circuitry.
- the configuration data consists of 14,779 bits of data. Let's assume the clock rate of the XC3020 is set to be 10 MHz, giving a period of 100 n ⁇ . If the XC3020 is configured to serially shift this configuration data into its Configuration Memory Array 20, the time required to complete configuration will nominally be:
- FIG 3 shows one specific implementation of the computing device 10 of Figure 1 when used in conjunction with an IBM- compatible Personal Computer (PC) 52 to implement a Digital Recording Studio 51 which digitally samples, filters and records up to 8 channels of audio input simultaneously.
- the PC 52 includes System Memory 54, Hard Drive 56, and an Application Program 58.
- This Application Program 58 is software which generates a studio environment for recording and filtering the audio inputs, and nominally runs under Microsoft Windows.
- the expansion card 60 contains the circuitry to implement the functions unique to the Digital Recording Studio 51, and is plugged into one of the expansion slots .of the PC 52. In this manner the PC 52 (of Figure 3) is the Host 40 shown in Figure 1, and communicates with and controls expansion card 60 via the System Bus 44.
- the XILINX 3000 series FPGA 12 contains a computing device 10 shown in Figure 1, which is comprised of a Host Interface 18, Control Logic 68, and a Digital Signal Processor (DSP) 70 (as shown in Figure 3).
- the DSP 70 is implemented using the RISC Processor 14 and Reconfigurable Instruction Execution Unit 16 as shown in Figure 1, along with other support circuitry within the FPGA 12 that is not shown in the figures.
- Control Logic 68 is coupled to Memory 72.
- Digital Signal Processor 70 is coupled to Program Memory 42, similar to the configuration shown in Figure 1.
- Control Logic 68 controls the function of the audio input portion 69 of the expansion board 60.
- This board can have up to eight Audio Input Channels 74.
- Each channel 74 has its own Input Amp 76, which has programmable gain 78 set by Control Logic 68.
- the output of Input Amp 76 is connected to the input of a 12th- Order Analog Anti-Aliasing Filter 80 which is also controlled by a Clock 82 from Control Logic 68.
- the output of this Anti-Aliasing Filter 80 is connected to one of the eight data inputs 84 on a Dual 4-to-l Multiplexer (MUX) 86.
- MUX Dual 4-to-l Multiplexer
- the Select Lines 88 of MUX 86 are controlled by Control Logic 68, which selects which audio input channel 74 will be processed.
- the MUX 86 routes the appropriate signal to a Dual 18-bit Analog-to-Digital (A/D) Converter 90, which converts the analog input signal to a digital representation, which is then transferred to DSP 70.
- DSP 70 then performs the appropriate digital signal processing functions through a combination of the RISC Processor 14 within FPGA 12 executing its program and the PC 52 reconfiguring FPGA 12 such that the Reconfigurable Instruction Execution Unit 16 within DSP 70 performs the most time-intensive operations quickly in hardware.
- the Digital audio data Once the digital audio data has been appropriately filtered by DSP 70, it can be written through the Host Interface 18 to the System Bus 44 into system Memory 54, then to the Hard Drive 56. In this manner up to eight channels of real-time audio can be processed and stored by the Digital Recording Studio 51 of Figure 3.
- the Control Logic 68 can be controlled by an external device through a Midi Interface 92, which is an industry-standard interface for small computer control of audio equipment. This allows the Digital Recording Studio 51 to be remotely controlled by an external keyboard or other electronically controlled equipment.
- the Digital Recording Studio 51 also contains an Analog Output Portion 94 for playing back the audio data stored on Hard Drive 56.
- the digital audio data on Hard Drive 56 goes through System Memory 54 to the System Bus 44, through Host Interface 18 to DSP 70, which operates on the data.
- DSP 70 then outputs a processed digital representation of the audio data to an 18-bit Dual Digital to Analog (D/A) Converter 96.
- a MUX 98 routes the analog signals 100 and 102 to Anti-Imaging Filters 104, then to a Left Audio Output 106 and a Right Audio Output 108. These Audio Outputs 106 and 108 can then be routed through an external amplifier to speakers for the playback of the recorded audio data.
- the Digital Recording Studio 51 with its eight channels of audio input and its two channels of audio output, can filter and mix the input audio signals as the user directs via the Application Program 58.
- This Application Program 58 can be very complex and provide numerous sophisticated functions.
- This Digital Recording Studio 51 can be implemented with a PC 52 and Expansion Card 60, which are both constructed of relatively low-cost components. Through the high level of specialized functionality gained through using the computing device 10 within FPGA 12 in the Digital Recording Studio 51, the functions of a very complex and sophisticated digital audio system can be implemented very simply and inexpensively.
- An alternate embodiment of the present invention includes the use of two FPGAs 12A and 12B in a pseudo-parallel arrangement, as shown in the computing device 50 of Figure 4.
- the two FPGAs 12A and 12B are coupled to the same Host 40 via System Bus 44 as shown, and the internal configuration of the RISC Processor 14 in each is nominally identical.
- These FPGAs 12A and 12B operate in pseudo- parallel manner, which means that while one FPGA 12A is in the process of being reconfigured by the Host 40, the second FPGA 12B can be executing a complex operation. In this manner the Host 40 has access to multiple slave processors 12A and 12B so program execution in Host 40 is not limited by having only one FPGA. For example, as FPGA 12A executes an operation at the command of Host 40, the second FPGA 12B can then be configured by the Host 40 for the next complex operation.
- the FPGAs 12A and 12B are used by the Host 40 in sequential manner, with one active while the other is being reconfigured. This allows the execution of the computing device 50 to continue during reconfiguration of the FPGAs, which further increases the speed of the computing device 50. Needless to say, more than two FPGAs could be used in the computing device 50 of Figure 3.
- the RISC Processor 14 could be the "master" with the Host 40 being a "slave” which simply reconfigures FPGA 12 on command.
- the computing device 10 of the present invention while described as being implemented within a XILINX RAM-based FPGA 12, could also be implemented as a custom semiconductor device with specialized control circuitry for particular applications.
- the FPGA need not necessarily be RAM-based if developments in other technologies such as EEPROMS make the use of other types of reconfigurable circuitry desirable.
- the Host 40 could have access to the Program Memory 42, and could therefore write into Program Memory 42 the actual program the RISC Processor 14 within FPGA 12 executes. While the disclosure herein describes only the Reconfigurable Instruction Execution Unit as changing during reconfiguration of the FPGA 12, it is an obvious extension of this invention that the attributes of the RISC Processor 14, the Bus Interface 18, and other circuitry within the FPGA 12 could all be modified as needed during reconfiguration of the FPGA 12.
Abstract
Un dispositif de calcul à circuit intégré (10) se compose d'un curcuit prédiffusés programmable par l'utilisateur et configurables dynamiquement (FPGA) (12). Ces circuits prédiffusés (12) sont configurés pour mettre en place un processeur RISC (à feu d'instructions réduit) (14) ainsi qu'un organe d'exécution d'instruction reconfigurable (16). Le FPGA (12) pouvant être reconfiguré dynamiquement, l'organe d'exécution d'instruction reconfigurable (16) peut être modifié dynamiquement pour mettre en place des opérations complexes en machine plutôt que dans des programmes logiciels prenant du temps. Cette caractéristique permet au dispositif de calcul (10) de fonctionner à des vitesses supérieures aux pendants classiques à jeu d'instructions réduit (RICS) ou à jeu d'instruction complexe (CISC). De plus, la programmabilité du dispositif de calcul (10) rend ce dernier très flexible et idéal pour traiter un grand nombre d'applications complexes.An integrated circuit computing device (10) consists of a preprogrammed curcuit programmable by the user and dynamically configurable (FPGA) (12). These pre-broadcast circuits (12) are configured to set up a RISC processor (at reduced instruction fire) (14) as well as a reconfigurable instruction execution member (16). Since the FPGA (12) can be reconfigured dynamically, the reconfigurable instruction execution member (16) can be modified dynamically to implement complex operations in the machine rather than in time-consuming software programs. This feature allows the computing device (10) to operate at speeds higher than conventional pendants with a reduced instruction set (RICS) or a complex instruction set (CISC). In addition, the programmability of the computing device (10) makes it very flexible and ideal for processing a large number of complex applications.
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US989236 | 1992-12-11 | ||
US07/989,236 US5361373A (en) | 1992-12-11 | 1992-12-11 | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
PCT/US1993/011964 WO1994014123A1 (en) | 1992-12-11 | 1993-12-09 | Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means |
Publications (2)
Publication Number | Publication Date |
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EP0626084A1 true EP0626084A1 (en) | 1994-11-30 |
EP0626084A4 EP0626084A4 (en) | 1995-02-22 |
Family
ID=25534898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP94903547A Withdrawn EP0626084A4 (en) | 1992-12-11 | 1993-12-09 | Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means. |
Country Status (4)
Country | Link |
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US (1) | US5361373A (en) |
EP (1) | EP0626084A4 (en) |
JP (1) | JPH07503804A (en) |
WO (1) | WO1994014123A1 (en) |
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- 1993-12-09 EP EP94903547A patent/EP0626084A4/en not_active Withdrawn
- 1993-12-09 WO PCT/US1993/011964 patent/WO1994014123A1/en not_active Application Discontinuation
- 1993-12-09 JP JP6514395A patent/JPH07503804A/en active Pending
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See also references of WO9414123A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP0626084A4 (en) | 1995-02-22 |
WO1994014123A1 (en) | 1994-06-23 |
JPH07503804A (en) | 1995-04-20 |
US5361373A (en) | 1994-11-01 |
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