EP0640979A3 - Checkerboard image buffer system. - Google Patents

Checkerboard image buffer system. Download PDF

Info

Publication number: EP0640979A3
Authority: EP; European Patent Office
Prior art keywords: buffer system; image buffer; checkerboard image; checkerboard; image
Prior art date: 1993-08-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

EP94305916A

Other languages

German (de)

French (fr)

Other versions

EP0640979B1 (en

EP0640979A2 (en

Inventor

Jean-Swey Kao

Jack C Liu

Ronald E Rider

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Xerox Corp

Original Assignee

Xerox Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1993-08-30

Filing date

1994-08-10

Publication date

1995-08-09

1994-08-10 Application filed by Xerox Corp filed Critical Xerox Corp

1994-08-10 Priority to EP98114329A priority Critical patent/EP0887802B1/en

1995-03-01 Publication of EP0640979A2 publication Critical patent/EP0640979A2/en

1995-08-09 Publication of EP0640979A3 publication Critical patent/EP0640979A3/en

1999-12-15 Application granted granted Critical

1999-12-15 Publication of EP0640979B1 publication Critical patent/EP0640979B1/en

2014-08-10 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Image Input (AREA)
Storing Facsimile Image Data (AREA)
Controls And Circuits For Display Device (AREA)
Memory System (AREA)
Dram (AREA)

EP94305916A 1993-08-30 1994-08-10 Checkerboard image buffer system Expired - Lifetime EP0640979B1 (en)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
EP98114329A EP0887802B1 (en)	1993-08-30	1994-08-10	Method for operating a memory

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US08/114,552 US5561777A (en)	1993-08-30	1993-08-30	Process for sequentially reading a page from an image memory in either of two directions
US114552		1993-08-30

Related Child Applications (1)

Application Number	Title	Priority Date	Filing Date
EP98114329A Division EP0887802B1 (en)	1993-08-30	1994-08-10	Method for operating a memory

Publications (3)

Publication Number	Publication Date
EP0640979A2 EP0640979A2 (en)	1995-03-01
EP0640979A3 true EP0640979A3 (en)	1995-08-09
EP0640979B1 EP0640979B1 (en)	1999-12-15

Family

ID=22355959

Family Applications (2)

Application Number	Title	Priority Date	Filing Date
EP94305916A Expired - Lifetime EP0640979B1 (en)	1993-08-30	1994-08-10	Checkerboard image buffer system
EP98114329A Expired - Lifetime EP0887802B1 (en)	1993-08-30	1994-08-10	Method for operating a memory

Family Applications After (1)

Application Number	Title	Priority Date	Filing Date
EP98114329A Expired - Lifetime EP0887802B1 (en)	1993-08-30	1994-08-10	Method for operating a memory

Country Status (4)

Country	Link
US (1)	US5561777A (en)
EP (2)	EP0640979B1 (en)
JP (1)	JPH07168754A (en)
DE (2)	DE69422101T2 (en)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CA2145365C (en)	1994-03-24	1999-04-27	Anthony M. Jones	Method for accessing banks of dram
JP3138173B2 (en) *	1995-04-10	2001-02-26	シャープ株式会社	Frame memory device for graphics
JPH10283770A (en)	1997-04-07	1998-10-23	Oki Electric Ind Co Ltd	Semiconductor memory device and its reading and writing method
US6247084B1 (en)	1997-10-08	2001-06-12	Lsi Logic Corporation	Integrated circuit with unified memory system and dual bus architecture
US6016522A (en) *	1997-11-13	2000-01-18	Creative Labs, Inc.	System for switching between buffers when receiving bursty audio by computing loop jump indicator plus loop start address for read operations in selected buffer
KR100385370B1 (en) *	1998-07-21	2003-05-27	시게이트 테크놀로지 엘엘씨	Improved memory system apparatus and method
US6394850B1 (en)	2000-03-20	2002-05-28	David Oliphant	Contact pin design for a modular jack
US6828977B2 (en) *	2001-02-15	2004-12-07	Sony Corporation	Dynamic buffer pages
US6795079B2 (en) *	2001-02-15	2004-09-21	Sony Corporation	Two-dimensional buffer pages
US7205993B2 (en) *	2001-02-15	2007-04-17	Sony Corporation	Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation
US7038691B2 (en) *	2001-02-15	2006-05-02	Sony Corporation	Two-dimensional buffer pages using memory bank alternation
US6831649B2 (en) *	2001-02-15	2004-12-14	Sony Corporation	Two-dimensional buffer pages using state addressing
US6803917B2 (en) *	2001-02-15	2004-10-12	Sony Corporation	Checkerboard buffer using memory bank alternation
US6831651B2 (en) *	2001-02-15	2004-12-14	Sony Corporation	Checkerboard buffer
US7088369B2 (en) *	2001-02-15	2006-08-08	Sony Corporation	Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing
US6850241B2 (en) *	2001-02-15	2005-02-01	Sony Corporation	Swapped pixel pages
US6765580B2 (en) *	2001-02-15	2004-07-20	Sony Corporation	Pixel pages optimized for GLV
US7379069B2 (en) *	2001-02-15	2008-05-27	Sony Corporation	Checkerboard buffer using two-dimensional buffer pages
US6992674B2 (en) *	2001-02-15	2006-01-31	Sony Corporation	Checkerboard buffer using two-dimensional buffer pages and using state addressing
US6801204B2 (en) *	2001-02-15	2004-10-05	Sony Corporation, A Japanese Corporation	Checkerboard buffer using memory blocks
US6765579B2 (en) *	2001-02-15	2004-07-20	Sony Corporation	Pixel pages using combined addressing
US6768490B2 (en) *	2001-02-15	2004-07-27	Sony Corporation	Checkerboard buffer using more than two memory devices
US6791557B2 (en) *	2001-02-15	2004-09-14	Sony Corporation	Two-dimensional buffer pages using bit-field addressing
US6831650B2 (en) *	2001-02-15	2004-12-14	Sony Corporation	Checkerboard buffer using sequential memory locations
US20030058368A1 (en) *	2001-09-24	2003-03-27	Mark Champion	Image warping using pixel pages
US6965980B2 (en) *	2002-02-14	2005-11-15	Sony Corporation	Multi-sequence burst accessing for SDRAM
US6992707B2 (en) *	2002-03-06	2006-01-31	Hewlett-Packard Development Company, L.P.	Delayed encoding based joint video and still image pipeline with still burst mode
US6919902B2 (en) *	2002-06-03	2005-07-19	Seiko Epson Corporation	Method and apparatus for fetching pixel data from memory
US7034887B2 (en) *	2002-07-15	2006-04-25	Seiko Epson Corporation	Method and apparatus for flicker filtering interlaced display data
US7583732B2 (en) *	2002-12-06	2009-09-01	Broadcom Corporation	Managing bursts of data
KR100612414B1 (en) *	2003-04-28	2006-08-16	삼성전자주식회사	Image data processing system and method for reading and writing image data
US7111093B2 (en) *	2003-06-23	2006-09-19	Intel Corporation	Ping-pong buffer system having a buffer to store a subset of data from a data source
FR2951310B1 (en) *	2009-10-13	2011-11-18	St Microelectronics Rousset	SERIAL PROTOCOL MEMORY DEVICE AND CORRESPONDING ADDRESSING METHOD
US8564603B2 (en) *	2010-10-24	2013-10-22	Himax Technologies Limited	Apparatus for controlling memory device and related method
CN106201363B (en) *	2016-07-26	2023-01-31	四川大学	Memory and storage method for random real-time access of video stream pixel-level data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE3913599C1 (en) *	1989-04-25	1990-01-18	Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung Ev, 8000 Muenchen, De	Intermediate image store e.g. for TV transmission - assigns separate control to each video channel for connection to all memory blocks

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4247920A (en) *	1979-04-24	1981-01-27	Tektronix, Inc.	Memory access system
JPS56140390A (en) *	1980-04-04	1981-11-02	Nippon Electric Co	Picture memory
DE3015125A1 (en) *	1980-04-19	1981-10-22	Ibm Deutschland Gmbh, 7000 Stuttgart	DEVICE FOR STORING AND DISPLAYING GRAPHIC INFORMATION
US4740927A (en) *	1985-02-13	1988-04-26	International Business Machines Corporation	Bit addressable multidimensional array
US4818932A (en) *	1986-09-25	1989-04-04	Tektronix, Inc.	Concurrent memory access system
US4893257A (en) *	1986-11-10	1990-01-09	International Business Machines Corporation	Multidirectional scan and print capability
KR900000114B1 (en) *	1986-12-29	1990-01-20	박종원	Memory system of image processing
JPH01291387A (en) *	1988-05-19	1989-11-22	Hitachi Ltd	Image processor
US5361339A (en) *	1992-05-04	1994-11-01	Xerox Corporation	Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines

1993
- 1993-08-30 US US08/114,552 patent/US5561777A/en not_active Expired - Fee Related
1994
- 1994-08-10 DE DE69422101T patent/DE69422101T2/en not_active Expired - Fee Related
- 1994-08-10 EP EP94305916A patent/EP0640979B1/en not_active Expired - Lifetime
- 1994-08-10 EP EP98114329A patent/EP0887802B1/en not_active Expired - Lifetime
- 1994-08-10 DE DE69429936T patent/DE69429936T2/en not_active Expired - Fee Related
- 1994-08-26 JP JP6201787A patent/JPH07168754A/en not_active Withdrawn

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE3913599C1 (en) *	1989-04-25	1990-01-18	Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung Ev, 8000 Muenchen, De	Intermediate image store e.g. for TV transmission - assigns separate control to each video channel for connection to all memory blocks

Also Published As

Publication number	Publication date
EP0887802B1 (en)	2002-02-20
EP0640979B1 (en)	1999-12-15
DE69429936D1 (en)	2002-03-28
DE69429936T2 (en)	2002-06-20
DE69422101D1 (en)	2000-01-20
JPH07168754A (en)	1995-07-04
US5561777A (en)	1996-10-01
EP0887802A2 (en)	1998-12-30
EP0887802A3 (en)	1999-02-10
DE69422101T2 (en)	2000-04-27
EP0640979A2 (en)	1995-03-01

Legal Events

Date	Code	Title	Description
1995-01-13	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
1995-03-01	AK	Designated contracting states	Kind code of ref document: A2 Designated state(s): DE FR GB
1995-06-16	PUAL	Search report despatched	Free format text: ORIGINAL CODE: 0009013
1995-08-09	AK	Designated contracting states	Kind code of ref document: A3 Designated state(s): DE FR GB
1996-04-10	17P	Request for examination filed	Effective date: 19960209
1998-06-10	17Q	First examination report despatched	Effective date: 19980427
1999-02-02	GRAG	Despatch of communication of intention to grant	Free format text: ORIGINAL CODE: EPIDOS AGRA
1999-06-11	GRAG	Despatch of communication of intention to grant	Free format text: ORIGINAL CODE: EPIDOS AGRA
1999-06-11	GRAH	Despatch of communication of intention to grant a patent	Free format text: ORIGINAL CODE: EPIDOS IGRA
1999-10-06	GRAH	Despatch of communication of intention to grant a patent	Free format text: ORIGINAL CODE: EPIDOS IGRA
1999-10-29	GRAA	(expected) grant	Free format text: ORIGINAL CODE: 0009210
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2000-01-20	REF	Corresponds to:	Ref document number: 69422101 Country of ref document: DE Date of ref document: 20000120
2000-04-07	ET	Fr: translation filed
2000-10-13	PLBE	No opposition filed within time limit	Free format text: ORIGINAL CODE: 0009261
2000-10-13	STAA	Information on the status of an ep patent application or granted ep patent	Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT
2000-11-29	26N	No opposition filed
2002-01-01	REG	Reference to a national code	Ref country code: GB Ref legal event code: IF02
2002-08-07	PGFP	Annual fee paid to national office [announced via postgrant information from national office to epo]	Ref country code: GB Payment date: 20020807 Year of fee payment: 9
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Publication	Publication Date	Title
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