EP0865162A3 - Optimum noise isolated I/O with minimized footprint - Google Patents

Optimum noise isolated I/O with minimized footprint Download PDF

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Publication number
EP0865162A3
EP0865162A3 EP98301714A EP98301714A EP0865162A3 EP 0865162 A3 EP0865162 A3 EP 0865162A3 EP 98301714 A EP98301714 A EP 98301714A EP 98301714 A EP98301714 A EP 98301714A EP 0865162 A3 EP0865162 A3 EP 0865162A3
Authority
EP
European Patent Office
Prior art keywords
lhc
tsc
switching
change
operational
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98301714A
Other languages
German (de)
French (fr)
Other versions
EP0865162A2 (en
Inventor
Derwin W. Mattos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Semiconductors Inc
Original Assignee
VLSI Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VLSI Technology Inc filed Critical VLSI Technology Inc
Publication of EP0865162A2 publication Critical patent/EP0865162A2/en
Publication of EP0865162A3 publication Critical patent/EP0865162A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements

Abstract

An I/O buffer with minimized footprint; which is less susceptible to voltage spikes caused by switching noise, and which is adapted for used in a separate power bus arrangement. The buffer minimizes voltage spikes caused by switching noise by replacing the single large current surge that occurs during switching with smaller current surges at different times. This is accomplish by having two different drivers for the transitional and holding phases: a Transient Switching Circuit (TSC) and a Logic Holding Circuit (LHC). Generally, the TSC is operational to cause a change in the output signal when there is a change in the input signal. Conversely, the LHC is operational subsequent to the logic transition occurrence at the input signal to bring the output signal to the rail voltage.
EP98301714A 1997-03-11 1998-03-09 Optimum noise isolated I/O with minimized footprint Withdrawn EP0865162A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/814,875 US5914618A (en) 1997-03-11 1997-03-11 Optimum noise isolated I/O with minimized footprint
US814875 1997-03-11

Publications (2)

Publication Number Publication Date
EP0865162A2 EP0865162A2 (en) 1998-09-16
EP0865162A3 true EP0865162A3 (en) 1998-10-07

Family

ID=25216230

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98301714A Withdrawn EP0865162A3 (en) 1997-03-11 1998-03-09 Optimum noise isolated I/O with minimized footprint

Country Status (3)

Country Link
US (1) US5914618A (en)
EP (1) EP0865162A3 (en)
JP (1) JPH1127120A (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3070510B2 (en) * 1997-03-21 2000-07-31 日本電気株式会社 Input circuit and output circuit of semiconductor device and semiconductor device
IT1296611B1 (en) * 1997-12-04 1999-07-14 Sgs Thomson Microelectronics INPUT / OUTPUT BUFFER CIRCUIT, IN PARTICULAR MADE IN CMOS TECHNOLOGY, WITH VOLTAGE VARIATION CONTROL
US6163174A (en) * 1998-05-26 2000-12-19 The University Of Rochester Digital buffer circuits
US6121789A (en) 1998-09-04 2000-09-19 Winbond Electronics Corporation Output buffer with control circuitry
US6051995A (en) * 1998-09-11 2000-04-18 Sharp Electronics Corporation Constant impedance, low noise CMOS buffer
US6512401B2 (en) * 1999-09-10 2003-01-28 Intel Corporation Output buffer for high and low voltage bus
DE19944519B4 (en) * 1999-09-16 2010-02-11 Infineon Technologies Ag Circuit arrangement for driving a load
US6329835B1 (en) 2000-02-23 2001-12-11 Pericom Semiconductor Corp. Quiet output buffers with neighbor sensing of wide bus and control signals
GB0024226D0 (en) * 2000-10-04 2000-11-15 Lsi Logic Corp Improvements in or relating to the reduction of simultaneous switching noise in integrated circuits
US6426652B1 (en) * 2001-05-14 2002-07-30 Sun Microsystems, Inc. Dual-edge triggered dynamic logic
KR100429871B1 (en) * 2001-06-07 2004-05-04 삼성전자주식회사 Semiconductor device having a plurality of output signals
US6586971B1 (en) 2001-12-18 2003-07-01 Hewlett-Packard Development Company, L.P. Adapting VLSI clocking to short term voltage transients
JP3667690B2 (en) 2001-12-19 2005-07-06 エルピーダメモリ株式会社 Output buffer circuit and semiconductor integrated circuit device
TW522646B (en) * 2002-03-11 2003-03-01 Via Tech Inc Output buffer capable of reducing power/ground bounce noise and method for reducing power/ground bounce noise
DE10355509A1 (en) * 2003-11-27 2005-07-07 Infineon Technologies Ag Circuit and method for delayed switching on of an electrical load
KR100825292B1 (en) 2003-12-20 2008-04-28 엘지전자 주식회사 Apparatus for correction of ground bounce
JP5290015B2 (en) 2009-03-25 2013-09-18 ルネサスエレクトロニクス株式会社 Buffer circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994026030A1 (en) * 1993-04-23 1994-11-10 Vlsi Technology, Inc. Noise isolated i/o buffer
US5493232A (en) * 1992-03-11 1996-02-20 Vlsi Technology, Inc. Disturbance immune output buffer with switch and hold stages

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121003A (en) * 1990-10-10 1992-06-09 Hal Computer Systems, Inc. Zero overhead self-timed iterative logic
US5717343A (en) * 1996-07-23 1998-02-10 Pericom Semiconductor Corp. High-drive CMOS output buffer with noise supression using pulsed drivers and neighbor-sensing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493232A (en) * 1992-03-11 1996-02-20 Vlsi Technology, Inc. Disturbance immune output buffer with switch and hold stages
WO1994026030A1 (en) * 1993-04-23 1994-11-10 Vlsi Technology, Inc. Noise isolated i/o buffer

Also Published As

Publication number Publication date
JPH1127120A (en) 1999-01-29
EP0865162A2 (en) 1998-09-16
US5914618A (en) 1999-06-22

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