EP1145437B1 - Digitaler pll-frequenzsynthesizer - Google Patents
Digitaler pll-frequenzsynthesizer Download PDFInfo
- Publication number
- EP1145437B1 EP1145437B1 EP99936339A EP99936339A EP1145437B1 EP 1145437 B1 EP1145437 B1 EP 1145437B1 EP 99936339 A EP99936339 A EP 99936339A EP 99936339 A EP99936339 A EP 99936339A EP 1145437 B1 EP1145437 B1 EP 1145437B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- frequency
- phase
- pll
- voltage
- phase delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Definitions
- the invention relates to a digital PLL (Phase Locked Loop) frequency synthesizer according to the preamble of the claim 1.
- a synthesizer according to the preamble of the claim is e.g. known from GB 2 107 142.
- a reference frequency f Ref which is formed by dividing a stable quartz frequency f Q generated with the aid of a quartz-stable oscillator 1 by the division factor 'R' using a reference frequency divider 2, is compared in a phase-frequency detector 3 with a second frequency f 2 , which is derived by dividing a frequency f VCO generated in a voltage controlled oscillator (VCO; Voltage Controlled Oscillator) 4 by the division factor N.
- VCO Voltage Controlled Oscillator
- the divider ratio 'N' which can be set by the N frequency divider 5, is an integer, which means that the voltage-controlled oscillator 4 can only oscillate on an integer multiple of the reference frequency f Ref when the phase locked loop PLL is engaged. This fact has several disadvantages.
- a low reference frequency f Ref In the case of a desired small distance between the frequencies f VCO that can be generated in the voltage-controlled oscillator 4, a low reference frequency f Ref must be used. Since the phase locked loop PLL represents a sampled system with the sampling rate f Ref , the bandwidth of the phase locked loop PLL cannot be selected higher than f Ref / 2 according to the sampling theorem (Nyquist theorem) in order to obtain a stable system. In practice, the bandwidth is usually around 10% of the reference frequency f Ref .
- a low PLL loop bandwidth means a slow settling behavior when switching over the N frequency divider 5 in order to set a different frequency f VCO of the voltage-controlled oscillator 4, ie a different frequency channel.
- a reference frequency f Ref which is greater than the required channel grid, can be used when the divider factor 'N' can no longer be set as an integer. Since the N-frequency divider 5 itself can only divide by integer factors, the fractional divider ratio must be set on average over M cycles, ie for the duration of MK cycles by the divider factor 'N' and then for the duration of K cycles the whole. Number '1' increased divisor factor 'N + 1' can be divided.
- f VCO f Ref * (N + K / M).
- the frequency f VCO of the voltage-controlled oscillator 4 is stable and set in accordance with the desired fractional divider ratio, it can be shown that during the cycles in which the division factor 'N' divides, the frequency f VCO / N is too high and therefore the phase difference between the reference frequency f Ref and the frequency f VCO / N for each pass by the factor T VCO_soll * K / M is enlarged.
- the PLL phase lock loop try the voltage controlled oscillator (VCO) constantly adjust, and thus the phase stability influence negatively.
- VCO voltage controlled oscillator
- phase jitter Approaches There are several ways to reduce phase jitter Approaches have become known.
- a well-known method (Company "Marconi”) consists in the use of several cascaded phase accumulators based on the sigma-delta principle the frequency components of the phase jitter in ranges shift, which is strongly attenuated by the loop low-pass filter become. Compensation is then no longer necessary.
- phase accumulators are required.
- phase jitter Another known method for reducing phase jitter is the active compensation of the regulation through interventions on the phase-frequency detector or on the loop low-pass filter. For example, in addition to the actual charge pump current a compensation current into the loop low pass filter be fed to the effect of the former To balance current. It must go from cycle to cycle either the size or the duration of the feed changed a quantity of charge dependent on the phase error to provide for compensation.
- the individual gradations of the different charge quantities depend on the desired frequency f VCO of the voltage-controlled oscillator and can be set, for example, as a function of a reference current depending on the VCO frequency / period.
- PLLs phase locked loops
- the current compensation principle is used.
- the disadvantage of this method is the required setting of the reference current and the intervention in the loop low-pass filter by means of an extended charge pump.
- FIG. 2 is a block diagram of a corresponding circuit digital PLL (phase Lokked Loop) frequency synthesizers. It is also in this circuit the known elements of an ordinary and already in connection with the FIG. 1 described PLL frequency synthesizer circuit to see, namely a quartz stable Oscillator 1, a reference frequency divider 2, a phase-frequency detector 3, a charge pump 6, a Loop low pass filter 7 and a voltage controlled oscillator (VCO) 4.
- VCO voltage controlled oscillator
- the frequency synthesizer shown becomes a reference frequency f Ref , which is formed by dividing the quartz frequency f Q supplied by the quartz-stabilized oscillator 1 in the reference frequency divider 2, with a second frequency f 2, derived by dividing the frequency f VCO of the voltage-controlled oscillator 4, in the phase-frequency Detector 3 compared, the output signal after conduction via the charge pump (Charge Pump) 6 and the loop low-pass filter 7 in the PLL loop serves as a control voltage for the voltage-controlled oscillator 4.
- f Ref which is formed by dividing the quartz frequency f Q supplied by the quartz-stabilized oscillator 1 in the reference frequency divider 2, with a second frequency f 2, derived by dividing the frequency f VCO of the voltage-controlled oscillator 4, in the phase-frequency Detector 3 compared
- the output signal after conduction via the charge pump (Charge Pump) 6 and the loop low-pass filter 7 in the PLL loop serves as a control voltage for the voltage-controlled oscillator 4.
- phase delay device 10 is also switched on, which has two control inputs 11 (DelAdjust) or 12 (DelSel), the control input 12 being implemented by a plurality of lines and, for example, + being a bus with ld (M) lines.
- a basic delay is set at the control input 11, and the number of these basic delays at which the output 13 of the phase delay device 10 follows its input 14 is set at the control input 12.
- the phase accumulator 17 is increased with each output pulse of the phase delay device 10 by the adjustable fraction K of the reference frequency f Ref , but modulo-M, for which purpose an adder modulo-M 19 is provided.
- the N / (N + 1) frequency divider 9 is switched to the division factor (N + 1) for the next period via an overflow output 20 of the phase accumulator 17.
- the output 21 of the phase accumulator 17 directly provides the control word DelSel for the control input 12 of the PLL phase delay device 10.
- control voltage DelAdjust with which this time T delmin is set via the control input 11 on each delay element 16 of the phase delay chain 15 in the phase delay device 10, with the aid of a further phase delay device 22 and a further phase Frequency detector 23 is derived directly from the frequency f VCO of the voltage-controlled oscillator 4.
- FIG. 4 shows the further phase delay device 22 constructed in exactly the same way as the phase delay device 10, i.e. it is in accordance with the decoupling lines in the delay elements 16 of the phase delay device 10 according to FIG. 3 for all delay elements 24 loaded by dummy decoupling elements 25 to the same Delay conditions as in the one with the M: 1 multiplexer 18 equipped PLL phase delay device 10.
- the further phase delay device 22 not M-1 delay elements as in the Phase delay device 10, but M delay elements 24 connected in series, which is of great importance is.
- the frequency f VCO of the voltage-controlled oscillator 4 is fed into the further phase delay device 22 at an input 26 via a buffer amplifier 27, and the phase of the signal at the output 28 of the further phase delay device 22 is in turn directly connected with the aid of the further phase-frequency detector 23 the frequency f VCO of the voltage-controlled oscillator 4, which is conducted via the same buffer amplifier 26.
- the comparison result derived from the output 28 of the further phase delay device 22 is low-pass filtered in a second loop low-pass filter 29 and then forms the control voltage for the further phase delay device 22, which is fed there to a control input 30.
- auxiliary phase locked loop auxiliary PLL
- the Auxiliary PLL have a very high loop bandwidth.
- each delay element 24 of the further phase delay device 22 delays by exactly the Mth part of T VCO_soll .
- phase delay device 10 Main PLL contained phase delay chain 15. Because the Delay elements 16 and 24 in both phase delay devices 10 or 22 regarding their temporal behavior are constructed the same, the control voltage for the further phase delay device 22 also as a control voltage DelAdjust for supply to the control input 11 of the phase delay device 10 can be used.
- a frequency synthesizer designed in accordance with the invention can be integrated in a particularly advantageous manner Carry out circuit technology.
Description
Claims (8)
- Digitaler PLL(Phase Locked Loop)-Frequenzsynthesizer, bei dem eine durch Teilung einer stabilen Quarzoszillatorfrequenz (fQ) gebildete Referenzfrequenz (fRef) mit einer zweiten, durch Teilen der Frequenz eines spannungsgesteuerten Oszillators (VCO) abgeleiteten Frequenz (fVCO) in einem Phasen-Frequenz-Detektor (3) verglichen wird, dessen Ausgangssignal nach Leitung über ein Schleifen-Tiefpaßfilter (7) in einer Schleife der PLL als Steuerspannung für den spannungsgesteuerten Oszillators dient, wobei zur Teilung der Frequenz des spannungsgesteuerten Oszillators in der Schleife der PLL ein zwischen zwei benachbarten ganzzahligen Teilerfaktoren N und N+1 umschaltbarer, für die Dauer von M-K Zyklen durch N teilender und dann für die Dauer von K Zyklen durch N+1 teilender N/(N+1)-Frequenzteiler (9) vorgesehen ist und zur Herbeiführung einer automatischen Umschaltung des N/(N+1)-Frequenzteilers ein Phasenakkumulator (17) vorgesehen sind, zu dessen Inhalt mit jedem Impuls der geteilten VCO-Frequenz der Wert K mit einer Modulo-M-Addition addiert wird und der nach jedem Überlauf im nächsten Zyklus eine Änderung des Teilerfaktors von N auf N+1 veranlaßt,
dadurch gekennzeichnet, daß
zwischen dem N/(N+1)-Frequenzteiler (9) und dem von diesem Frequenzteiler angesteuerten Eingang des Phasen-Frequenz-Detektors (3) und dem Eingang des Phasenakkumulators (17) eine Phasenverzögerungseinrichtung (10) eingefügt ist, die in einer Phasenverzögerungskette (15) M-1 Verzögerungselemente (16) enthält und die zwei Steuereingänge (11, 12) aufweist, von denen der eine (11) zur Einstellung der jeweils übereinstimmenden Größe der Grundverzögerungen der Verzögerungselemente der Phasenverzögerungskette und der andere (12) zur Einstellung der Anzahl der in dieser Phasenverzögerungskette wirksamen Grundverzögerungen vorgesehen ist, daß der Inhalt des Phasenakkumulators (17) mit jedem Ausgangsimpuls der Phasenverzögerungseinrichtung (10) um den einstellbaren Bruchteil K der Referenzfrequenz Modulo-M erhöht wird und bei einem Überlauf der N/(N+1)-Frequenzteiler für die nächste Periode auf N+1 geschaltet wird, daß der Ausgang (21) des Phasenakkumulators (17) mit dem zur Einstellung der Anzahl der wirksamen Grundverzögerungen vorgesehenen Steuereingang (12) der Phasenverzögerungseinrichtung (10) verbunden ist, und daß eine weitere Phasenverzögerungseinrichtung (22), die M hintereinandergeschaltete Verzögerungselemente (24) aufweist, zwischen dem Ausgang des spannungsgesteuerten Oszillators (4) und dem einen Eingang eines weiteren Phasen-Frequenz-Detektors (23) eingefügt ist, daß an einem zweiten Eingang des weiteren Phasen-Frequenz-Detektors (23) der Ausgang des spannungsgesteuerten Oszillators (4) ohne Zwischenschaltung von Verzögerungselementen angeschlossen ist und daß mit einem Ausgang des weiteren Phasen-Frequenz-Detektors (23) über ein weiteres Schleifen-Tiefpaßfilter (29) unter Bildung einer Hilfs-PLL-Schleife die zur Einstellung der jeweils übereinstimmenden Größe der Grundverzögerungen der Verzögerungselemente vorgesehenen Steuereingänge (11, 30) der beiden Phasenverzögerungseinrichtungen (10, 22) verbunden sind. - Frequenzsynthesizer nach Anspruch 1, dadurch gekennzeichnet, daß der zur Einstellung der Anzahl der in der Phasenverzögerungseinrichtung (10) wirksamen Grundverzögerungen vorgesehene Steuereingang (12) durch den Steuereingang eines M:1-Multiplexers (18) gebildet ist, mittels welchem sich in Abhängigkeit vom an seinem Steuereingang liegenden Steuersignal auswählen läßt, hinter welchem der in Reihe geschalteten Verzögerungselemente (16) das einerseits dem einen Eingang des Phasen-Frequenz-Detektors (3) und andererseits dem Phasenakkumulator (17) zuzuführende Signal ausgekoppelt wird.
- Frequenzsynthesizer nach Anspruch 1, dadurch gekennzeichnet, daß die weitere Phasenverzögerungseinrichtung (22) zur Nachbildung von Verzögerungsbedingungen, die mit denjenigen der Phasenverzögerungseinrichtung (10) übereinstimmen, außer den Verzögerungselementen (24) selbst diesen letzteren zugeordnete Dummy-Auskoppelemente (25) enthält.
- Frequenzsynthesizer nach den Ansprüchen 2 und 3, dadurch gekennzeichnet, daß die Dummy-Auskoppelelemente (25) Lastelemente sind, welche die Belastung durch den Eingang des M:1-Multiplexers (18) der PLL-Phasenverzögerungseinrichtung (10) nachbilden.
- Frequenzsynthesizer nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die unter anderem den weiteren Phasen-Frequenz-Detektor (22) enthaltende Hilfs-PLL-Schleife so ausgelegt ist, daß sie eine sehr hohe Schleifenbandbreite aufweist.
- Frequenzsynthesizer nach Anspruch 5, dadurch gekennzeichnet, daß die Hilfs-PLL-Schleife so ausgelegt ist, daß ihre Bandbreite in der Größenordnung der Referenzfrequenz (fRef) liegt.
- Frequenzsynthesizer nach einem der vorhergehenden Ansprüche, gekennzeichnet durch eine Ausführung in integrierter Schaltkreistechnik.
- Frequenzsynthesizer nach einem der vorhergehenden Ansprüche,
dadurch gekennzeichnet, daß
eine Ladungspumpe (6) zwischen den Phasen-Frequenz-Detektor (3) und das Schleifenfilter (7) geschaltet ist.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19840241 | 1998-09-03 | ||
DE19840241A DE19840241C1 (de) | 1998-09-03 | 1998-09-03 | Digitaler PLL (Phase Locked Loop)-Frequenzsynthesizer |
PCT/DE1999/001569 WO2000014879A2 (de) | 1998-09-03 | 1999-05-28 | Digitaler pll-frequenzsynthesizer |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1145437A2 EP1145437A2 (de) | 2001-10-17 |
EP1145437B1 true EP1145437B1 (de) | 2003-07-30 |
Family
ID=7879726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99936339A Expired - Lifetime EP1145437B1 (de) | 1998-09-03 | 1999-05-28 | Digitaler pll-frequenzsynthesizer |
Country Status (5)
Country | Link |
---|---|
US (1) | US6359950B2 (de) |
EP (1) | EP1145437B1 (de) |
JP (1) | JP3597471B2 (de) |
DE (1) | DE19840241C1 (de) |
WO (1) | WO2000014879A2 (de) |
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FR2481549A1 (fr) * | 1980-04-25 | 1981-10-30 | Thomson Brandt | Dispositif de synthese et de demodulation combinees pour recepteurs d'ondes modulees en frequence et recepteur le comportant |
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GB8512912D0 (en) * | 1985-05-22 | 1985-06-26 | Plessey Co Plc | Phase modulators |
DE3544371A1 (de) * | 1985-12-14 | 1987-06-19 | Wandel & Goltermann | Generator mit digitaler frequenzeinstellung |
US5495206A (en) * | 1993-10-29 | 1996-02-27 | Motorola, Inc. | Fractional N frequency synthesis with residual error correction and method thereof |
US5907253A (en) * | 1997-11-24 | 1999-05-25 | National Semiconductor Corporation | Fractional-N phase-lock loop with delay line loop having self-calibrating fractional delay element |
-
1998
- 1998-09-03 DE DE19840241A patent/DE19840241C1/de not_active Expired - Fee Related
-
1999
- 1999-05-28 JP JP2000569512A patent/JP3597471B2/ja not_active Expired - Fee Related
- 1999-05-28 EP EP99936339A patent/EP1145437B1/de not_active Expired - Lifetime
- 1999-05-28 WO PCT/DE1999/001569 patent/WO2000014879A2/de active IP Right Grant
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2001
- 2001-03-05 US US09/799,669 patent/US6359950B2/en not_active Expired - Fee Related
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JP2003515963A (ja) | 2003-05-07 |
DE19840241C1 (de) | 2000-03-23 |
WO2000014879A3 (de) | 2002-07-11 |
EP1145437A2 (de) | 2001-10-17 |
US20010036240A1 (en) | 2001-11-01 |
US6359950B2 (en) | 2002-03-19 |
JP3597471B2 (ja) | 2004-12-08 |
WO2000014879A2 (de) | 2000-03-16 |
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