EP2191518A2 - Lighting emitting device package and method of fabricating the same - Google Patents

Lighting emitting device package and method of fabricating the same

Info

Publication number
EP2191518A2
EP2191518A2 EP08793723A EP08793723A EP2191518A2 EP 2191518 A2 EP2191518 A2 EP 2191518A2 EP 08793723 A EP08793723 A EP 08793723A EP 08793723 A EP08793723 A EP 08793723A EP 2191518 A2 EP2191518 A2 EP 2191518A2
Authority
EP
European Patent Office
Prior art keywords
layer
emitting device
light emitting
package body
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP08793723A
Other languages
German (de)
French (fr)
Other versions
EP2191518A4 (en
EP2191518B1 (en
Inventor
Bum Chul Cho
Geun Ho Kim
Sung Jin Son
Jin Soo Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of EP2191518A2 publication Critical patent/EP2191518A2/en
Publication of EP2191518A4 publication Critical patent/EP2191518A4/en
Application granted granted Critical
Publication of EP2191518B1 publication Critical patent/EP2191518B1/en
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • Embodiments relate to a light emitting device package and a method of fabricating the same.
  • a light emitting diode constitutes a light emitting source using GaAs series
  • AlGaAs series GaN series, InGaN series, or InGaAlP series compound semiconductor materials.
  • This LED is packaged and used as a light emitting device for emitting various colors, and the light emitting device is used as a light source in various fields such as an on/off display for displaying colors, an alphanumeric display, and an image display. Disclosure of Invention Technical Problem
  • Embodiments provide a light emitting device package capable of improving the soldering characteristic and light intensity of a package and a method of fabricating the same.
  • Embodiments also provide a light emitting device package capable of preventing resin material from overflowing toward the outside through an upper projection of a package body such that work yield deterioration due to the resin material can be avoided, and a method of fabricating the same.
  • An embodiment provides a light emitting device package comprising: a package body comprising a cavity; a seed layer on a surface of the package body; a conductive layer on the seed layer; a mirror layer on the conductive layer; and a light emitting device in the cavity.
  • a method of fabricating a light emitting device package comprising: forming a cavity with a predetermined depth in a package body; forming a seed layer on a surface of the package body; forming a plated layer on the seed layer at an outer circumference of the package body; forming a conductive layer on the seed layer in the cavity of the package body; electrically separating the seed layer, the plated layer, and the conductive layer by partially etching them; forming a mirror layer on the conductive layer; and mounting a light emitting device in the cavity.
  • Embodiments improve the soldering characteristic of a package.
  • Embodiments prevent resin material from overflowing through an upper projection of a package body and also prevent work yield deterioration due to resin material during soldering. [10] Embodiments improve the light intensity of a package.
  • Fig. 1 is a cross-sectional view of a light emitting device package according to an embodiment.
  • Figs. 2 to 8 are views illustrating a method of fabricating a light emitting device package according to an embodiment.
  • Fig. 9 is a flowchart illustrating a process of forming a metal layer on a package body according to an embodiment.
  • Fig. 1 is a cross-sectional view of a light emitting device package according to an embodiment.
  • a light emitting device package 100 is a silicon-based wafer level package (WLP) and uses a polyhedral (e.g., rectangular parallelepiped) package frame
  • a cavity 111 is formed in the top of the package body 110.
  • the cavity 111 may be realized with any one of a tube with an inner space, a polygonal groove, and a circular groove.
  • An inner side 114 of the cavity 111 is formed slanted at a predetermined angle or with a predetermined curvature.
  • a top 115 of the package body 110 is formed on the outside of the cavity 111, and a body side 116 is curved at a predetermined angle to be slanted toward the top and bottom directions but is not limited thereto.
  • a seed layer 122 is formed on an entire surface of the package body 110 except for open regions 131 and 132.
  • the seed layer 122 comprises a sequentially-stacked Ti layer/Cu layer or a sequentially- stacked Ti layer/Cu layer/Ti layer.
  • the seed layer 122 improves adhesiveness with respect to the package body 110, and also between other metal layers (e.g., comprising a conductive layer and a plated layer).
  • the seed layer 122 may be formed with a thickness of 1000 Ato 7000 A.
  • a plated layer 124 is formed on the seed layer 122 at the outer circumference of the package body 110.
  • the outer circumference of the package body 110 comprises the outers of a portion of the rear 118, the side 116, and the top 115 of the package body 110.
  • the plated layer 124 is formed with a thick layer through a plating method (e.g., an electrolytic or electroless plating method), such that soldering characteristic during a surface mount technology (SMT) process can be improved.
  • the plated layer 124 is formed with a thickness of 1.5 ⁇ m to 2.0 ⁇ m, for example.
  • the plated layer 124 can be formed with a multilayer comprising Cu, Ni, Au, and Ti on the seed layer 122 and, for example, comprises a sequentially- stacked Cu layer/Ni layer/ Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer.
  • end portions 124a and 124b of the plated layer 124 are formed extending to the top 115 of the package body 110.
  • the conductive layer 126 is formed on the seed layer 122 at the cavity 111 of the package body 110.
  • the conductive layer 126 is formed extending to a bottom 112, the inner side 114, and the body top 115 of the cavity 111.
  • the conductive layer 126 is formed with a multilayer comprising Cu, Ni, Au, and Ti and, for example, comprises a sequentially-stacked Cu layer/Ni layer/Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer.
  • end portions 126a and 126b of the conductive layer 126 extends on the end portions 124a and 124b at the body top 115 and protrudes with a projection form.
  • the end portions 126a and 126b of the conductive layer 126 prevents resin material 150 molded in the cavity 111 from overflowing, and also foreign materials from inflowing through the body side 116. Because the resin material 150 is prevented from overflowing toward the outside of the package body 110, work yield deterioration due to the resin material 150 can be avoided during the soldering of the light emitting device package 100.
  • the conductive layer 126 is formed thicker than other layers, for example, with a thickness of 1000 A to 7000 A.
  • the conductive layer 126 can improve electrical characteristic.
  • a mirror layer 128 is formed on the conductive layer 126.
  • the mirror layer 128 selectively comprises a sequentially-stacked Ti layer/ Ag layer, a sequentially- stacked Ti layer/ Al layer, an alloy of Ti and Ag, and an alloy of Ti and Al, on the conductive layer 126.
  • the mirror layer 128 is formed with a thickness of 1000 A to 4000 A, for example. Additionally, because the mirror layer 128 is formed on the conductive layer 126, metal materials can be prevented from peeling off.
  • the mirror layer 128 improves a reflected amount of the light generated from a light emitting device 140 such that the light intensity of the light emitting device package 100 can be improved.
  • the seed layer 122, the conductive layer 126, and the mirror layer 128 of the package body 110 may be deposited using an electron beam deposition method or/and a sputtering method.
  • At least one light emitting device 140 is mounted in the cavity 111 of the package body 110, and the light emitting device 140 may comprise colored LED chips such as a blue LED chip, a green LED chip, and a red LED chip, or a UV LED chip.
  • the light emitting device 140 is mounted on an electrode terminal of the cavity 111.
  • the mirror layer 128 and the conductive layer 126 formed on the bottom 112 of the cavity 111 may be used as an electrode terminal.
  • the electrode terminal in the cavity 111 is electrically connected to a portion of the rear 118 along the side 116 of the package body 110.
  • the first open region 131 is formed in the cavity 111 and the first open region 131 divides the seed layer 122, the conductive layer 126, and the mirror layer 128 into a plurality of areas.
  • the second open region 132 is formed at the rear 118 of the package body 110, and the second open region 132 divides the seed layer 122 and the plated layer 124 into a plurality of regions. That is, the first and second open regions 131 and 132 divide the electrode terminal into a plurality of electrode terminals.
  • the light emitting device 140 can be connected to the electrode terminal through a wire 142 or a flip chip method, but is not limited thereto.
  • An arrangement structure of the electrode terminal may vary based on the number of LED chips and a design method, but is not limited thereto.
  • the resin material 150 of a transparent resin material is molded in the cavity 111 and protects the light emitting device 140.
  • the resin material 150 is formed of transparent epoxy or silicon material and at least one of red, green blue fluorescent substances may be added to the resin material 150, but is not limited thereto.
  • FIGs. 2 to 8 are views illustrating a method of fabricating a light emitting device package according to an embodiment.
  • Fig. 9 is a flowchart illustrating a process of forming a metal layer on a package body according to an embodiment.
  • the cavity 111 is formed with a predetermined depth in the top of the package body 110.
  • the cavity 111 may be formed with a predetermined depth by etching the middle top of the package body 110.
  • the package body 110 is a silicon wafer.
  • the seed layer 122 is deposited on the entire surfaces 112, 114, 116, and 118 of the package body 110 in operation SlOl of Fig. 9.
  • the seed layer 122 improves adhesiveness with respect to the package body 110, and also between other metal layers.
  • the seed layer 122 may be formed with a thickness of 1000 Ato 7000 A, for example.
  • a first mask pattern Ml is formed on the seed layer 122 on top of the package body 110 in operation S 103 of Fig. 9.
  • the first mask pattern Ml is formed on the bottom 112 and the inner side 114 of the cavity 111 and a portion of the body top 115 through a photo-lithography method.
  • the plated layer 124 is deposited on the seed layer 122 at the outer circumference of the package body 110, i.e., an area except for the first mask pattern Ml.
  • the plated layer 124 may be formed with a multilayer comprising Cu, Ni, Au, and Ti on the seed layer 122, and, for example, comprises a sequentially-stacked Cu layer/Ni layer/ Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer.
  • the plated layer 124 is formed with a thickness of 1.5 ⁇ m to 2.0 ⁇ m, for example. If the upper most layer of the seed layer 122 is a Ti layer, a Cu layer of the plated layer 124 may be formed after etching it.
  • the plated layer 124 is formed with a thick layer through a plating method such that soldering characteristic can be improved during a SMT process.
  • a second mask pattern M2 is formed in operation S 109 of Fig. 9.
  • the second mask pattern M2 is formed at the outer circumference of the package body 110, i.e., the outers of the body top 115, the body side 116, and the rear 118, through a photolithography method.
  • the conductive layer 126 is formed on the seed layer 122 in an area except for the second mask pattern M2 in operation Si l l of Fig. 9.
  • the conductive layer 126 extends from the inner circumference of the cavity 111 to the body top 115.
  • the end portions 126a and 126b of the conductive layer 126 on the body top 115 are formed on the end portions 124a and 124b of the plated layer 124.
  • the conductive layer 126 comprises a sequentially- stacked Cu layer/Ni layer/Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer, on the seed layer
  • the conductive layer 126 is formed with a thickness of 1000 A to 7000 A, and the Ni layer or the Au layer may be formed with a thickness of 100 A to 3000 A.
  • the Au layer prevents the conductive layer 126 from being damaged by an impact or friction.
  • the conductive layer 126 is formed with a multi-metal layer, it can improve electrical characteristics. Moreover, since the end portions 126a and 126b of the conductive layer 126 protrude with a projection form on the body top 115, the resin material 150 filled in the cavity 111 can be prevented from overflowing. The resin material 150 may be molded into the cavity 111 through a dispensing process after mounting a light emitting device.
  • the second mask pattern M2 is removed in operation Sl 13 of Fig. 9, and then the first open region 131 is formed by etching the inner cir- cumference of the cavity 111 and the second open region 132 is formed by etching the body rear 118 in operation Sl 15 of Fig. 9. Because the first and second open regions 131 and 132 are etched up to the seed layer 122, at least two electrode terminals are disposed with an open structure on the both sides of the cavity 111.
  • a third mask pattern M3 can be formed on the outer circumference of the package body 110 in operation Sl 17 of Fig. 9.
  • the third mask pattern M3 can be formed through a photo-lithography method.
  • the third mask pattern M3 is formed on a upper portion of the plated layer 124, the end portions 126a and 126b of the conductive layer 126.
  • the third mask pattern M3 can be formed in a part among the end portions 126a and 126b of the conductive layer 126, on the plated layer 124, the first open region 131 of the cavity bottom 112, and the second open region 132 of the body rear 118 at least.
  • the mirror layer 128 is formed on the conductive layer 126 where no third mask pattern M3 is formed in operation Sl 19 of Fig. 9.
  • the mirror 128 comprises a sequentially-stacked Ti layer/ Ag layer, a sequentially stacked Ti layer/ Al layer, or an alloy of Ti and Al, on the conductive layer 126.
  • the mirror layer 128 is formed with a thickness of 1000 A to 4000 A.
  • a luminous efficiency of LED chip can increase.
  • an end portion of the mirror layer 128 can be formed on an end portion of the conductive layer 126 but is not limited thereto.
  • a process for forming the mirror layer 128 can be performed before forming the first and second open regions 131 and 132.
  • the light emitting device 140 is attached to the mirror layer 128 through an adhesive and then is electrically connected to the mirror layer 128 and the conductive layer 126 through the wire 142.
  • the light emitting device 140 may be connected through a flip method or a die attachment method.
  • the light emitting device 140 may comprise colored LED chips such as a blue LED chip, a green LED chip, and a red LED chip, or a UV LED chip.
  • the resin material 150 that light transmits or the resin material 150 to which at least one kind of a fluorescent substance is added is molded in the cavity 111. Additionally, a convex lens can be attached on the resin material 150.
  • Embodiments are used as a light emitting device package comprising an LED.
  • Embodiments are used as a light emitting device package of a silicon wafer.
  • Embodiments are used as a light source in various fields such as an on/off display, an alphanumeric display, and an image display by the use of a wafer level package

Abstract

Provided is a light emitting device package and a method of fabricating the same. The light emitting device package comprises a package body having a cavity, a seed layer on a surface of the package body, a conductive layer on the seed layer, a mirror layer on the conductive layer, and a light emitting device in the cavity.

Description

Description
LIGHTING EMITTING DEVICE PACKAGE AND METHOD OF
FABRICATING THE SAME
Technical Field
[1] Embodiments relate to a light emitting device package and a method of fabricating the same. Background Art
[2] A light emitting diode (LED) constitutes a light emitting source using GaAs series,
AlGaAs series, GaN series, InGaN series, or InGaAlP series compound semiconductor materials.
[3] This LED is packaged and used as a light emitting device for emitting various colors, and the light emitting device is used as a light source in various fields such as an on/off display for displaying colors, an alphanumeric display, and an image display. Disclosure of Invention Technical Problem
[4] Embodiments provide a light emitting device package capable of improving the soldering characteristic and light intensity of a package and a method of fabricating the same.
[5] Embodiments also provide a light emitting device package capable of preventing resin material from overflowing toward the outside through an upper projection of a package body such that work yield deterioration due to the resin material can be avoided, and a method of fabricating the same. Technical Solution
[6] An embodiment provides a light emitting device package comprising: a package body comprising a cavity; a seed layer on a surface of the package body; a conductive layer on the seed layer; a mirror layer on the conductive layer; and a light emitting device in the cavity.
[7] An embodiment, a method of fabricating a light emitting device package comprising: forming a cavity with a predetermined depth in a package body; forming a seed layer on a surface of the package body; forming a plated layer on the seed layer at an outer circumference of the package body; forming a conductive layer on the seed layer in the cavity of the package body; electrically separating the seed layer, the plated layer, and the conductive layer by partially etching them; forming a mirror layer on the conductive layer; and mounting a light emitting device in the cavity.
Advantageous Effects [8] Embodiments improve the soldering characteristic of a package.
[9] Embodiments prevent resin material from overflowing through an upper projection of a package body and also prevent work yield deterioration due to resin material during soldering. [10] Embodiments improve the light intensity of a package.
Brief Description of the Drawings [11] Fig. 1 is a cross-sectional view of a light emitting device package according to an embodiment. [12] Figs. 2 to 8 are views illustrating a method of fabricating a light emitting device package according to an embodiment. [13] Fig. 9 is a flowchart illustrating a process of forming a metal layer on a package body according to an embodiment.
Best Mode for Carrying Out the Invention [14] Hereinafter, embodiments will be described with reference to the accompanying drawings. In description of the embodiments, the thickness of each layer is merely one example and is not limited to that in the accompanying drawings. [15] Fig. 1 is a cross-sectional view of a light emitting device package according to an embodiment. [16] Referring to Fig. 1, a light emitting device package 100 is a silicon-based wafer level package (WLP) and uses a polyhedral (e.g., rectangular parallelepiped) package frame
110. [17] A cavity 111 is formed in the top of the package body 110. The cavity 111 may be realized with any one of a tube with an inner space, a polygonal groove, and a circular groove. [18] An inner side 114 of the cavity 111 is formed slanted at a predetermined angle or with a predetermined curvature. [19] A top 115 of the package body 110 is formed on the outside of the cavity 111, and a body side 116 is curved at a predetermined angle to be slanted toward the top and bottom directions but is not limited thereto. [20] Additionally, at least one body side 116 of the package body 110 is formed slanted toward the top and bottom directions, and the other body side (not shown) may be perpendicularly formed. [21] A seed layer 122 is formed on an entire surface of the package body 110 except for open regions 131 and 132. The seed layer 122 comprises a sequentially-stacked Ti layer/Cu layer or a sequentially- stacked Ti layer/Cu layer/Ti layer. The seed layer 122 improves adhesiveness with respect to the package body 110, and also between other metal layers (e.g., comprising a conductive layer and a plated layer). The seed layer 122 may be formed with a thickness of 1000 Ato 7000 A.
[22] A plated layer 124 is formed on the seed layer 122 at the outer circumference of the package body 110. The outer circumference of the package body 110 comprises the outers of a portion of the rear 118, the side 116, and the top 115 of the package body 110.
[23] The plated layer 124 is formed with a thick layer through a plating method (e.g., an electrolytic or electroless plating method), such that soldering characteristic during a surface mount technology (SMT) process can be improved. The plated layer 124 is formed with a thickness of 1.5 μm to 2.0 μm, for example.
[24] The plated layer 124 can be formed with a multilayer comprising Cu, Ni, Au, and Ti on the seed layer 122 and, for example, comprises a sequentially- stacked Cu layer/Ni layer/ Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer.
[25] Here, end portions 124a and 124b of the plated layer 124 are formed extending to the top 115 of the package body 110.
[26] The conductive layer 126 is formed on the seed layer 122 at the cavity 111 of the package body 110. The conductive layer 126 is formed extending to a bottom 112, the inner side 114, and the body top 115 of the cavity 111. The conductive layer 126 is formed with a multilayer comprising Cu, Ni, Au, and Ti and, for example, comprises a sequentially-stacked Cu layer/Ni layer/Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer.
[27] Here, end portions 126a and 126b of the conductive layer 126 extends on the end portions 124a and 124b at the body top 115 and protrudes with a projection form. The end portions 126a and 126b of the conductive layer 126 prevents resin material 150 molded in the cavity 111 from overflowing, and also foreign materials from inflowing through the body side 116. Because the resin material 150 is prevented from overflowing toward the outside of the package body 110, work yield deterioration due to the resin material 150 can be avoided during the soldering of the light emitting device package 100.
[28] The conductive layer 126 is formed thicker than other layers, for example, with a thickness of 1000 A to 7000 A. The conductive layer 126 can improve electrical characteristic.
[29] A mirror layer 128 is formed on the conductive layer 126. The mirror layer 128 selectively comprises a sequentially-stacked Ti layer/ Ag layer, a sequentially- stacked Ti layer/ Al layer, an alloy of Ti and Ag, and an alloy of Ti and Al, on the conductive layer 126. The mirror layer 128 is formed with a thickness of 1000 A to 4000 A, for example. Additionally, because the mirror layer 128 is formed on the conductive layer 126, metal materials can be prevented from peeling off.
[30] The mirror layer 128 improves a reflected amount of the light generated from a light emitting device 140 such that the light intensity of the light emitting device package 100 can be improved.
[31] The seed layer 122, the conductive layer 126, and the mirror layer 128 of the package body 110 may be deposited using an electron beam deposition method or/and a sputtering method.
[32] At least one light emitting device 140 is mounted in the cavity 111 of the package body 110, and the light emitting device 140 may comprise colored LED chips such as a blue LED chip, a green LED chip, and a red LED chip, or a UV LED chip. The light emitting device 140 is mounted on an electrode terminal of the cavity 111.
[33] The mirror layer 128 and the conductive layer 126 formed on the bottom 112 of the cavity 111 may be used as an electrode terminal. The electrode terminal in the cavity 111 is electrically connected to a portion of the rear 118 along the side 116 of the package body 110. The first open region 131 is formed in the cavity 111 and the first open region 131 divides the seed layer 122, the conductive layer 126, and the mirror layer 128 into a plurality of areas. The second open region 132 is formed at the rear 118 of the package body 110, and the second open region 132 divides the seed layer 122 and the plated layer 124 into a plurality of regions. That is, the first and second open regions 131 and 132 divide the electrode terminal into a plurality of electrode terminals.
[34] Here, the light emitting device 140 can be connected to the electrode terminal through a wire 142 or a flip chip method, but is not limited thereto. An arrangement structure of the electrode terminal may vary based on the number of LED chips and a design method, but is not limited thereto.
[35] The resin material 150 of a transparent resin material is molded in the cavity 111 and protects the light emitting device 140. The resin material 150 is formed of transparent epoxy or silicon material and at least one of red, green blue fluorescent substances may be added to the resin material 150, but is not limited thereto.
[36] Figs. 2 to 8 are views illustrating a method of fabricating a light emitting device package according to an embodiment. Fig. 9 is a flowchart illustrating a process of forming a metal layer on a package body according to an embodiment.
[37] Referring to Figs. 2 and 3, the cavity 111 is formed with a predetermined depth in the top of the package body 110. The cavity 111 may be formed with a predetermined depth by etching the middle top of the package body 110. Here, the package body 110 is a silicon wafer.
[38] The seed layer 122 is deposited on the entire surfaces 112, 114, 116, and 118 of the package body 110 in operation SlOl of Fig. 9. The seed layer 122 improves adhesiveness with respect to the package body 110, and also between other metal layers.
The seed layer 122 may be formed with a thickness of 1000 Ato 7000 A, for example. [39] Referring to Figs. 3 and 4, a first mask pattern Ml is formed on the seed layer 122 on top of the package body 110 in operation S 103 of Fig. 9. Here, the first mask pattern Ml is formed on the bottom 112 and the inner side 114 of the cavity 111 and a portion of the body top 115 through a photo-lithography method.
[40] In operation S 105 of Fig. 9, the plated layer 124 is deposited on the seed layer 122 at the outer circumference of the package body 110, i.e., an area except for the first mask pattern Ml.
[41] The plated layer 124 may be formed with a multilayer comprising Cu, Ni, Au, and Ti on the seed layer 122, and, for example, comprises a sequentially-stacked Cu layer/Ni layer/ Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer. The plated layer 124 is formed with a thickness of 1.5 μm to 2.0 μm, for example. If the upper most layer of the seed layer 122 is a Ti layer, a Cu layer of the plated layer 124 may be formed after etching it. The plated layer 124 is formed with a thick layer through a plating method such that soldering characteristic can be improved during a SMT process.
[42] Referring to Figs. 4 and 5, the first mask pattern Ml is removed in operation S 107 of
Fig. 9 and a second mask pattern M2 is formed in operation S 109 of Fig. 9. The second mask pattern M2 is formed at the outer circumference of the package body 110, i.e., the outers of the body top 115, the body side 116, and the rear 118, through a photolithography method.
[43] The conductive layer 126 is formed on the seed layer 122 in an area except for the second mask pattern M2 in operation Si l l of Fig. 9. The conductive layer 126 extends from the inner circumference of the cavity 111 to the body top 115. Here, the end portions 126a and 126b of the conductive layer 126 on the body top 115 are formed on the end portions 124a and 124b of the plated layer 124.
[44] The conductive layer 126 comprises a sequentially- stacked Cu layer/Ni layer/Au layer or a sequentially-stacked Ti layer/Cu layer/Ni layer/Au layer, on the seed layer
122. The conductive layer 126 is formed with a thickness of 1000 A to 7000 A, and the Ni layer or the Au layer may be formed with a thickness of 100 A to 3000 A. The Au layer prevents the conductive layer 126 from being damaged by an impact or friction.
[45] Because the conductive layer 126 is formed with a multi-metal layer, it can improve electrical characteristics. Moreover, since the end portions 126a and 126b of the conductive layer 126 protrude with a projection form on the body top 115, the resin material 150 filled in the cavity 111 can be prevented from overflowing. The resin material 150 may be molded into the cavity 111 through a dispensing process after mounting a light emitting device.
[46] Referring to Figs. 5 and 6, the second mask pattern M2 is removed in operation Sl 13 of Fig. 9, and then the first open region 131 is formed by etching the inner cir- cumference of the cavity 111 and the second open region 132 is formed by etching the body rear 118 in operation Sl 15 of Fig. 9. Because the first and second open regions 131 and 132 are etched up to the seed layer 122, at least two electrode terminals are disposed with an open structure on the both sides of the cavity 111.
[47] Referring to Fig. 7, when the first and second open regions 131 and 132 are formed, a third mask pattern M3 can be formed on the outer circumference of the package body 110 in operation Sl 17 of Fig. 9. The third mask pattern M3 can be formed through a photo-lithography method. The third mask pattern M3 is formed on a upper portion of the plated layer 124, the end portions 126a and 126b of the conductive layer 126. Also, The third mask pattern M3 can be formed in a part among the end portions 126a and 126b of the conductive layer 126, on the plated layer 124, the first open region 131 of the cavity bottom 112, and the second open region 132 of the body rear 118 at least.
[48] The mirror layer 128 is formed on the conductive layer 126 where no third mask pattern M3 is formed in operation Sl 19 of Fig. 9. The mirror 128 comprises a sequentially-stacked Ti layer/ Ag layer, a sequentially stacked Ti layer/ Al layer, or an alloy of Ti and Al, on the conductive layer 126. The mirror layer 128 is formed with a thickness of 1000 A to 4000 A. Here, because the mirror layer 128 is formed on the conductive layer 126, a luminous efficiency of LED chip can increase.
[49] Moreover, an end portion of the mirror layer 128 can be formed on an end portion of the conductive layer 126 but is not limited thereto. A process for forming the mirror layer 128 can be performed before forming the first and second open regions 131 and 132.
[50] Referring to Figs. 7 and 8, the third mask pattern M3 is removed in operation S121 of
Fig. 9. Moreover, the light emitting device 140 is attached to the mirror layer 128 through an adhesive and then is electrically connected to the mirror layer 128 and the conductive layer 126 through the wire 142. Here, the light emitting device 140 may be connected through a flip method or a die attachment method. The light emitting device 140 may comprise colored LED chips such as a blue LED chip, a green LED chip, and a red LED chip, or a UV LED chip.
[51] The resin material 150 that light transmits or the resin material 150 to which at least one kind of a fluorescent substance is added is molded in the cavity 111. Additionally, a convex lens can be attached on the resin material 150.
[52] Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Industrial Applicability
[53] Embodiments are used as a light emitting device package comprising an LED.
[54] Embodiments are used as a light emitting device package of a silicon wafer.
[55] Embodiments are used as a light source in various fields such as an on/off display, an alphanumeric display, and an image display by the use of a wafer level package
(WLP).

Claims

Claims
[I] A light emitting device package comprising: a package body comprising a cavity; a seed layer on a surface of the package body; a conductive layer on the seed layer; a mirror layer on the conductive layer; and a light emitting device in the cavity. [2] The light emitting device package according to claim 1, wherein the cavity is formed in a tubular shape, a circular shape, or a polygonal shape having a predetermined groove. [3] The light emitting device package according to claim 1, comprising a plated layer on the seed layer at an outer circumference of the package body. [4] The light emitting device package according to claim 3, wherein an end portion of the conductive layer extends on a top of the package body and is formed with a projection form on the plated layer. [5] The light emitting device package according to claim 3, wherein the seed layer, the conductive layer, and the plated layer are electrically separated at the cavity and a rear of the package body. [6] The light emitting device package according to claim 1, wherein the seed layer comprises at least one of a titanium (Ti) layer and a copper (Cu) layer. [7] The light emitting device package according to claim 3, wherein the conductive layer and the plated layer comprises at least one of a Ti layer, a Cu layer, a Ni layer, and an Au layer. [8] The light emitting device package according to claim 1, wherein the mirror layer comprises at least one of Ti, Ag, Al, and an alloy thereof. [9] The light emitting device package according to claim 1, wherein at least one of the seed layer and the conductive layer is formed with a thickness of 1000 A to
7000 A, and the mirror layer is formed with a thickness of 1000 A to 4000 A. [10] The light emitting device package according to claim 1, wherein the light emitting device comprises a light emitting device (LED) chip that is electrically connected to the mirror layer and the conductive layer, and comprises resin material or fluorescence added resin material in the cavity.
[I I] The light emitting device package according to claim 1, wherein the conductive layer and the mirror layer are formed from a cavity bottom to a top of the package body, the package body is a silicon wafer. [12] A method of fabricating a light emitting device package, the method comprising: forming a cavity with a predetermined depth in a package body; forming a seed layer on a surface of the package body; forming a plated layer on the seed layer at an outer circumference of the package body; forming a conductive layer on the seed layer in the cavity of the package body; electrically separating the seed layer, the plated layer, and the conductive layer by partially etching them; forming a mirror layer on the conductive layer; and mounting a light emitting device in the cavity. [13] The method according to claim 12, wherein an end portion of the conductive layer extends on a top of the package body and is formed with a projection form on the plated layer. [14] The method according to claim 12, wherein the forming of the plated layer comprises: forming a first mask pattern on an inner circumference of the cavity on the seed layer and a top of the package body; forming the plated layer on an outer circumference of the package body where no first mask pattern is formed; and removing the first mask pattern, wherein the plated layer comprises a sequentially-stacked Cu/Ni/Au layer or a sequentially-stacked Ti/Cu/Ni/Au layer.
[15] The method according to claim 12, wherein the seed layer is formed with a sequentially-stacked Ti and Cu layer, the conductive layer is formed with a sequentially-stacked Cu/Ni/Au layer or a sequentially-stacked Ti/Cu/Ni/Au layer, and the mirror layer is formed with one of Ti/ Ag, Ti/ Al, and an alloy thereof.
EP08793723.1A 2007-09-06 2008-09-05 Lighting emitting device package and method of fabricating the same Not-in-force EP2191518B1 (en)

Applications Claiming Priority (2)

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KR1020070090321A KR100877881B1 (en) 2007-09-06 2007-09-06 Lighting emitting diode package and fabrication method thereof
PCT/KR2008/005264 WO2009031856A2 (en) 2007-09-06 2008-09-05 Lighting emitting device package and method of fabricating the same

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EP2191518A2 true EP2191518A2 (en) 2010-06-02
EP2191518A4 EP2191518A4 (en) 2013-10-23
EP2191518B1 EP2191518B1 (en) 2016-06-15

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EP (1) EP2191518B1 (en)
JP (1) JP5154649B2 (en)
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US8203163B2 (en) 2012-06-19
WO2009031856A3 (en) 2009-05-07
CN101796659B (en) 2012-09-19
EP2191518A4 (en) 2013-10-23
JP5154649B2 (en) 2013-02-27
JP2010538490A (en) 2010-12-09
CN101796659A (en) 2010-08-04
KR100877881B1 (en) 2009-01-08
WO2009031856A2 (en) 2009-03-12
US20110309391A1 (en) 2011-12-22
EP2191518B1 (en) 2016-06-15

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