Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20010000492 A1
Publication typeApplication
Application numberUS 09/729,848
Publication dateApr 26, 2001
Filing dateDec 6, 2000
Priority dateJun 19, 1998
Also published asUS6025624, US6180452, US6373084
Publication number09729848, 729848, US 2001/0000492 A1, US 2001/000492 A1, US 20010000492 A1, US 20010000492A1, US 2001000492 A1, US 2001000492A1, US-A1-20010000492, US-A1-2001000492, US2001/0000492A1, US2001/000492A1, US20010000492 A1, US20010000492A1, US2001000492 A1, US2001000492A1
InventorsThomas Figura
Original AssigneeFigura Thomas A.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Shared length cell for improved capacitance
US 20010000492 A1
Abstract
A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.
Images(16)
Previous page
Next page
Claims(42)
What is claimed as new and desired to be protected by Letters Patent of the United States is:
1. A DRAM cell comprising:
a container capacitor having a storage electrode, the storage electrode having a width of 1F and a length greater than 4F, where F is the minimum lithographic dimension.
2. The cell of
claim 1
, wherein the storage electrode has a length of at least 6F where F is the minimum lithographic dimension.
3. The cell of
claim 1
, wherein the storage electrode has a perimeter of greater than 12F where F is the minimum lithographic dimension.
4. The cell of
claim 1
, wherein the storage electrode comprises hemispherical grain polysilicon.
5. The cell of
claim 1
, wherein the storage electrode has a U-shaped cross-section.
6. The cell of
claim 1
, wherein the storage electrode has a rectangular cross-section.
7. The cell of
claim 1
, further comprising a buried bit line.
8. A memory cell array comprising:
a first memory cell and a second memory cell, each cell having a transistor and a container capacitor, said capacitor including a storage electrode covering at least a portion of the first memory cell and at least a portion of the second memory cell,
at least three word lines; and
at least one bit line.
9. The memory cell array of
claim 8
, wherein said storage electrodes cover the transistor of the first memory cell and the transistor of the second memory cell.
10. The memory cell array of
claim 8
, wherein each storage electrode covers at least three of said at least three word lines.
11. The memory cell array of
claim 8
, further comprising at least four word lines, and wherein each storage electrode covers at least four of said at least four word lines.
12. The memory cell array of
claim 8
, wherein the capacitors are formed over said at least one bit line.
13. The memory cell array of
claim 8
, wherein said array is a DRAM cell array.
14. The memory cell array of
claim 8
, wherein each storage electrode comprises two rectangular runners at least partially coated and connected by a conductive layer.
15. The memory cell array of
claim 14
, wherein the conductive layer is hemispherical grain polysilicon.
16. The memory cell array of
claim 8
, wherein each storage electrode comprises one rectangular runner.
17. The memory cell array of
claim 16
, wherein said rectangular runner is coated with hemispherical grain polysilicon.
18. An integrated circuit comprising at least two memory cells, each of said cells having a transistor and a container capacitor, and wherein the storage electrode of each of said capacitors covers the transistor of both of said memory cells and has a length of at least four times the width of said storage electrode.
19. An integrated circuit of
claim 18
wherein each of said storage electrodes has a length of greater than 4F where F is the minimum lithographic dimension.
20. The integrated circuit of
claim 19
wherein each of said storage electrodes has a length of between about 6F and 8F.
21. The integrated circuit of
claim 20
wherein each of said storage electrodes has a width of about 1F.
22. The integrated circuit of
claim 18
wherein said storage electrodes are parallel to each other.
23. A method for fabricating an array of memory cells containing container capacitors, comprising the steps of:
providing a semiconductor substrate with at least two transistors and a plurality of word lines formed therein;
forming sacrificial molding bars in parallel rows atop at least some of said transistors and word lines;
forming runners adjoining the sacrificial molding bars;
removing the sacrificial molding bars; and
forming a conductive layer on the runners to form the storage electrodes of said container capacitors of said array over said at least two transistors.
24. The method of
claim 23
wherein the initial step further comprises providing a bit line on the semiconductor substrate.
25. The method
claim 23
further comprising forming storage electrodes extending over at least three of said plurality of word lines.
26. The method of
claim 23
wherein said runners are formed of an insulating material, and wherein each storage electrode comprises two runners partially coated by the conductive layer so that the storage electrode has a U-shaped cross-section.
27. The method of
claim 26
wherein said insulating material is silicon nitride.
28. The method of
claim 26
wherein said insulating material is silicon oxide.
29. The method of
claim 23
wherein said runners are formed of a conductive material, and wherein each storage electrode comprises one runner coated by the conductive layer so that the storage electrode has a rectangular cross-section.
30. The method of
claim 29
wherein said conductive material is polysilicon.
31. The method of
claim 29
wherein said conductive material is amorphous silicon.
32. The method of
claim 23
wherein said conductive layer is hemispherical-grain polysilicon.
33. The method of
claim 23
wherein said conductive layer is titanium nitride.
34. A method for fabricating an array of memory cells containing capacitors comprising the steps of:
providing a semiconductor substrate with at least two transistors and a plurality of word lines formed therein;
forming conductive runners in parallel rows atop at least some of said transistors and word lines;
forming sacrificial spacers adjoining the conductive runners;
forming polysilicon runners between said sacrificial spacers; and
removing the sacrificial spacers to form the storage electrodes of said container capacitors of said array over said at least two transistors.
35. The method of
claim 34
comprising the further step of forming a conductive layer on the conductive and polysilicon runners.
36. The method of
claim 34
wherein each storage electrode comprises one runner coated by the conductive layer so that the storage electrode has a rectangular cross-section.
37. The method of
claim 34
further comprising providing a bit line on the semiconductor substrate.
38. The method of
claim 34
further comprising forming storage electrodes extending over at least three of said plurality of word lines.
39. The method of
claim 34
wherein said conductive runners are formed of polysilicon.
40. The method of
claim 34
wherein said conductive runners are formed of amorphous silicon.
41. The method of
claim 35
wherein said conductive layer is hemispherical-grain polysilicon.
42. The method of
claim 35
wherein said conductive layer is titanium nitride.
Description
FIELD OF THE INVENTION

1. This invention relates generally to semiconductor memory storage devices, and more particularly to the design of capacitor electrodes for use in integrated circuits.

BACKGROUND OF THE INVENTION

2. Capacitors are used in a wide variety of semiconductor circuits. Because capacitors are of special importance in dynamic random access memory (DRAM) circuits, the invention will therefore be discussed in connection with DRAM circuits. However, the invention has broader applicability to any other memory circuits in which capacitors are used.

3. DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

4.FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 10. For each cell, the capacitor 14 has two connections, located on opposite sides of the capacitor 14. The first connection is to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1”signal) of the circuit. The second connection is to the drain of the FET 12. The gate of the FET 12 is connected to the word line 18, and the source of the FET is connected to the bit line 16. This connection enables the word line 18 to control access to the capacitor 14 by allowing or preventing a signal (a logic “0”or a logic “1”) on the bit line 16 to be written to or read from the capacitor 14.

5. The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip.

6. Because the capacitor in a memory cell usually occupies a large portion of the cell area, many efforts at achieving higher cell packing density focus on reducing the semiconductor area occupied by the capacitor. Maintaining or increasing capacitance of a capacitor as its relative area is decreased is necessary not only to maintain charge at the refresh rates used, but also to facilitate information detection and decrease soft errors resulting from alpha particles.

7. In order to minimize the area occupied by a capacitor and maximize capacitance, various storage cell designs have been developed, including planar capacitors, stacked capacitor (STC) cells, and trench capacitors. Planar capacitors are located next to the transistor, stacked capacitors are stacked or placed over the access transistor, and trench capacitors are formed in the wafer substrate beneath the transistor. Most large capacity DRAMs use stacked capacitors because of their greater capacitance, reliability, and ease of formation.

8. One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube having an oval or cylindrical shape when viewed from the top down. The wall of the tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon) separated by a dielectric. The bottom end of the tube is closed. The outer wall is in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container, hence the name “container capacitor.”

9. In addition, methods of forming a rough surface on the storage electrode of a capacitor have been developed to increase the capacitance by increasing the surface area of the storage electrode. One of the most successful techniques for creating a rough surface is the formation of hemispherical-grain (HSG) polysilicon nodules on the surface of the storage electrode.

10. As memory cell density continues to increase, efficient use of space becomes ever more important. Therefore, what is needed is a capacitor that maximizes surface area without increasing the proportion of cell area occupied by the capacitor relative to the other cell components.

SUMMARY OF THE INVENTION

11. The present invention provides an improved storage electrode for a container capacitor formed to span more than one cell in length. The narrow, elongated capacitor has a larger perimeter, resulting in increased capacitor wall area and therefore increased capacitance over the typical capacitor, without increasing the amount of cell area occupied by the capacitor. Methods for forming the improved storage electrode capacitor are also disclosed.

12. Advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

13.FIG. 1 is a circuit diagram of a portion of a conventional DRAM memory circuit;

14.FIG. 2A is a perspective view of one embodiment of a memory circuit according to the present invention showing a capacitor storage electrode;

15.FIG. 2B is a top view of the perspective view of FIG. 2A;

16.FIG. 3A is a top view of a known memory circuit showing a conventional capacitor storage electrode;

17.FIG. 3B is a side view of a cross section of the known memory circuit of FIG. 3A;

18.FIG. 4 is a perspective view of a portion of a semiconductor wafer at an early processing step according to one embodiment of the present invention;

19.FIG. 5 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 4;

20.FIG. 6 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 5;

21.FIG. 7 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 6;

22.FIG. 8 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 7;

23.FIG. 9 is a perspective view of a second embodiment of the present invention;

24.FIG. 10 is a perspective view of a portion of a semiconductor wafer at an early processing step according to the second embodiment of the present invention;

25.FIG. 11 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 10;

26.FIG. 12 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 11;

27.FIG. 13 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 12;

28.FIG. 14 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 13; and

29.FIG. 15 is a perspective view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

30. In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

31. The terms wafer or substrate used in the following description include any semiconductor-based structure having an exposed silicon surface in which to form the structure of this invention. Wafer and substrate are to be understood as including silicon-on-insulator, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation.

32. Exemplary constructions of fabrication processes for container capacitors according to several embodiments of the present invention are described below. It is to be understood, however, that these processes are only a few examples of many possible processes. For example, the capacitor is formed over the bit-line in the following process, but the bit-line could also be formed over the capacitor. Variants in the masking and etching processes are also contemplated, as are variations in the structure that retain the spirit of the invention. The following detailed description is, therefore, not to be taken in a limiting sense.

33. Referring now to the drawings, where like elements are designated by like reference numerals, an embodiment of the capacitor storage electrode array 10 of the present invention is shown in FIG. 2. The capacitor storage electrode array 10 is comprised of a plurality of storage electrodes 20 associated with access field effect transistors (FETS) 22 on a semiconductor wafer 24. Each storage electrode 20 and its associated access FET 22 correspond to a memory cell 26 suitable for use in a DRAM or other memory array.

34. The wafer 24 comprises a bulk semiconductor substrate having electrically conductive diffusion regions 28, word lines 30, and bit lines (not shown) formed therein, as can be seen by referring to FIG. 2. The structure shown in FIGS. 2(a) and 2(b) is a buried bit line or capacitor-over-bit line structure, in which the capacitor storage electrode array 10 is formed over the bit lines.

35. Each storage electrode 20 is connected to the diffusion region 28 via a polysilicon plug 34, and to the bit line via a polysilicon plug 42. The storage electrodes 20 comprise insulative film runners 36 coated with a layer of hemispherical-grain (HSG) polysilicon 38 or another conductive layer. The storage electrodes 20 are arranged in complementary pairs 40 parallel to one another, as can best be seen in FIG. 2(b). Each complementary pair 40 of storage electrodes 20 relates to two cells 26, 26′, with the storage electrode 20 of each cell extending over that cells access FET 22 to partially or completely cover the access FET 22′ of the complementary cell 26′ as well. Each storage electrode 20 comprises two runners 36 that are partially coated with HSG polysilicon 38, as shown in FIG. 2(a). The storage electrode 20 has a U-shaped cross section due to the shape of the HSG layer 38. Oxide layers 44, 46 serve to insulate active regions of the cell 26 from each other. Insulation layer 48 isolates the storage electrode 20 from the underlying active regions.

36.FIG. 2(b) depicts a storage electrode array 10 in which the storage electrodes 20 extend over the length of the related pair of cells. Each storage electrode 20 has a perimeter of well over 12F, preferably at least about 15 up to 18F, where F is the minimum feature size. The storage electrodes 20 of FIG. 2(b) may be seen to cross over four word lines. A variant structure in which the storage electrodes 20 of each cell 26 extend only partially over the complementary cell 26′, providing each storage electrode 20 with a perimeter in the range of about 12 to 15F, where F is the minimum feature size is also contemplated, but not shown. In such a variant structure the storage electrodes 20 would cross over at least three word lines, but less than four word lines.

37. Referring now to FIG. 3, depicting a known container capacitor storage electrode, the advantages of the present invention can be identified. The storage electrode of FIG. 3 has a perimeter of well under 12F, where F is the minimum feature size. However, referring now to FIGS. 2 and 3, it is evident that while both capacitor storage electrodes have a similar area, the storage electrode of FIG. 2 has a much greater perimeter than that of FIG. 3. The novel structure of the storage electrode of the embodiment depicted in FIG. 2 enables the storage electrode to maintain the same area as the known electrode while greatly increasing the perimeter of the capacitor and thereby increasing its container wall area and capacitance. This advantage is possible due to the shared length capacitors of the invention, wherein each capacitor storage node has a length which extends over its adjacent cell, and has a width which accommodates the extended length capacitor node of the adjacent cell.

38. The capacitor storage electrode array 10 is manufactured through a process described as follows, and illustrated by FIGS. 4 through 8. The process begins at a point in the DRAM manufacturing sequence that follows formation of field effect transistors, diffusion regions, word lines and bit lines on a semiconductor wafer 24.

39. As seen in FIG. 4, formation of the storage electrode array 10 begins with deposition and subsequent etching of a sacrificial mold layer (not shown) on top of the wafer 24. The sacrificial mold layer may comprise borophosphosilicate glass (BPSG), silicon dioxide, or another substance that is selectively etchable. A “sacrificial” layer is one which is used only during fabrication and which will not be present in the final product. The mold layer may be deposited using well-established deposition techniques such as chemical vapor deposition (CVD). A resist and mask are applied, and photolithographic techniques are used to define areas to be etched-out. A directional etching process such as reactive ion etching (RIE) is used to etch through the mold layer to form parallel molding bars 50, resulting in the structure shown in FIG. 4.

40. The next step is the formation of insulating runners 36 on the sides of the molding bars 50, as seen in FIG. 4. The insulating runners 36 are formed by deposition of an insulating layer (not shown) of silicon nitride or silicon oxide on the sides of the molding bars 50, and by subsequent directional etching to shape the runners 36, and to leave the top surface of the molding bars 50 exposed. The resultant parallel runners 36 are shown most clearly in FIG. 4.

41. The sacrificial molding bars 50 are then removed by an etching process, preferably with a wet etch that is selective for BPSG over silicon. The resultant structure is shown in FIG. 5. Referring now to FIG. 6, a conductive layer 38 is then deposited or formed on the inner and outer surfaces of the runners 36. The conductive layer 38 may be formed of polysilicon, hemispherical-grain (HSG) polysilicon, titanium nitride, or the like, but is preferably HSG polysilicon. The HSG polysilicon layer 38 may be formed by low pressure chemical vapor deposition (LPCVD) of polysilicon under carefully controlled pressure and temperature so that nucleation occurs. Deposition of HSG polysilicon may be carried out in helium-diluted SiH4 gas at 1.0 torr pressure and 550°C. The thickness of the HSG polysilicon layer 38 is preferably less than one-half of the runner-to-runner distance.

42. Referring now to FIGS. 7 and 8, the runners 36 are formed into individual storage electrodes 20. First, chemical-mechanical polishing (CMP) or other planarization methods are used to remove HSG from the top surfaces of the runners 36, forming parallel storage electrode bars 58, as can be seen in FIG. 7. Then a resist and mask are applied, and a directional etching process such as RIE is used to separate the storage electrode bars 58 into storage electrodes 20, as shown in FIG. 8. Conventional processing is then performed to construct the remainder of the capacitor and to finish the array 10. For example, a capacitor dielectric layer is provided over the storage electrodes 20. The dielectric layer is deposited with a thickness such that the capacitor openings are not completely filled. The dielectric layer preferably comprises an oxide-nitride-oxide (ONO) dielectric, although other materials are of course possible. A second conductive layer is then deposited over the dielectric layer. The second conductive layer is preferably composed of polysilicon. In addition to serving as the second or upper electrode of the capacitor, the second conductive layer also forms the interconnection lines between the second electrodes of the capacitors. The second electrode is the electrode of the capacitor that is connected to the reference voltage as discussed in connection with FIG. 1. In this manner, active areas 28 are also electrically isolated (without the influence of the gate). A damascene or other inter-metal backend process then completes the remaining circuit elements, thereby forming the DRAM of the preferred embodiments.

43. Referring now to FIGS. 9 through 15, a second embodiment of the capacitor storage electrode array 110 of the present invention is shown in FIG. 9. The capacitor storage electrode array 110 is comprised of a plurality of storage electrodes 120 associated with access field effect transistors (FETS) 22 on a semiconductor wafer 24. Each storage electrode 120 and its associated access FET 22 corresponds to a memory cell 126 suitable for use in a DRAM or other memory array.

44. The wafer 24 comprises a bulk semiconductor substrate having an electrically conductive diffusion region 28, with word lines 30, and bit lines (not shown) formed therein, as can be seen by referring to FIG. 9. The structure shown in FIG. 9 is also a buried bit line structure, in which the capacitor storage electrode array 110 is formed over the bit lines.

45. Each storage electrode 120 is connected to diffusion regions 28 via a polysilicon plug 34, and to the bit line via a polysilicon plug 42. The storage electrodes 120 comprise conductive polysilicon runners 136, optionally coated with a layer of hemispherical-grain (HSG) polysilicon 38 or other conductive material. Oxide layers 44, 46 serve to insulate active regions of the cell 126 from each other, and insulation layer 48 isolates the storage electrode 120 from the underlying active regions. The storage electrodes 120 are arranged in complementary pairs 140 arranged parallel to one another, as can best be seen in FIG. 9. Each complementary pair 140 of storage electrodes 120 relates to two cells 126, 126′, with the storage electrode 120 of each cell extending over that cell's access FET 22 to partially or completely cover the access FET 22′ of the complementary cell as well. Each storage electrode 120 comprises one runner 136, 136′, optionally coated with HSG polysilicon 38, as shown in FIG. 9, resulting in a storage electrode 120 having a rectangular cross section.

46.FIG. 9 depicts a storage electrode array 110 in which the storage electrodes 120 extend over the length of the related pair of cells. Each storage electrode has a perimeter of at least about 17F, where F is the minimum feature size. The storage electrodes 120 of FIG. 9 may be seen to cross over four word lines. An alternative structure (not shown) may be formed in which the storage electrodes of each cell extend only partially over the complementary cell, providing each storage electrode with a perimeter of between 12and 15F, where F is the minimum feature size. The alternative storage electrodes cross over at least three, but less than four word lines.

47. The capacitor storage electrode array 110 is manufactured through a process described as follows, and illustrated by FIGS. 10 through 15. The process begins at a point in the DRAM manufacturing sequence that follows formation of field effect transistors, diffusion regions, word lines and bit lines on a semiconductor wafer 24.

48. As seen in FIG. 10, formation of the storage electrode array 110 begins with deposition and subsequent etching of a conductive layer (not shown) to form a first set of runners 136 on top of the wafer 24. The conductive layer may comprise any conductive material such as patterned polysilicon, amorphous silicon, polysilicon, or the like, but is preferably polysilicon.

49. Sacrificial spacers 162 are then formed of silicon oxide or silicon nitride (Si3N4) on the sides of the first set of runners 136, as shown in FIG. 11. If silicon oxide is used, it may be deposited by CVD or grown, and if silicon nitride is used, it is first deposited by CVD and then subsequently directionally etched to remove it from the horizontal surfaces of the wafer 24.

50. Referring to FIG. 12, a silicon layer is then deposited over the surface of the wafer 24 and subsequently etched to form a second set of runners 136′ on top of the wafer 24 and in between and parallel to the sacrificial spacers 162. The sacrificial spacers 162 are then removed by a selective etching process, leaving the structure as shown in FIG. 13. Alternatively, a sacrificial molding layer technique as described for the first embodiment may be used to form the sets of runners 136, 136′ in place of the process described above.

51. Referring now to FIG. 14, a conductive layer 38 is then optionally deposited or formed on the inner and outer surfaces of the first and second sets of runners 136, 136′. The conductive layer 38 may be formed of polysilicon, hemispherical-grain (HSG) polysilicon, titanium nitride, or the like, but is preferably HSG polysilicon. The HSG polysilicon layer 38 may be formed by low pressure chemical vapor deposition (LPCVD) of polysilicon under controlled pressure and temperature so that nucleation occurs. Deposition of HSG polysilicon may be carried out in helium-diluted SiH4 gas at 1.0 torr pressure and 550°C.

52. The thickness of the HSG polysilicon layer 38 is preferably less than one-half of the distance between each runner of the first set of runners 136 and each runner of the second set of runners 136′. Etch-back of the HSG polysilicon layer 38 is then performed by reactive ion etching using HBr gas without any etching masks, or by another suitable process. The resultant structure is shown in FIG. 14. Alternatively, without the optional HSG deposition, the process may proceed directly from FIG. 13 to FIG. 15, discussed below.

53. Referring now to FIG. 15, the first and second sets of runners 136, 136′ are then formed into individual storage electrodes 120. A resist and mask are applied, and a directional etching process such as RIE is used to separate the runners 136, 136′ into storage electrodes 120, as shown in FIG. 15. Well established processing techniques, including deposition of a capacitor dielectric layer and a top electrode, are then performed to construct the remainder of the capacitors and to complete the array.

54. The above description and drawings illustrate preferred embodiments which achieve the objects, features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6967134 *Jan 8, 2003Nov 22, 2005Micron Technology, Inc.Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructions
US7012294Aug 12, 2005Mar 14, 2006Micron Technology, Inc.Semiconductor constructions
US7244648Mar 13, 2006Jul 17, 2007Micron Technology, Inc.Methods of forming semiconductor constructions
US7459362 *Jun 27, 2005Dec 2, 2008Micron Technology, Inc.Methods of forming DRAM arrays
US7573088 *Apr 2, 2007Aug 11, 2009Micron Technology, Inc.DRAM array and electronic system
US7695756 *Apr 29, 2004Apr 13, 2010Zettacore, Inc.Systems, tools and methods for production of molecular memory
US7799598Mar 14, 2008Sep 21, 2010Zettacore, Inc.Processing systems and methods for molecular memory
US8058126Feb 4, 2009Nov 15, 2011Micron Technology, Inc.Semiconductor devices and structures including at least partially formed container capacitors and methods of forming the same
US8692305Nov 1, 2011Apr 8, 2014Micron Technology, Inc.Semiconductor devices and structures including at least partially formed container capacitors
US8742542 *Mar 27, 2013Jun 3, 2014Semiconductor Manufacturing International (Shanghai) CorporationMethod and device for a dram capacitor having low depletion ratio
US20130207233 *Mar 27, 2013Aug 15, 2013Semiconductor Manufacturing International (Shanghai) CorporationMethod and device for a dram capacitor having low depletion ratio
WO2008087498A1 *Jan 17, 2007Jul 24, 2008St Microelectronics Crolles 2Dram stacked capacitor and its manufacturing method using cmp
Classifications
U.S. Classification438/256, 257/E21.648, 257/E21.018, 257/E27.089, 257/E21.008, 257/E21.019, 438/258, 257/E21.013, 257/E21.012
International ClassificationH01L21/02, H01L27/108, H01L21/8242
Cooperative ClassificationH01L28/40, H01L27/10852, H01L28/82, H01L28/91, H01L28/84, H01L28/90, H01L27/10817
European ClassificationH01L27/108M4B2, H01L28/84, H01L28/82, H01L28/40, H01L28/91, H01L27/108F2M
Legal Events
DateCodeEventDescription
Sep 9, 2014ASAssignment
Effective date: 20140611
Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA
Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367
Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA
Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367
Effective date: 20140611
Sep 3, 2014ASAssignment
Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096
Effective date: 20140820
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,
Aug 7, 2014ASAssignment
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,
Effective date: 20140611
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344
Owner name: CONVERSANT IP N.B. 868 INC., CANADA
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344
Effective date: 20140611
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344
Owner name: CONVERSANT IP N.B. 276 INC., CANADA
Effective date: 20140611
Mar 13, 2014ASAssignment
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,
Effective date: 20140101
Free format text: CHANGE OF NAME;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:032439/0638
Sep 13, 2013FPAYFee payment
Year of fee payment: 12
Jan 10, 2012ASAssignment
Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196
Effective date: 20111223
Owner name: ROYAL BANK OF CANADA, CANADA
Oct 29, 2009ASAssignment
Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023438/0614
Effective date: 20090609
Sep 4, 2009FPAYFee payment
Year of fee payment: 8
Sep 23, 2005FPAYFee payment
Year of fee payment: 4