US 20010001860 A1 Abstract A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of selecting weights and thresholds for logic gates. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier that is a function of the weighted sum.
Claims(69) 1. A circuit for deriving an adder output bit from adder input bits, comprising:
first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of said adder input bits; and combinatorial logic that generates said adder output bit from said intermediate bits. 2. The circuit as recited in claim 1 a carry out bit,
a carry-generate bit, and
a carry-propagate bit.
3. The circuit as recited in claim 1 a carry in bit,
first and second addend and augend bits,
first and second carry-generate bits, and
first and second carry-propagate bits.
4. The circuit as recited in claim 1 5. The circuit as recited in claim 1 6. The circuit as recited in claim 1 7. The circuit as recited in claim 1 8. The circuit as recited in claim 1 9. The circuit as recited in claim 1 a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at said at least two binary inputs; and
a quantizer, coupled to said summer, that generates an output binary digit at a binary output thereof that is a function of said weighted sum.
10. The circuit as recited in claim 9 11. The circuit as recited in claim 9 a current source capable of producing a substantially constant electrical current corresponding to a particular discrete weight; and
a switch, coupled to said current source, that switches said electrical current as a function of a corresponding particular input binary digit.
12. The circuit as recited in claim 9 13. The circuit as recited in claim 1 14. A method of deriving an adder output bit from adder input bits, comprising:
generating intermediate bits based on threshold comparisons of concatenations of said adder input bits; and generating said adder output bit from said intermediate bits. 15. The method as recited in claim 14 a carry out bit,
a carry-generate bit, and
a carry-propagate bit.
16. The method as recited in claim 14 a carry in bit,
first and second addend and augend bits,
first and second carry-generate bits, and
first and second carry-propagate bits.
17. The method as recited in claim 14 18. The method as recited in claim 14 19. The method as recited in claim 14 20. The method as recited in claim 14 21. The method as recited in claim 14 22. The method as recited in claim 14 generating a weighted sum of input binary digits presented at said at least two binary inputs; and
generating an output binary digit at a binary output thereof that is a function of said weighted sum.
23. The method as recited in claim 22 24. The method as recited in claim 22 a current source capable of producing a substantially constant electrical current corresponding to a particular discrete weight; and
a switch, coupled to said current source, that switches said electrical current as a function of a corresponding particular input binary digit.
25. The method as recited in claim 22 26. A circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, comprising:
a first logic gate that generates a first intermediate bit based on a comparison between a concatenation of said second addend and augend bits and zero; a second logic gate that generates a second intermediate bit based on a comparison between said concatenation of said second addend and augend bits and two; a third logic gate that generates a third intermediate bit based on a comparison between a concatenation of said first addend and augend bits and said carry in bit and four; a first OR gate that generates a fourth intermediate bit based on said first addend and augend bits; a first AND gate that generates a fifth intermediate bit based on said first addend and augend bits; a second AND gate that generates a sixth intermediate bit based on said first and third intermediate bits; a third AND gate that generates a seventh intermediate bit based on said second and fourth intermediate bits; and a second OR gate that generates said carry out bit based on said sixth, seventh and fifth intermediate bits. 27. The circuit as recited in claim 26 a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at said at least two binary inputs; and
a quantizer, coupled to said summer, that generates an output binary digit at a binary output thereof that is a function of said weighted sum.
28. A multiplier circuit, comprising a summer having at least two inputs with corresponding weights, said inputs corresponding to bits of a multiplicand, said weights based on a multiplier, said summer generating a weighted sum of said multiplicand that represents a multiplication of said multiplicand and said multiplier. 29. The multiplier as recited in claim 28 30. The multiplier as recited in claim 28 31. The multiplier as recited in claim 28 32. The multiplier as recited in claim 28 a current source capable of producing a substantially constant electrical current corresponding to a particular weight; and
a switch, coupled to said current source, that switches said electrical current as a function of a corresponding particular bits of said multiplicand.
33. A method of multiplying a multiplicand by a multiplier, comprising generating a weighted sum of said multiplicand with a summer having at least two inputs with corresponding weights, said inputs corresponding to bits of said multiplicand, said weights based on a multiplier; and
generating an output representing a multiplication of said multiplicand and said multiplier that is a function of said weighted sum. 34. The method as recited in claim 33 35. The method as recited in claim 33 36. The method as recited in claim 33 37. The method as recited in claim 33 a current source capable of producing a substantially constant electrical current corresponding to a particular weight; and
a switch, coupled to said current source, that switches said electrical current as a function of a corresponding particular bits of said multiplicand.
38. A microprocessor, comprising:
a cache memory; and an arithmetic and logic unit containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, and
combinatorial logic that generates said carry out bit from said intermediate bits.
39. The microprocessor as recited in claim 38 40. The microprocessor as recited in claim 38 41. The microprocessor as recited in claim 38 42. The microprocessor as recited in claim 38 43. The microprocessor as recited in claim 38 44. The microprocessor as recited in claim 38 a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at said at least two binary inputs; and
a quantizer, coupled to said summer, that generates an output binary digit at a binary output thereof that is a function of said weighted sum.
45. The microprocessor as recited in claim 44 46. The microprocessor as recited in claim 44 a current source capable of producing a substantially constant electrical current corresponding to a particular discrete weight; and
a switch, coupled to said current source, that switches said electrical current as a function of a corresponding particular input binary digit.
47. The microprocessor as recited in claim 44 48. The microprocessor as recited in claim 38 49. A digital signal processor, comprising:
a signal input; a signal output; and a signal transformation unit containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, and
combinatorial logic that generates said carry out bit from said intermediate bits.
50. The DSP as recited in claim 49 51. The DSP as recited in claim 49 52. The DSP as recited in claim 49 53. The DSP as recited in claim 49 54. The DSP as recited in claim 49 55. The DSP as recited in claim 49 56. The DSP as recited in claim 55 57. The DSP as recited in claim 55 58. The DSP as recited in claim 55 59. The DSP as recited in claim 55 60. A logic gate, comprising:
first, second and third current paths having preset current magnitudes representing discrete weights; first, second and third switches coupled to said first, second and third current paths, respectively, and adapted to receive binary digits to open or close said first, second and third switches; and a quantizer, coupled to said first, second and third switches, that receives an electrical current that is a function of a value of said discrete weights and said binary digits, said electrical current representing a result of an operation with respect to said binary digits. 61. The logic gate as recited in claim 60 a current source, and
a current sink.
62. The logic gate as recited in claim 60 a current source, and
a current sink.
63. The logic gate as recited in claim 60 a current source, and
a current sink.
64. The logic gate as recited in claim 60 65. A processor containing the logic gate as recited in claim 60 66. A DSP containing the logic gate as recited in claim 60 67. A method of selecting weights and a threshold value for a threshold gate having a given fan-in (A), comprising:
solving
for v _{Δ/2}; for w _{Δ/2}; solving t _{Δ+2}; =-π_{Δ/2 }for t_{Δ+2}, wherein w_{0 }=0, v_{0}=1, w_{1}=1 and v_{1}=2; and employing said v _{Δ/2 }and said w_{Δ/2 }as said weights and said t_{Δ-2 }as said threshold value in said threshold gate. 68. The method as recited in claim 67 _{Δ/2 }and said w_{Δ/2 }are of minimum value. 69. The method as recited in claim 67 _{Δ+2 }is of minimum value. Description [0001] The present invention is directed, in general, to adder and multiplier circuits and, more specifically, to adder and multiplier circuits employing logic gates having discrete, weighted inputs, combinations of the same, methods of performing combinatorial operations with such logic gates and combinations thereof. [0002] Digital systems are used extensively in computation and data processing, controls, communications and measurement. Digital systems use digital signals that may only assume discrete values. Typically, digital systems use binary signals that employ only two values. Since such systems only use two distinct values, errors caused by component variations are minimized. As a result, a digital system may be designed such that, for a given input, an output thereof is exactly correct and repeatable. This gives rise to the extreme accuracy for which digital systems are well known. [0003] Analog systems, on the other hand, use analog signals that vary continuously over a specified range. Analog systems are thus particularly vulnerable to error, depending on the accuracy of the components used therein. Since digital systems are generally capable of greater accuracy and reliability than analog systems, many tasks formerly performed by analog systems are now performed exclusively by digital systems. [0004] A digital system, such as a computer, typically includes an input device, an output device, a processor or central processing unit (CPU) and a data storage device (e.g., random access memory or hard disk). A CPU typically contains an arithmetic/logic unit (ALU) that performs arithmetic functions (e.g., add, subtract, multiply and divide) and logic functions (e.g., AND, OR and NOT). Additionally, a CPU may also contain a floating point unit (FPU) that performs floating point operations (e.g., add, subtract, multiply and divide). [0005] One basic building block of digital systems is a logic gate. Conventional logic gates have one output and one or more inputs. The number of inputs is called the fan-in of the gate. The state of the output is completely determined by the state(s) of the input(s). [0006] Logical and arithmetic functions are typically performed by a number of logic gates coupled together to form a multi-layer network. The maximum number of gates cascaded in series between the input and the output of such a network is typically referred to as the number of layers of gates. Designers are concerned with the number of layers in a network for several reasons. In some applications, increasing the number of layers may reduce the required number of gates and gate inputs (i.e., fan-in), thus reducing the cost (which may be expressed in terms of integrated circuit area) of building the network. Of course, cascading a large number of gates together may result in unacceptable input-output delays and data dependency conditions. When the input of a gate is switched, a finite time elapses before the output of the gate changes. If a large number of gates are cascaded together to form a network, the time between an input change and a corresponding change in the network output may become excessive, thereby slowing down the operation of the network. [0007] Arithmetic functions are particularly susceptible to the effects of cascaded gates. The serial solution for binary addition is given here as an example. Initially, a first augend bit and a first addend bit are added together, to produce a first sum bit and a first carry bit. The first carry bit is then added to the second augend and addend bits to produce the second sum and carry bits. Since the second sum bit is dependent on the value of the first carry bit, the second sum bit cannot be computed before the first carry bit is computed. While each input-output delay is small, the cumulative input-output delay perceived when adding large numbers, due to the propagation of the carry bit, is proportional to the number of bits added, and may be prohibitive. Techniques (e.g., carry look-ahead, conditional sum or prefix computation have been developed for reducing the delay to a logarithmic function of the number of input bits to be added. The number of Boolean gates (e.g., AND, OR or NOT) used by such techniques is in the range of from 8n to 35n or 2n log(n) to 3n log(n), where n is the number of bits to be added and the logarithms are base two. [0008] Increasing processing power is a continuing goal in the development of microprocessors. Microprocessor designers are generally familiar with three ways to increase the processing power of a CPU. The CPU's clock frequency may be increased so that the CPU can perform a greater number of operations in a given time period. Microprocessors are designed to operate at increasingly high clock frequencies. For instance, the 8080 (introduced in 1974 by the Intel Corporation) was designed to operate at about 2 to 3 MHZ. Today, Intel's Pentium II line of processors are designed to operate with clock frequencies over 300 MHZ. While a higher clock frequency generally results in increased processing power, the higher clock frequency also increases power dissipation, resulting in higher device operating temperatures. Microprocessor designers, therefore, must address these additional problems to avoid catastrophic device failures. [0009] Another way to increase processing power is to increase input and output data bus width, thereby allowing the CPU to process a greater amount of code and data. Early microprocessors were packaged using dual in-line packaging (DIP) technology. Increasing the width of the data buses was both expensive and unrealistic, often resulting in extremely large device packages. Today, with the use of pin grid array (PGA) packaging, increasing the size of the data buses no longer poses a packaging problem. Of course, a larger number of transistors is required to process the additional information conveyed by the wider data buses. [0010] Yet another way to increase processing power is to change the internal architecture of the microprocessor to overlap the execution of instructions by, for example, superscaling. This method also requires the addition of a large number of transistors, since entire processing stages or execution units must be duplicated. Performing a large number of instructions in parallel may also result in data dependency problems. [0011] Accordingly, what is needed in the art is new architectures for addition circuitry, multiplication circuitry and combinations of the same that increase the processing power of conventional digital systems. [0012] To address the above-discussed deficiencies of the prior art, the present invention provides a circuit and method for deriving an adder output bit (such as a carry out bit, a carry-generate bit or a carry-propagate bit) from adder input bits (such as a carry in bit, (at least) first and second addend and augend bits, (at least) first and second carry-generate bits or (at least) first and second carry-propagate bits. The present invention further provides a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of generating weights for logic gates. [0013] In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. Circuits may be coupled to one another in layers to yield a wider adder. In such configuration, addend and augend bits are transformed into carry-generate and carry-propagate bits, which are ultimately transformed into a carry out bit. [0014] The present invention introduces novel digital addition and multiplication circuits that take advantage of multiple discrete logic levels to perform respective addition and multiplication operations significantly faster than prior art adders and multipliers. Of course, the principles of the present invention extend to cover logic gates that process more than two adder input bits concurrently. [0015] In one embodiment of the present invention, the first logic gate generates a first intermediate bit based on a comparison between a concatenation of ones of the adder input bits and zero. In a related embodiment of the present invention, the second logic gate generates a second intermediate bit based on a comparison between a concatenation of ones of the adder input bits and two. In another related embodiment of the present invention, the third logic gate generates a third intermediate bit based on a comparison between a concatenation of ones of the adder input bits and four. [0016] The first, second and third logic gates cooperate to provide the correct intermediate bits to the combinatorial circuitry based on the values of the various adder input bits. [0017] In one embodiment of the present invention, the combinatorial logic comprises first, second and third AND gates and first and second OR gates coupled to outputs thereof. In an embodiment of the invention to be illustrated and described, the combinatorial logic generates the adder output bit by additionally employing the ones of the adder input bits. [0018] In one embodiment of the present invention, each of the first, second and third logic gates includes: (1) a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at the at least two binary inputs and (2) a quantizer, coupled to the summer, that generates an output binary digit at a binary output thereof that is a function of the weighted sum. In this embodiment, the logic gates employ an internal representation having more than two logic levels to perform combinatorial operations, but nonetheless have purely binary inputs and outputs. The binary inputs and outputs ensure that the logic gates can be employed in an otherwise conventional binary digital architecture without requiring the architecture to be modified apart from insertion of the logic gates or circuits that employ the logic gates in combination with more conventional gates, e.g., Boolean gates. [0019] In one embodiment of the present invention, the discrete weights are integer multiples of a predetermined number. The predetermined number may be 1, allowing the discrete weights to assume integer values. Of course, the predetermined number may be any suitable number. [0020] In one embodiment of the present invention, each of the at least two binary inputs includes: (1) a current source capable of producing a substantially constant electrical current corresponding to a particular discrete weight and (2) a switch, coupled to the current source, that switches the electrical current as a function of a corresponding particular input binary digit. The current source may be derived from a voltage source by way of a resistance. The voltage source may be provided by a power supply that provides power to other logic circuitry (such as other microprocessor circuitry) that may surround, and interact with, the logic gate. For purposes of the present invention, substantially constant electrical current is defined to be sufficiently constant such that the accuracy of the logic gate is not adversely affected. The level of precision required of the current is or can be a function of the range of discrete integer weights employed in the logic gate. [0021] In one embodiment of the present invention, the circuit further includes a threshold input that provides a threshold number to the quantizer, the output binary digit being a function of a relationship between the weighted sum and the threshold number. The threshold number provides a bias to the quantizer, allowing a threshold between the binary output states to assume a value other than zero. In an embodiment to be illustrated and described, the discrete weights are advantageously selected to minimize (ideally to zero) the threshold number. This has the advantage of minimizing the number or size of current sources or sinks and thus potentially reducing the area (and therefore the cost) of the logic gate. [0022] In one embodiment of the present invention, the corresponding discrete weights are provided by a selected one of: (1) current sources and (2) current sinks. The current sources may be made to correspond to positive discrete weights and the current sinks may be made to correspond to negative discrete weights, such that currents are added and subtracted in the summer to obtain the desired weighted sum. In this way, the logic gates of the present invention can be adapted to operate with respect to discrete weights of either positive or negative sign or a combination thereof. [0023] In one embodiment of the present invention, the minimum integer weights and thresholds determining the threshold gates of arbitrary fan-ins able to compute the group carry-generate bit from multiple carry-generate and carry-propagate bits are also presented together with the method of determining them for gates of arbitrary fan-ins (larger than two). [0024] In one embodiment of the present invention, the circuit further includes a plurality of other of the circuits coupled together to form a multiplier circuit. Those skilled in the art will readily perceive other highly advantageous applications for the logic gates of the present invention. The present invention fully encompasses all applications. [0025] The present invention further provides a multiplier circuit, including a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand. The weighted sum represents the result of a multiplication of the multiplier and the multiplicand and is analog in nature. A digital equivalent of the weighted sum may be derived by either successive comparisons with known analog levels (thereby producing a succession of result bits) or by converting the analog weighted sum to a digital number in an analog-to-digital (A/D) converter. The weights are preferably created by bit-shifting the multiplier. A bias may also be applied to the multiplier circuit to accommodate equations of the type: AxB+C; called inner product or multiply accumulate. [0026] The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. [0027] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0028]FIG. 1 illustrates an embodiment of a logic gate constructed according to the principles of the present invention; [0029]FIG. 2 illustrates an embodiment of a carry bit generating circuit constructed according to the present invention; [0030]FIGS. 3A, 3B and [0031]FIGS. 4A, 4B and [0032]FIG. 5 illustrates an embodiment of a portion of a multiplier circuit constructed according to the present invention; [0033]FIG. 6 illustrates a microprocessor employing the gate of FIGS. 1, 3A, [0034]FIG. 7 illustrates a digital signal processor (DSP) employing the gate of FIGS. 1, 3A, [0035] Referring initially to FIG. 1, illustrated is an embodiment of a logic gate [0036] In the illustrated embodiment, the logic gate [0037] In the illustrated embodiment, the first and second binary inputs [0038] In the illustrated embodiment, with the first and second discrete weights [0039] The logic gate [0040] Of course, the threshold number may be modified as required by changing the threshold input. For example, the threshold number may be set at 1.5 to enable the logic gate [0041] Turning now to FIG. 2, illustrated is an embodiment of a carry bit generating circuit, generally designated [0042] The carry bit generating circuit [0043] The illustrated embodiment of the carry bit generating circuit [0044] The carry bit generating circuit further includes a second logic gate [0045] The carry bit generating circuit [0046] The carry bit generating circuit [0047] The carry bit generating circuit [0048] The carry bit generating circuit [0049] The carry bit generating circuit [0050] Finally, the carry bit generating circuit [0051] Those skilled in the art will note two aspects of the carry bit generating circuit [0052] The following discussion introduces carry-generate and carry-propagate bits as employed in certain adders. Those skilled in the art will understand such bits. However, for a greater understanding of their derivation, see V. Beiu and J. Taylor, [0053] At this point, it is instructive to set forth a method for obtaining the weights to be employed in a given logic gate, such as the logic gate [0054] wherein w [0055] Turning now to FIGS. 3A, 3B and [0056] In FIG. 3A, the gate [0057] In FIG. 3B, the gate [0058] In FIG. 3C, the gate [0059] Those skilled in the art will perceive an advantage to having weights and threshold values as small as possible. Accordingly, FIGS. 4A, 4B and [0060] In FIG. 4B, the gate [0061] In FIG. 4C, the gate [0062] Turning now to FIG. 5, illustrated is an embodiment of a portion of a multiplier circuit, generally designated [0063] Each of the at least two inputs [0064] From this point, the multiplier circuit [0065] The quantizer [0066]FIG. 5 further illustrates a further input [0067] Turning now to FIG. 6, illustrated is a microprocessor [0068] The ALU includes either or both of an adder [0069] Turning now to FIG. 7, illustrated is a digital signal processor (DSP) [0070] Interposed between the signal input [0071] From the above, it is apparent that the present invention provides a circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying and a microprocessor and DSP employing the circuit or the method. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier. [0072] Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form. Referenced by
Classifications
Rotate |