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Publication numberUS20010002068 A1
Publication typeApplication
Application numberUS 09/738,915
Publication dateMay 31, 2001
Filing dateDec 14, 2000
Priority dateMar 22, 1999
Also published asUS6222280, US6437451
Publication number09738915, 738915, US 2001/0002068 A1, US 2001/002068 A1, US 20010002068 A1, US 20010002068A1, US 2001002068 A1, US 2001002068A1, US-A1-20010002068, US-A1-2001002068, US2001/0002068A1, US2001/002068A1, US20010002068 A1, US20010002068A1, US2001002068 A1, US2001002068A1
InventorsWarren Farnworth, Salman Akram
Original AssigneeFarnworth Warren M., Salman Akram
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Test interconnect for semiconductor components having bumped and planar contacts
US 20010002068 A1
Abstract
An interconnect for testing semiconductor components having both bumped contacts, and planar contacts, is provided. The interconnect includes: a substrate, first contacts on the substrate for electrically engaging the bumped contacts, and second contacts on the substrate for electrically engaging the planar contacts. In illustrative embodiments the first contacts include recesses in the substrate covered with a conductive layer, or recesses formed in a compliant layer on the substrate, or conductive polymer donuts sized and shaped to retain the bumped contacts. In illustrative embodiments the second contacts include etched pillars having penetrating projections, or conductive polymer bumps having penetrating particles, or flat topped projections having a compliant layer thereon. The interconnect can be used to construct a die level test carrier for testing components in singulated form, or to construct a wafer level test carrier for testing components in wafer or panel form.
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Claims(42)
What is claimed is:
1. An interconnect for a semiconductor component comprising:
a substrate;
a first contact comprising a recess on the substrate at least partially covered with a conductive layer, the recess configured to retain and electrically engage a bumped contact on the component; and
a second contact comprising a projection on the substrate sized and shaped to engage a planar contact on the component as the first contact electrically engages the bumped contact.
2. The interconnect of
claim 1
wherein the substrate comprises a polymer layer wherein the recess is formed.
3. The interconnect of
claim 1
wherein the recess comprises a conductive polymer donut on the substrate.
4. The interconnect of
claim 1
wherein the second contact comprise a conductive polymer comprising metal particles for penetrating the planar contact.
5. The interconnect of
claim 1
wherein the recess comprises a stepped surface.
6. An interconnect for a semiconductor component comprising:
a substrate;
a first contact comprising a recess on the substrate at least partially covered with a conductive layer, the recess configured to retain and electrically engage a bumped contact on the component; and
a second contact comprising a projection on the substrate configured to engage a planar contact on the component, the projection having a height selected to space the component from the substrate to prevent deformation of the bumped contact during electrical engagement by the first contact.
7. The interconnect of
claim 6
wherein the projection has a planar tip portion configured to support and prevent tilting of the component during electrical engagement of the bumped contact.
8. An interconnect for a semiconductor component comprising:
a substrate;
a first contact comprising a recess on the substrate at least partially covered with a conductive layer, the recess configured to retain and electrically engage a bumped contact on the component; and
a second contact comprising a conductive polymer projection on the substrate configured to electrically engage a planar contact on the component, the projection comprising a plurality of particles therein configured to penetrate the planar contact.
9. The interconnect of
claim 8
wherein the second contact further comprises a contact pad on the substrate comprising a non-oxidizing metal.
10. The interconnect of
claim 8
wherein the conductive polymer projection comprises a material selected from the group consisting of anisotropic conductive adhesives and metal filled silicone.
11. An interconnect for a semiconductor component comprising:
a substrate;
a first contact comprising a conductive polymer donut on the substrate configured to retain and electrically engage a bumped contact on the component; and
a second contact comprising a projection on the substrate configured to engage a planar contact on the component as the first contact electrically engages the bumped contact.
12. The interconnect of
claim 11
wherein the conductive polymer donut includes a plurality of particles for penetrating the bumped contact.
13. The interconnect of
claim 11
wherein the conductive polymer donut comprises a contact pad on the substrate comprising a non-oxidizing metal.
14. An interconnect for a semiconductor component comprising:
a substrate;
a first contact on the substrate configured to electrically engage a bumped contact on the component; and
a second contact comprising a projection on the substrate having a planar tip portion with a polymer layer thereon configured to support the component during electrical engagement of the bumped contact by the first contact.
15. The interconnect of
claim 14
wherein the component comprises a plurality of bumped contacts located along a center line thereof and the interconnect comprises at least two second contacts configured to support the component on either side of the bumped contacts.
16. The interconnect of
claim 14
wherein the polymer layer comprises a material selected from the group consisting of polyimide, silicone, and butyl rubber.
17. The interconnect of
claim 14
wherein the substrate comprises silicon and the second contact comprises silicon.
18. An interconnect for a semiconductor component comprising:
a substrate;
a first contact comprising a recess on the substrate at least partially covered with a conductive layer, the recess configured to retain and electrically engage a bumped contact on the component;
a second contact comprising a projection on the substrate configured to engage a planar contact on the component as the first contact electrically engages the bumped contact; and
an alignment member on the substrate having a first alignment opening configured to contact a peripheral edge of the component and a second alignment opening aligned with the recess configured to guide the bumped contact onto the first contact.
19. The interconnect of
claim 18
wherein the alignment member comprises a photoimageable polymer.
20. The interconnect of
claim 18
wherein the first contact comprises a conductive polymer donut.
21. The interconnect of
claim 18
wherein the second contact comprises a conductive polymer having dendritic metal particles for penetrating the planar contact.
22. The interconnect of
claim 18
wherein the recess comprises a stepped surface.
23. A carrier for testing a semiconductor component comprising:
a base configured to hold the component;
an interconnect on the base comprising a first contact configured to retain and electrically engage a bumped contact on the component and a second contact comprising a projection configured to engage a planar contact on the component as the first contact electrically engages the bumped contact; and
a force applying mechanism for biasing the component against the interconnect.
24. The carrier of
claim 23
further comprising an alignment member on the interconnect for aligning the component to the interconnect.
25. The carrier of
claim 23
wherein the first contact comprises a conductive polymer donut.
26. The carrier of
claim 23
wherein the second contact comprises a conductive polymer having conductive particles therein.
27. The carrier of
claim 23
wherein the component comprises an element selected from the group consisting of bare dice and chip scale packages.
28. The carrier of
claim 23
wherein the component comprises a semiconductor wafer.
29. A carrier for testing a semiconductor component comprising:
a base configured to hold the component;
an interconnect on the base comprising:
a plurality of first contacts configured to electrically engage a plurality of bumped contacts on the component; and
a second contact comprising a projection configured to engage a planar contact on the component and to support the component during electrical engagement of the bumped contacts by the first contacts; and
a force applying mechanism for biasing the component against the interconnect.
30. The carrier of
claim 29
wherein the bumped contacts are located along a center line of the component and the interconnect comprises at least two second contacts configured to engage planar contacts on either side of the bumped contacts.
31. The carrier of
claim 29
further comprising an alignment member on the interconnect for aligning the component to the interconnect.
32. A carrier for testing a semiconductor component comprising:
a base for retaining the component;
an interconnect on the base for electrically connecting the component to a test circuit, the interconnect comprising:
a substrate;
a first contact comprising a conductive polymer donut on the substrate configured to retain and electrically engage a bumped contact on the component; and
a second contact comprising a projection on the substrate configured to engage a planar contact on the component as the first contact electrically engages the bumped contact.
33. The carrier of
claim 32
wherein the conductive polymer donut comprises a plurality of metal particles for penetrating the bumped contact.
34. The carrier of
claim 32
wherein the second contact comprises a conductive polymer.
35. A system for testing a semiconductor component comprising:
test circuitry for applying test signals to the component; and
a carrier for holding the component in electrical communication with the test circuitry, the carrier comprising an interconnect comprising a first contact for electrically engaging a bumped contact on the component and a second contact for engaging a planar contact on the component, the second contact having a height selected to space the component from the interconnect to prevent deformation of the bumped contact.
36. The system of
claim 35
wherein the carrier further comprises an alignment member for aligning the component to the interconnect.
37. The system of
claim 35
wherein the interconnect comprises a polymer alignment member having a first alignment opening for contacting a peripheral edge of the component and a second alignment opening aligned with the first contact for aligning the bumped contact to the first contact.
38. A system for testing a semiconductor component comprising:
test circuitry for applying test signals to the component; and
a carrier for holding the component in electrical communication with the test circuitry, the carrier comprising:
a base;
an interconnect on the base comprising:
a substrate;
a first contact comprising a recess on the substrate at least partially covered with a conductive layer, the recess configured to retain and electrically engage a bumped contact on the component; and
a second contact comprising a projection on the substrate configured to engage a planar contact on the component, the projection having a planar surface for supporting the component to prevent tilting thereof during electrical engagement of the bumped contact by the first contact; and
a force applying mechanism for biasing the component against the interconnect.
39. The system of
claim 38
wherein the interconnect further comprises an alignment member on the substrate having a first alignment opening configured to contact a peripheral edge of the component and a second alignment opening aligned with the recess configured to guide the bumped contact onto the first contact.
40. The system of
claim 38
wherein the recess comprises a conductive polymer donut.
41. The system of
claim 38
wherein the second contact comprises a conductive polymer.
42. The system of
claim 38
wherein the recess comprises a stepped surface.
Description
FIELD OF THE INVENTION

[0001] This invention relates generally to the manufacture and testing of semiconductor components. More particularly, this invention relates to an interconnect for electrically engaging semiconductor components having both bumped, and planar, terminal contacts.

BACKGROUND OF THE INVENTION

[0002] Semiconductor components, such as bare dice, chip scale packages, BGA devices and wafers can include bumped contacts. For example, bumped contacts, such as solder balls, allow a component to be surface mounted to a mating substrate (e.g., PCB) using a solder reflow process. This type of component is sometimes referred to as a “bumped” component (e.g., bumped die, bumped wafer). Semiconductor components can also include planar contacts. For example, components can include planar land pads, or planar bond pads.

[0003] For testing the integrated circuits contained on semiconductor components it is necessary to make temporary electrical connections with the bumped contacts, or with the planar contacts. Different types of interconnects have been developed for making these temporary electrical connections. For example, a wafer probe card is one type of interconnect that is used to test semiconductor wafers. Another type of interconnect, is contained within a carrier for temporarily packaging singulated components, such as bare dice and chip scale packages, for test and burn-in. The interconnects include contacts that make the electrical connections with the terminal contacts on the components.

[0004] Sometimes a semiconductor component can include both bumped contacts, and planar contacts. For example, a chip scale package can include solder balls bonded to land pads. Some of the land pads may not include a solder ball. For testing this type of component a two step process must be utilized. In a first test step, electrical connections are made to the bumped contacts using a first interconnect constructed for bumped contacts. In a second test step, electrical connections are made to the planar contacts using a second interconnect constructed for planar contacts.

[0005] It would be desirable for a single interconnect to be able to accommodate both bumped contacts and planar contacts. This would simplify the test procedure, and the equipment associated with test processes. Such an interconnect must be able to compensate for the different surface topographies of the bumped contacts and the planar contacts. In particular, the bumped contacts are raised above the surface of the component, while the planar contacts are substantially planar to the surface of the component. In addition, the bumped contacts can have different sizes and heights, such that the bumped contacts are not all located along a common plane. Similarly planar contacts can vary in size, location and planarity on the component.

[0006] Another problem with making temporary electrical connections with a component occurs when the contacts are located along a center line of the component. In particular, the component can tilt if the contact pressure is not applied directly along the center line of the component to the component contacts. It would be desirable for an interconnect to be configured to prevent tilting of the component during electrical engagement of the contacts.

[0007] The present invention is directed to an interconnect for making temporary electrical connections with semiconductor components having both bumped contacts and planar contacts. The interconnect includes first contacts constructed to center and retain the bumped contacts, and to accommodate variations in the size and planarity of the bumped contacts. In addition, the interconnect includes second contacts constructed to electrically engage the planar contacts.

SUMMARY OF THE INVENTION

[0008] In accordance with the present invention, an improved interconnect for testing semiconductor components having both bumped contacts and planar contacts is provided. Also provided are a test carrier, and a test system incorporating the interconnect.

[0009] The interconnect, simply stated, comprises: a substrate, a plurality of first contacts on the substrate for electrically engaging the bumped contacts, and a plurality of second contacts on the substrate for electrically engaging the planar contacts. Different embodiments are provided for the interconnect contacts including compliant embodiments, able to cushion contact forces, and to compensate for variations in the size and planarity of the contacts on the components. Preferably, either the first contacts or the second contacts on the interconnect are provided in a compliant embodiment.

[0010] In an illustrative embodiment, the first contacts comprise recesses in the substrate at least partially covered with a conductive layer. The recesses are configured to retain and electrically engage the bumped contacts. In an alternate embodiment, the recesses are formed in a polymer layer deposited on the substrate, which allows flexure in a z-direction. In another alternate embodiment the first contacts comprise conductive polymer donuts formed on a surface of the substrate. The polymer donuts are sized and shaped to compliantly retain, and electrically engage the bumped contacts.

[0011] The second contacts comprise projections on the substrate configured to simultaneously engage the planar contacts during electrical engagement of the bumped contacts by the first contacts. In addition, the second contacts have a height selected to space the component from the interconnect such that the bumped contacts are not excessively deformed during electrical engagement by the first contacts.

[0012] In an illustrative embodiment, the second contacts include penetrating projections for penetrating the planar contacts to a limited penetration depth. In an alternate embodiment, the second contacts comprise conductive polymer bumps. In another alternate embodiment, the second contacts have a planar tip portion configured to support and prevent tilting of the component, during electrical engagement of the bumped contacts by the first contacts.

[0013] Suitable materials for forming the substrate include silicon, ceramic, and plastic. With the substrate comprising silicon both the first contacts and the second contacts can be formed integrally with the substrate using an etching process. In the compliant embodiments a conductive polymer material, such as a metal filled silicone, or an anisotropic adhesive can be used to form the interconnect contacts. Using conductive polymers, the interconnect contacts are naturally resilient to provide compliancy for cushioning contact forces, and for accommodating variations in the size and planarity of the component contacts. In addition, the resiliency of the conductive polymer allows the interconnect contacts to be compression loaded during test procedures, while conductive dendritic particles within the conductive polymer, penetrate oxide layers covering the component contacts. The compliant contacts can be formed by stenciling, screen printing, or otherwise depositing, a viscous conductive elastomeric material in a desired pattern, followed by partial curing, planarization and then total curing.

[0014] The die level carrier is configured to retain singulated semiconductor components, such as bare dice and packages, in electrical communication with test circuitry. The die level carrier includes: a base, the interconnect mounted to the base, and a force applying mechanism for biasing the component against the interconnect.

[0015] The wafer level carrier is configured to retain a wafer, or portion of a wafer, containing multiple semiconductor dice. Alternately the wafer level carrier can be configured to retain, a wafer, or a panel containing multiple semiconductor packages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1A is a bottom view of a semiconductor component having both bumped contacts and planar contacts;

[0017]FIG. 1B is an enlarged cross sectional view taken along section line 1B-1B of FIG. 1A illustrating a bumped contact on the component;

[0018]FIG. 1C is an enlarged cross sectional view taken along section line 1C-1C of FIG. 1A illustrating a planar contact on the component;

[0019]FIG. 2 is a schematic plan view of an interconnect constructed in accordance with the invention with the outline of the component superimposed thereon;

[0020]FIG. 3A is an enlarged cross sectional view taken along section line 3A-3A of FIG. 2 illustrating an interconnect contact configured to electrically engage a bumped contact on the component;

[0021]FIG. 3B is an enlarged cross sectional view equivalent to FIG. 3A illustrating an alternate embodiment interconnect contact formed on a compliant layer;

[0022]FIG. 3C is an enlarged cross sectional view equivalent to FIG. 3A illustrating an alternate embodiment interconnect contact in the form of a conductive polymer donut;

[0023]FIG. 3D is a cross sectional view taken along section line 3D-3D of FIG. 3C;

[0024]FIG. 3E is an enlarged cross sectional view equivalent to FIG. 3A illustrating an alternate embodiment interconnect contact in the form of a stepped recess;

[0025]FIG. 3F is an enlarged cross sectional view equivalent to FIG. 3A illustrating an alternate embodiment interconnect contact in the form of a concave recess;

[0026]FIG. 4A is an enlarged cross sectional view taken along section line 4A-4A of FIG. 2 illustrating an interconnect contact configured to electrically engage a planar contact on the component;

[0027]FIG. 4B is an enlarged cross sectional view equivalent to FIG. 4A illustrating an interconnect contact in the form of a conductive polymer bump;

[0028]FIG. 4C is a cross sectional view taken along section line 4C-4C of FIG. 4B;

[0029]FIG. 4D is an enlarged cross sectional view equivalent to FIG. 4A illustrating an interconnect contact engaging a dummy planar contact on the component;

[0030]FIG. 5A is a plan view of a test carrier incorporating an interconnect constructed in accordance with the invention;

[0031]FIG. 5B is a cross sectional view taken along section line 5B-5B of FIG. 5A;

[0032]FIG. 6A is a plan view of an alternate embodiment interconnect having a polymer alignment member;

[0033]FIG. 6B is a cross sectional view of the polymer alignment member taken along section line 6B-6B of FIG. 6A;

[0034]FIG. 6C is a cross sectional view of the polymer alignment member shown aligning the component;

[0035]FIG. 7A is a plan view of a wafer test carrier incorporating an interconnect constructed in accordance with the invention; and

[0036]FIG. 7B is an enlarged cross sectional view of the wafer test carrier taken along section line 7B-7B of FIG. 7A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0037] Referring to FIG. 1, a semiconductor component 10 that includes both bumped contacts 12 and planar contacts 14 is illustrated. As used herein, the term “semiconductor component” refers to an electronic component that includes a semiconductor die. Exemplary semiconductor components include bare semiconductor dice, chip scale packages, ceramic or plastic semiconductor packages, semiconductor wafers, BGA devices, and multi chip modules.

[0038] The bumped contacts 12 and the planar contacts 14 are in electrical communication with integrated circuits contained on the semiconductor component 10. The bumped contacts 12 and planar contacts 14 allow electrical access from the outside to the integrated circuits on the component 10. As shown in FIG. 1B, the bumped contacts 12 can comprise metal balls, such as solder balls, attached to pads 16 on the component 10. Alternately, rather than being balls, the bumped contacts 12 can have other shapes such as hemispheres, bumps, or cones. As shown in FIG. 1C, the planar contacts 14 comprise metal pads such as land pads, bond pads, or test pads formed on the component 10.

[0039] Referring to FIG. 2, an interconnect 18 constructed in accordance with the invention is illustrated. The interconnect 18 is adapted to establish temporary electrical connections with the component 10 for testing. The interconnect 18 includes a substrate 20; a plurality of first contacts 22 on the substrate 20 for electrically engaging the bumped contacts 12 on the component 10; and a plurality of second contacts 24 on the substrate for electrically engaging the planar contacts 14 on the component 10. The interconnect 18 also includes a plurality of conductors 26 on the substrate 20 in electrical communication with the first contacts 22 and the second contacts 24; and a plurality of input/output pads 28 on the substrate 20 in electrical communication with the conductors 26.

[0040] Referring to FIG. 3A, a first embodiment interconnect contact 22A is illustrated. The interconnect contact 22A comprises a recess 30 formed in the substrate 20A, that is sized and shaped to retain the bumped contact 12. The interconnect contact 22A also includes a conductive layer 32A at least partially covering the recess 30. The conductive layer 32A is in electrical communication with a conductor 26A, and with an input/output pad 28A on the substrate 20A. Peripheral edges 34A of the conductive layer 32A are adapted to penetrate the bumped contact 12 to pierce native oxide layers and contact the underlying metal.

[0041] In the first embodiment, the substrate 20A comprises silicon, which permits the interconnect contacts 22A, the conductive layers 32A, the conductors 26A and the input/output pads 28A to be made using semiconductor fabrication techniques (e.g., photolithography, etching, metallization). In addition, with silicon, a coefficient of thermal expansion (CTE) of the interconnect 18 substantially matches that of the component 10. However, the substrate 20A can also comprise ceramic, glass filled resin (e.g., FR-4), silicon-on-glass, or another semiconductor material such as gallium arsenide. With the substrate 20A comprising silicon, an electrically insulating layer 38A can be formed on exposed surfaces thereof for insulating the first contacts 22A, the conductors 26A, and the input/output pads 28A from a bulk of the substrate 20A. The electrically insulating layer 38A can comprise a grown or deposited oxide, such as SiO2, or a deposited polymer, such as polyimide.

[0042] Preferably, the conductive layers 32A and conductors 26A comprise a highly conductive metal such as copper, aluminum, titanium, tantalum, tungsten, molybdenum or alloys of these metals. The conductive layers 32A and conductors 26A can be formed as a single layer of metal, or as a multi metal stack, using a thin film metallization process (e.g., CVD, patterning, etching or electroplating). Alternately, a thick film metallization process (e.g., screen printing, stenciling) can be used to form the conductive layers 32A and conductors 26A.

[0043] The conductors 26A also include the input/output pads 28A located along the peripheral edges of the interconnect 18. Wires 36A are wire bonded to the input/output pads 28A to provide separate electrical paths from test circuitry to the conductors 26. Preferably the input/output pads 28A are located on recessed surfaces along the edges of the substrate 20A to provide clearance for the wires 36A. Alternately, rather than wire bonding wires 36A, TAB tape can be used to electrically connect the input/output pads 28A to the test circuitry.

[0044] The recess 30A for the first contacts 22A can be etched by forming a mask (not shown) on the substrate 20A, such as a photopatterned resist mask, and then etching the substrate 20A through openings in the mask, using an etchant. With the substrate 20A comprising silicon, a suitable etchant for performing the etch process comprises a solution of KOH.

[0045] A size and shape of the recess 30A will be determined by the openings in the etch mask used to etch the substrate 20A. The recess 30A is sized and shaped to retain and electrically engage a single bumped contact 12. A representative diameter, or width, of the recess 30A can be from 2 mils to 50 mils or more. This diameter can be less than a diameter of the bumped contact 12 so that only portions thereof will be contacted. A depth of the recess 30A can be equal to or less than the diameter thereof. A pitch or spacing of the recess 30A relative to adjacent recesses 30A will exactly match a pitch P (FIG. 1A) of the bumped contacts 12.

[0046] Referring to FIG. 3B, an alternate embodiment first contact 22B is illustrated. The alternate embodiment first contact 22B is substantially identical in construction to the previously described first contact 22A. However, rather than being formed in a substrate 20B, the first contact 22B is formed in a compliant layer 40 formed on the substrate 20B. The compliant layer 40 can comprise a polymer such as polyimide, photoimageable polyimide, polyester, epoxy, urethane, polystyrene, silicone or polycarbonate deposited to a desired thickness.

[0047] Recesses for the first contact 22B can be etched by forming a mask (not shown) on the compliant layer 40, such as a photopatterned resist mask, and then etching the compliant layer 40 through openings in the mask, using an etchant. With the compliant layer 40 comprising polyimide, a suitable etchant for performing the etch process comprises a solution of TMAH (tetramethylammonium hydroxide). If the compliant layer 40 comprises a photoimageable polyimide, an etch mask is not required, as the photoimageable material can be patterned by exposure to UV and then developed using a suitable developing solution.

[0048] Referring to FIG. 3C, another alternate embodiment first contact 22C is illustrated. The first contact 22C comprises a conductive polymer donut 42, and a contact pad 44 which provides a bonding surface for the polymer donut 42. The contact pad 44 is in electrical communication with a conductor 26C on a substrate 20C. Preferably the contact pad 44 comprises a non-oxidizing metal, such as gold or palladium. The non-oxidizing contact pad 44 forms a “touch contact” surface, and provides a low resistance electrical path between the conductor 26C and the conductive polymer donut 42.

[0049] The conductive polymer donut 42 comprises a conductive elastomeric material deposited on the contact pad 44 in a desired size and shape. Suitable materials the conductive polymer donut 42 include metal filled adhesives (e.g., silver filled silicone) that are conductive in any direction. Alternately, the conductive polymer donut 42 can comprise an anisotropic adhesive that are conductive in only one direction. For example, Z-axis anisotropic adhesives are filled with conductive dendritic particles to a low level such that the particles do not contact each other in the X and Y planes. However, compression of the anisotropic adhesive provides an electrical path in the Z-direction. Curing is typically accomplished by compression of the conductive adhesive along the direction of conduction.

[0050] The conductive polymer donut 42 can be formed by screen printing, stenciling, or otherwise dispensing, a viscous conductive elastomeric material in a required size and shape. In the illustrative embodiment the conductive polymer donut 42 has an inside diameter sized and shaped to retain the bumped contact 12. The conductive elastomeric material can be provided in either a thermal plastic configuration or a thermal setting configuration. Thermal plastic conductive elastomers are heated to soften for use and then cooled for curing. Thermal setting conductive elastomers are viscous at room temperature but require heat curing at temperatures from 100-300° C. for from several minutes to an hour or more. Suitable conductive elastomers for forming the conductive polymer donut 42 include: materials containing dendritic silver flakes; “X-POLY” and “Z-POXY”, by A. I. Technology, Trenton, N.J.; and “SHELL-ZAC”, by Sheldahl, Northfield, Minn. Other suitable conductive elastomers are also sold by 3M, St. Paul, Minn.

[0051] During a test procedure, the conductive polymer donut 42 can be placed in compression during contact with the bumped contact 12, such that metal particles 46 within the conductive elastomeric material penetrate oxide layers covering the bumped contacts 12. In addition, the conductive materials used to form the conductive polymer donut 42 are naturally resilient and possess compliant characteristics. This compliancy can also provide force for pressing the metal particles 46 into the bumped contacts 12, and for accommodating variations in the z-direction locations of the bumped contacts 12.

[0052] Referring to FIG. 3E, another alternate embodiment first contact 22D is illustrated. The first contact 22D comprises a stepped recess 30D formed in a substrate 20D and at least partially covered with a conductive layer 32D. The conductive layer 32D is in electrical communication with a conductor 26D as previously described. In addition, in this embodiment the substrate 20D comprises an electrically insulating material, such as ceramic or plastic, such that insulating layers are not required. During a test procedure the bumped contact 12 can be pressed into the stepped recess 30D. Deformation of the bumped contact 12 into the stepped recess 30D helps to compensate for variations in the size and planarity of the bumped contact 12.

[0053] Referring to FIG. 3F, another alternate embodiment first contact 22E is illustrated. The first contact 22E comprise a concave recess 30E formed in an electrically insulating substrate 20E. The recess 30E has a size and shape that substantially matches a size and shape of the bumped contact 12. In addition, the recess 30E is at least partially covered with a conductive layer 32E in electrical communication with a conductor 26E.

[0054] Other types of contacts configured to make non-bonded, temporary electrical connections with bumped contacts 12 are described in the following U.S. Patent Applications, which are incorporated herein by reference:

[0055] U.S. patent application Ser. No. 08/829,193, entitled “Interconnect Having Recessed Contact Members With Penetrating Blades For Testing Semiconductor Dice And Packages With Contact Bumps”;

[0056] U.S. patent application Ser. No. 08/823,490, entitled “Method, Apparatus And System For Testing Bumped Semiconductor Components”; and

[0057] U.S. patent application Ser. No. 08/867,551, entitled “Interconnect For Making Temporary Electrical Connections With Bumped Semiconductor Components”.

[0058] Referring to FIG. 4A, a second contact 24A is illustrated. The second contact 24A comprises a projection formed on a substrate 20F. In this embodiment the substrate 20F comprises an etchable material such as silicon, and the second contact 24A can be formed using an etching process.

[0059] The second contact 24A is sized and shaped to electrically engage the planar contacts 14 on the component 10, as the first contacts 22 electrically engage the bumped contacts 12 on the component 10. In addition, the second contact 24A has a height selected to space the component 10 from the interconnect 18 such that the bumped contacts 12 do not deform excessively during engagement by the first contacts 22. Accordingly, the height of the second contact 24A is approximately equal, to but less than, the height of the bumped contacts 12. A representative height for the second contact 24A can be from 2 mils to 50 mils or more.

[0060] The second contact 24A includes penetrating projections 48 for penetrating the planar contacts 14 on the component 10 to a self limiting penetration depth. The penetrating projections 48 are at least partially covered with a conductive layer 32F in electrical communication with a conductor 26F and with an input/output pad 28F. In addition, a wire 36F is bonded to the input/output pad 28F, and an electrically insulating layer 38F electrically insulates the substrate 20F. The second contact 24A can be formed as described in U.S. Pat. No. 5,686,317, entitled “Method For Forming An Interconnect Having A Penetration Limited Contact Structure For Establishing A Temporary Electrical Connection With A Semiconductor Die”, which is incorporated herein by reference.

[0061] Referring to FIG. 4B, an alternate embodiment second contact 24B is illustrated. The second contact 24B comprises a conductive polymer projection formed on a contact pad 44B. The conductive polymer projection can comprise an isotropic or anisotropic elastomer as previously described for conductive polymer donut 42 (FIG. 3C). The contact pad 44B can comprise a non-oxidizing metal such as gold or palladium as previously described for contact pad 44 (FIG. 3D).

[0062] In the illustrative embodiment, the second contact 24B is generally conically shaped and has a planar tip portion. As will be further described, this shape can be achieved using a screen printing process. If required, the tip portion of the second contact 24B can be planarized such that a height “H” of the second contacts 24B on the interconnect 18 is uniform. Planarization can be accomplished by contact with a planar surface during the curing process. Additionally, the second contacts 24B can be placed in compression during the curing process by contact with a planar surface. A representative height “H” for the second contact 24B can be from 1-20 mils. A representative diameter at the base of the second contact 24B can be from 1-40 mils.

[0063] As shown in FIG. 4B, the second contact 24B can be used to establish a temporary electrical connection with the planar contact 14 of the component 10. In addition, the second contact 24B can be placed in compression during contact with the planar contact 14, such that metal particles 46B within the second contact 24B penetrate oxide layers covering the planar contact 14. In addition, the conductive material used to form the second contact 24B is naturally resilient such that the contact 24B will possess compliant characteristics. This compliancy can also provide force for pressing the metal particles 46B into the planar contact 14, and for accommodating variations in the z-direction locations of the planar contact 14.

[0064] The contact pad 44B for the second contact 24B is in electrical communication with a conductor 26G substantially as previously described. In addition, an insulating layer 38G electrically insulates the contact pad 44B and conductor 26G from a bulk of the substrate 20G. However, in this embodiment a conductive via 50 is formed in the substrate 20G and electrically connects the conductor 26G to a terminal contact 52 formed on a backside of the substrate 20G. The conductive via 50 can be formed using a laser machining process as described in U.S. patent application Ser. No. 08/993,965 entitled “Semiconductor Interconnect Having Laser Machined Contacts”, which is incorporated herein by reference. This type of conductive via can also be used to electrically connect the first contacts 22 (FIG. 2) to terminal contacts on the interconnect 18. For example, in the first contact 22A of FIG. 3A, a conductive via can be located along a center line of the recess 30A substantially as shown in FIG. 7B.

[0065] Referring to FIG. 4D, an alternate embodiment second contact 24C is illustrated. In this embodiment a planar contact 14A on the component 10 comprises a “dummy contact” that has no electrical function. The second contact 24C mechanically engages the planar contact 14A to provide support, such that the component 10 does not tilt during electrical engagement of the bumped contacts 12 (FIG. 1A) by the first contacts 22 (FIG. 2). In addition, the second contact 24C maintains a “stand off” spacing between the interconnect 18 and the component 10 such that the bumped contacts 12 (FIG. 1A) on the component 10 are not excessively deformed by the first contacts 22 (FIG. 2). In the illustrative embodiment, two second contacts 24C are provided on either side of the first contacts 22. However, a greater number of second contacts 24C can be provided, and located on different portions of the interconnect 10 to perform a required support function.

[0066] In this embodiment, the second contact 24C comprises a generally pyramidally shaped projection formed on a substrate 20H. In addition, the second contact 24C includes a planar tip portion which supports and prevents tilting of the component 10. A representative value for the width, and the height of the second contact 24C can be from 1-50 mils or greater.

[0067] Also in this embodiment the substrate 20H can comprise silicon and the second contact 24C can be formed by anisotropically etching the substrate 20H using an etchant such as KOH as previously described. The substrate 20H can also includes an insulating layer 38H as previously described. In addition, the second contact 24C includes a cushioning layer 54 having a thickness of “T”. The cushioning layer 54 can comprise a polymer material, such as polyimide or silicone, deposited on a tip portion of the second contact 24C to the thickness T. A representative value for the thickness T can be from 1-5 mils. Alternately the cushioning layer 54 can comprise a separate member such as a gasket, or a piece of tape, attached to the tip portion of the second contact 24C. As another alternative, the second contact 24C can comprise a polymer material having compliant characteristics. Suitable polymers include polyimide, silicone and butyl rubber. In this case the cushioning layer 54 can be eliminated.

[0068] Referring to FIGS. 5A and 5B, a test carrier 60 constructed with the interconnect 18 is illustrated. The carrier 60 is adapted to temporarily package the semiconductor component 10 for testing and burn-in. In addition, the test carrier 60 is adapted to bias the component 10 against the interconnect 18.

[0069] The carrier 60 includes a base 62, and the interconnect 18 mounted to the base 62. The carrier 60 also includes a force applying mechanism 64 comprising a biasing member 66, a pressure plate 68, and a clamp 70. In addition, the carrier 60 includes a plurality of terminal leads 72 in electrical communication with the interconnect 18.

[0070] The terminal leads 72 are adapted for electrical communication with a test apparatus 74 (FIG. 5B), such as a burn-in board, and test circuitry 76 (FIG. 5B). The test circuitry 76 generates test signals, and transmits the test signals to the terminal leads 72, and through the interconnect 18 to the component 10. The test circuitry 76 also analyzes the resultant test signals transmitted from the component 10. The carrier 60, test apparatus 74, and test circuitry 76 form a test system 78 which permits various electrical characteristics of the component 10 to be evaluated.

[0071] In the illustrative embodiment, the terminal leads 72 comprise pins formed in a pin grid array (PGA) on a backside of the base 62. Alternately, other configurations for the terminal leads 72 can be provided. For example, the carrier base 62 can include ball contacts in a ball grid array (BGA) or fine ball grid array (FBGA).

[0072] Also in the illustrative embodiment, the base 62 comprises a laminated ceramic material. A ceramic lamination process can be used to fabricate the base 62 with a desired geometry, and with metal features such as internal conductors and external pads. U.S. Pat. No. 5,519,332, entitled “Carrier For Testing An Unpackaged Semiconductor Die”, which is incorporated herein by reference, describes a ceramic lamination process for fabricating the base 62.

[0073] Alternately, rather than ceramic, the base 62 can comprise plastic and the metal features formed using a 3-D molding process. Previously cited U.S. Pat. No. 5,519,332 describes a 3-D molding process for fabricating the base 62.

[0074] Rather than ceramic or plastic, the base can also comprise a glass reinforced plastic (e.g., FR-4) similar to materials used for circuit boards. In this case, conventional plastic substrate fabrication processes, as described in Ball Grid Array Technology, by John H. Lau, McGraw-Hill Inc. (1995), can be used for fabricating the base 62.

[0075] The base 62 includes internal conductors (not shown) in electrical communication with the terminal leads 72. As will be further explained, bond wires 36 (FIG. 5B) are wire bonded to bond pads on the base 62 in electrical communication with the internal conductors in the base 62. The bond wires 36 (FIG. 5B) are also wire bonded to the input/output pads 28 (FIG. 2) on the interconnect 18, and establish electrical communication between the terminal leads 72 on the base 62, and the first contacts 22 (FIG. 2) and the second contacts 24 (FIG. 2) on the interconnect 18.

[0076] The base 62 also includes a clamp ring 80 for attaching the clamp 70 of the force applying mechanism 64 to the base 62 during assembly of the carrier 60. The clamp ring 80 is attached to the base 62, and as shown in FIG. 5B, has a frame-like configuration. As also shown in FIG. 5B, the clamp ring 80 includes grooves 82 wherein the clamp 70 is attached. In the illustrative embodiment, the clamp ring 80 comprises metal, and is attached to the base 62 using a brazing process. One suitable metal for the clamp ring 80 comprises “KOVAR” coated with gold. The base 62 can include bonding features, such as metal pads, for attaching the clamp ring 80.

[0077] The clamp 70 comprises a flexible bridge-like structure formed of a resilient material such as steel. The clamp 70 includes tabs 84 that physically engage the grooves 82 on the clamp ring 80. In addition, the clamp 70 includes opposed sides 86 movable towards one another to permit engagement of the tabs 84 on the clamp 70, with the grooves 82 on the clamp ring 80. The clamp 70 also includes an opening 88 which provides access to the component 10 for a vacuum assembly tool during assembly of the carrier 60. The biasing member 66 also includes an opening 90, and the pressure plate 68 includes an opening 92 for the vacuum assembly tool. A pair of openings 94 (FIG. 5A) can also be provided on the clamp 70 for manipulation of the clamp 70 by the vacuum assembly tool during assembly of the carrier 60.

[0078] The pressure plate 68 can comprise a metal, a plastic, or a ceramic material. A peripheral shape and thickness of the pressure plate 68 can be selected as required.

[0079] Assembly of the carrier can be accomplished manually, or using an automated assembly apparatus. U.S. Pat. No. 5,796,264, entitled “Apparatus For Manufacturing Known Good Semiconductor Dice”, which is incorporated herein by reference, describes a method and apparatus for assembling the carrier. In the illustrative embodiment, alignment of the component 10 with the interconnect 18 can be performed using an optical alignment technique. Such an optical alignment technique is described in the above cited U.S. Pat. No. 5,796,264. Alignment of the component 10 with the interconnect 18 can also be performed using a mechanical alignment fence on the base 62, or on the interconnect 18. as will be hereinafter described.

[0080] Using the carrier 60 the component 10 can be tested as required. In the assembled carrier, the first contacts 22 (FIG. 2) on the interconnect 18 electrically engage the bumped contacts 12 on the component 10. In addition, the second contacts 24 (FIG. 2) on the interconnect 18 electrically engage the planar contacts 24 on the component 10. Also the component 10 can be provided with dummy contacts 14A (FIG. 4D) and the interconnect 18 can be provided with contacts 24C (FIG. 4D) to prevent tilting and flexure of the component 10 during electrical engagement thereof. Further, the contacts 24C provide a stand off support such that the contact bumps 12 are not excessively deformed by contact with the first contacts 22 on the interconnect 18.

[0081] Referring to FIGS. 6A-6C an alternate embodiment interconnect 18A is illustrated. The interconnect 18A is substantially similar in construction to interconnect 18 (FIG. 2) but also includes a polymer alignment member 96. The polymer alignment member 96 is adapted to align the bumped contacts 12 on the component 10 to the first contacts 22 on the interconnect 18A.

[0082] Preferably the alignment member 96 is formed of a photoimageable material such that patterning can be accomplished using a photolithographic process. One suitable polymer for forming the alignment member 96 comprises a negative tone resist, which is blanket deposited to a desired thickness, exposed, developed and then cured. A suitable resist formulation is sold by Shell Chemical under the trademark “EPON RESIN SU-8”. Such a resist can be deposited to a thickness of from about 5-50 mils. A conventional resist coating apparatus, such as a spin coater, can be used to deposit the resist onto the surface of the interconnect 18A. The deposited resist can then be “prebaked” at about 95° C. for about 15 minutes and exposed in a desired pattern using a conventional UV aligner with a dose of about 165 mJ/cm2. Developing can be accomplished with a solution of PGMEA (propyleneglycol-monomethylether-acetate). This can be followed by a hard bake at about 200° C. for about 30 minutes. Another suitable material for forming the alignment member 96 is a photoimageable polyimide.

[0083] The alignment member 96 includes a peripheral alignment opening 98 sized and shaped to contact the peripheral edges of the semiconductor component 10. This provides coarse alignment of the bumped contacts 12 on the component 10 to the first contacts 22. As used herein, the term “coarse alignment” refers to a first alignment stage in which a registration between the bumped contacts 12 and the first contacts 22 is from about 1 mil to 6 mils.

[0084] In addition to the alignment opening 98, the alignment member 96 includes a connecting segment 102 having alignment openings 100 configured to provide fine alignment of individual bumped contacts 12 on the component 10 to individual first contacts 22 on the interconnect 18A. As used herein, the term “fine alignment” refers to a second alignment stage in which a registration between the bumped contacts 12 and the first contacts 22 is from about 1 mil to 3 mils. A representative diameter for the alignment openings 100 for 12 mil diameter bumped contacts 12 can be from 13 mils to 15 mils. Preferably connecting segment 102 has a thickness that is less than an average height of the bumped contacts 12. This thickness is preferably from about 3 mils to 7 mils. A remainder of the alignment member 96 has a thickness approximately equal to a thickness of the component.

[0085] Alternately rather than a deposited polymer the alignment member can comprise a separate plate attached to the interconnect 18 or to the carrier base 62 (FIG. 5B). Suitable materials for forming a separate alignment member include silicon, ceramic, plastic, glass filled resin and photosensitive glass. In addition, U.S. Pat. No. 5,559,444 entitled “Method And Apparatus For Testing Unpackaged Semiconductor Dice”, which is incorporated herein by reference, describes a method for fabricating an alignment member.

[0086] Referring to FIGS. 7A and 7B, an alternate embodiment test carrier 60W is illustrated. The test carrier 60W is configured to temporarily package a wafer level component 10W, such as a wafer containing multiple dice, or a panel containing multiple chip scale packages for testing. The test carrier 60W comprises a base 62W, an elastomeric biasing member 66W, an alignment member 96W, and a cover 104.

[0087] The base 62W includes first contacts 22W for electrically engaging bumped contacts 12 on the component 10W, and second contacts 24W for electrically engaging planar contacts 14 on the component 10W. The first contacts 22W are formed substantially as previously described for first contacts 22A (FIG. 3A). The second contacts 24W are formed substantially as previously described for second contacts 24B (FIG. 4B).

[0088] The base 62W also includes conductive vias 50W, and terminal contacts 52W in electrical communication with the first contacts 22W. In this embodiment the conductive vias 50W are coincident to a center line of the first contacts 22W. Other conductive vias (not shown) electrically connect the second contacts 24W to the terminal contacts 52W.

[0089] The alignment member 96W includes an alignment opening 100W which functions substantially as previously described for alignment opening 98 (FIG. 6B) on alignment member 96 (FIG. 6B). The elastomeric biasing member 66W is attached to the cover 104 using an adhesive, such as silicone. In addition, the elastomeric biasing member 66W and cover 104 include a vacuum opening 106. The vacuum opening 106 can be used to apply a vacuum to the component 10W for holding the component 10W against the elastomeric biasing member 66W during assembly of the test carrier 60W. In addition, clips 108 are provided for securing the cover 104 to the base 62W.

[0090] The test carrier 60W is configured for placement on a test apparatus 74W, such as a burn-in board, in electrical communication with test circuitry 76W. The test carrier 60W, test apparatus 74W, and test circuitry 76W form a test system 78W for testing the component 10W.

[0091] Thus the invention provides an improved interconnect for testing semiconductor components having both bumped and planar contacts. Also provided are improved test carriers and test systems incorporating the interconnect. While the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6528407 *Oct 6, 2000Mar 4, 2003Stmicroelectronics S.A.Process for producing electrical-connections on a semiconductor package, and semiconductor package
US6992001 *May 8, 2003Jan 31, 2006Kulicke And Soffa Industries, Inc.Screen print under-bump metalization (UBM) to produce low cost flip chip substrate
US8823166 *Aug 30, 2010Sep 2, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Pillar bumps and process for making same
US20120049346 *Aug 30, 2010Mar 1, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Pillar Bumps and Process for Making Same
Classifications
U.S. Classification257/737, 257/773, 257/734
International ClassificationH05K1/11, G01R1/073, G01R1/04, G01R1/067, H05K3/32
Cooperative ClassificationG01R1/0408, H05K1/11, G01R1/07314, H05K3/325, G01R1/06733
European ClassificationG01R1/067C3, G01R1/073B2
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